diff --git a/lib/cretonne/src/regalloc/coalescing.rs b/lib/cretonne/src/regalloc/coalescing.rs
index 10d0df2e62..3b9d6d03bb 100644
--- a/lib/cretonne/src/regalloc/coalescing.rs
+++ b/lib/cretonne/src/regalloc/coalescing.rs
@@ -1,9 +1,9 @@
-//! Constructing conventional SSA form.
+//! Constructing Conventional SSA form.
 //!
-//! Conventional SSA form is a subset of SSA form where any (transitively) phi-related values do
-//! not interfere. We construct CSSA by building virtual registers that are as large as possible
-//! and inserting copies where necessary such that all argument values passed to an EBB parameter
-//! will belong to the same virtual register as the EBB parameter value itself.
+//! Conventional SSA (CSSA) form is a subset of SSA form where any (transitively) phi-related
+//! values do not interfere. We construct CSSA by building virtual registers that are as large as
+//! possible and inserting copies where necessary such that all argument values passed to an EBB
+//! parameter will belong to the same virtual register as the EBB parameter value itself.
 
 use cursor::{Cursor, EncCursor};
 use dbg::DisplayList;
@@ -103,7 +103,7 @@ impl Coalescing {
         self.backedges.clear();
     }
 
-    /// Convert `func` to conventional SSA form and build virtual registers in the process.
+    /// Convert `func` to Conventional SSA form and build virtual registers in the process.
     pub fn conventional_ssa(
         &mut self,
         isa: &TargetIsa,
diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 2de41e67c6..d7ab5dd0f3 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -23,7 +23,7 @@
 //!    operands are allowed to read spilled values, but each such instance must be counted as using
 //!    a register.
 //!
-//! 5. The code must be in conventional SSA form. Among other things, this means that values passed
+//! 5. The code must be in Conventional SSA form. Among other things, this means that values passed
 //!    as arguments when branching to an EBB must belong to the same virtual register as the
 //!    corresponding EBB argument value.
 //!
diff --git a/lib/cretonne/src/regalloc/context.rs b/lib/cretonne/src/regalloc/context.rs
index 765ecf155c..a8284a9579 100644
--- a/lib/cretonne/src/regalloc/context.rs
+++ b/lib/cretonne/src/regalloc/context.rs
@@ -90,7 +90,7 @@ impl Context {
             verify_liveness(isa, func, cfg, &self.liveness)?;
         }
 
-        // Pass: Coalesce and create conventional SSA form.
+        // Pass: Coalesce and create Conventional SSA form.
         self.coalescing.conventional_ssa(
             isa,
             func,