diff --git a/Cargo.lock b/Cargo.lock
index f908113083..60a17aa88a 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -548,9 +548,11 @@ dependencies = [
 name = "cranelift-codegen"
 version = "0.94.0"
 dependencies = [
+ "anyhow",
  "arrayvec",
  "bincode",
  "bumpalo",
+ "capstone",
  "cranelift-bforest",
  "cranelift-codegen-meta",
  "cranelift-codegen-shared",
diff --git a/cranelift/Cargo.toml b/cranelift/Cargo.toml
index 03af48c318..7603fd2611 100644
--- a/cranelift/Cargo.toml
+++ b/cranelift/Cargo.toml
@@ -20,7 +20,7 @@ harness = false
 
 [dependencies]
 cfg-if = "1.0"
-cranelift-codegen = { workspace = true }
+cranelift-codegen = { workspace = true, features = ["disas"] }
 cranelift-entity = { workspace = true }
 cranelift-interpreter = { workspace = true }
 cranelift-reader = { workspace = true }
diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml
index 19a87930e9..42293f6b76 100644
--- a/cranelift/codegen/Cargo.toml
+++ b/cranelift/codegen/Cargo.toml
@@ -14,7 +14,9 @@ edition.workspace = true
 
 [dependencies]
 arrayvec = "0.7"
+anyhow = { workspace = true, optional = true }
 bumpalo = "3"
+capstone = { workspace = true, optional = true }
 cranelift-codegen-shared = { path = "./shared", version = "0.94.0" }
 cranelift-entity = { workspace = true }
 cranelift-bforest = { workspace = true }
@@ -55,6 +57,10 @@ std = []
 # compatibility as a no-op.
 core = []
 
+# Enable the `to_capstone` method on TargetIsa, for constructing a Capstone
+# context, and the `disassemble` method on `MachBufferFinalized`.
+disas = ["anyhow", "capstone"]
+
 # This enables some additional functions useful for writing tests, but which
 # can significantly increase the size of the library.
 testing_hooks = []
diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs
index 6f6f30e11a..80caf350bd 100644
--- a/cranelift/codegen/src/isa/aarch64/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/mod.rs
@@ -90,7 +90,7 @@ impl TargetIsa for AArch64Backend {
         Ok(CompiledCodeStencil {
             buffer,
             frame_size,
-            disasm: emit_result.disasm,
+            vcode: emit_result.disasm,
             value_labels_ranges,
             sized_stackslot_offsets,
             dynamic_stackslot_offsets,
@@ -195,6 +195,22 @@ impl TargetIsa for AArch64Backend {
         // 4-byte alignment.
         32
     }
+
+    #[cfg(feature = "disas")]
+    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
+        use capstone::prelude::*;
+        let mut cs = Capstone::new()
+            .arm64()
+            .mode(arch::arm64::ArchMode::Arm)
+            .build()?;
+        // AArch64 uses inline constants rather than a separate constant pool right now.
+        // Without this option, Capstone will stop disassembling as soon as it sees
+        // an inline constant that is not also a valid instruction. With this option,
+        // Capstone will print a `.byte` directive with the bytes of the inline constant
+        // and continue to the next instruction.
+        cs.set_skipdata(true)?;
+        Ok(cs)
+    }
 }
 
 impl fmt::Display for AArch64Backend {
diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs
index 3d1e6f977c..03f6119170 100644
--- a/cranelift/codegen/src/isa/mod.rs
+++ b/cranelift/codegen/src/isa/mod.rs
@@ -307,6 +307,12 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
     {
         Arc::new(self)
     }
+
+    /// Generate a `Capstone` context for disassembling bytecode for this architecture.
+    #[cfg(feature = "disas")]
+    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
+        Err(capstone::Error::UnsupportedArch)
+    }
 }
 
 /// Methods implemented for free for target ISA!
diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs
index 2880425203..848db2169f 100644
--- a/cranelift/codegen/src/isa/riscv64/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/mod.rs
@@ -91,7 +91,7 @@ impl TargetIsa for Riscv64Backend {
         Ok(CompiledCodeStencil {
             buffer,
             frame_size,
-            disasm: emit_result.disasm,
+            vcode: emit_result.disasm,
             value_labels_ranges,
             sized_stackslot_offsets,
             dynamic_stackslot_offsets,
@@ -169,6 +169,20 @@ impl TargetIsa for Riscv64Backend {
     fn function_alignment(&self) -> u32 {
         4
     }
+
+    #[cfg(feature = "disas")]
+    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
+        use capstone::prelude::*;
+        let mut cs = Capstone::new()
+            .riscv()
+            .mode(arch::riscv::ArchMode::RiscV64)
+            .build()?;
+        // Similar to AArch64, RISC-V uses inline constants rather than a separate
+        // constant pool. We want to skip dissasembly over inline constants instead
+        // of stopping on invalid bytes.
+        cs.set_skipdata(true)?;
+        Ok(cs)
+    }
 }
 
 impl fmt::Display for Riscv64Backend {
diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs
index 4e4ff5d44c..61b0f0c36f 100644
--- a/cranelift/codegen/src/isa/s390x/mod.rs
+++ b/cranelift/codegen/src/isa/s390x/mod.rs
@@ -87,7 +87,7 @@ impl TargetIsa for S390xBackend {
         Ok(CompiledCodeStencil {
             buffer,
             frame_size,
-            disasm: emit_result.disasm,
+            vcode: emit_result.disasm,
             value_labels_ranges,
             sized_stackslot_offsets,
             dynamic_stackslot_offsets,
@@ -170,6 +170,19 @@ impl TargetIsa for S390xBackend {
     fn function_alignment(&self) -> u32 {
         4
     }
+
+    #[cfg(feature = "disas")]
+    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
+        use capstone::prelude::*;
+        let mut cs = Capstone::new()
+            .sysz()
+            .mode(arch::sysz::ArchMode::Default)
+            .build()?;
+
+        cs.set_skipdata(true)?;
+
+        Ok(cs)
+    }
 }
 
 impl fmt::Display for S390xBackend {
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index d43e58d31a..2da9cc3d42 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -84,7 +84,7 @@ impl TargetIsa for X64Backend {
         Ok(CompiledCodeStencil {
             buffer,
             frame_size,
-            disasm: emit_result.disasm,
+            vcode: emit_result.disasm,
             value_labels_ranges,
             sized_stackslot_offsets,
             dynamic_stackslot_offsets,
@@ -171,6 +171,16 @@ impl TargetIsa for X64Backend {
     fn function_alignment(&self) -> u32 {
         16
     }
+
+    #[cfg(feature = "disas")]
+    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
+        use capstone::prelude::*;
+        Capstone::new()
+            .x86()
+            .mode(arch::x86::ArchMode::Mode64)
+            .syntax(arch::x86::ArchSyntax::Att)
+            .build()
+    }
 }
 
 impl fmt::Display for X64Backend {
diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs
index 83c0701e6b..072c32a9d0 100644
--- a/cranelift/codegen/src/machinst/mod.rs
+++ b/cranelift/codegen/src/machinst/mod.rs
@@ -287,7 +287,7 @@ pub struct CompiledCodeBase<T: CompilePhase> {
     /// Size of stack frame, in bytes.
     pub frame_size: u32,
     /// Disassembly, if requested.
-    pub disasm: Option<String>,
+    pub vcode: Option<String>,
     /// Debug info: value labels to registers/stackslots at code offsets.
     pub value_labels_ranges: ValueLabelsRanges,
     /// Debug info: stackslots to stack pointer offsets.
@@ -317,7 +317,7 @@ impl CompiledCodeStencil {
         CompiledCode {
             buffer: self.buffer.apply_base_srcloc(params.base_srcloc()),
             frame_size: self.frame_size,
-            disasm: self.disasm,
+            vcode: self.vcode,
             value_labels_ranges: self.value_labels_ranges,
             sized_stackslot_offsets: self.sized_stackslot_offsets,
             dynamic_stackslot_offsets: self.dynamic_stackslot_offsets,
@@ -340,6 +340,71 @@ impl<T: CompilePhase> CompiledCodeBase<T> {
     pub fn code_buffer(&self) -> &[u8] {
         self.buffer.data()
     }
+
+    /// Get the disassembly of the buffer, using the given capstone context.
+    #[cfg(feature = "disas")]
+    pub fn disassemble(
+        &self,
+        params: Option<&crate::ir::function::FunctionParameters>,
+        cs: &capstone::Capstone,
+    ) -> Result<String, anyhow::Error> {
+        use std::fmt::Write;
+
+        let mut buf = String::new();
+
+        let relocs = self.buffer.relocs();
+        let traps = self.buffer.traps();
+        let labels = self.bb_starts.as_slice();
+
+        let insns = cs.disasm_all(self.buffer.data(), 0x0).map_err(map_caperr)?;
+        for i in insns.iter() {
+            if let Some((n, off)) = labels
+                .iter()
+                .copied()
+                .enumerate()
+                .find(|(_, val)| *val == i.address() as u32)
+            {
+                writeln!(buf, "block{}: ; offset 0x{:x}", n, off)?;
+            }
+
+            write!(buf, "  ")?;
+
+            let op_str = i.op_str().unwrap_or("");
+            if let Some(s) = i.mnemonic() {
+                write!(buf, "{}", s)?;
+                if !op_str.is_empty() {
+                    write!(buf, " ")?;
+                }
+            }
+
+            write!(buf, "{}", op_str)?;
+
+            let end = i.address() + i.bytes().len() as u64;
+            let contains = |off| i.address() <= off && off < end;
+
+            if let Some(reloc) = relocs.iter().find(|reloc| contains(reloc.offset as u64)) {
+                write!(
+                    buf,
+                    " ; reloc_external {} {} {}",
+                    reloc.kind,
+                    reloc.name.display(params),
+                    reloc.addend,
+                )?;
+            }
+
+            if let Some(trap) = traps.iter().find(|trap| contains(trap.offset as u64)) {
+                write!(buf, " ; trap: {}", trap.code)?;
+            }
+
+            writeln!(buf)?;
+        }
+
+        return Ok(buf);
+
+        fn map_caperr(err: capstone::Error) -> anyhow::Error {
+            anyhow::format_err!("{}", err)
+        }
+    }
 }
 
 /// Result of compiling a `FunctionStencil`, before applying `FunctionParameters` onto it.
diff --git a/cranelift/filetests/Cargo.toml b/cranelift/filetests/Cargo.toml
index 123c27ac30..7ed94698ce 100644
--- a/cranelift/filetests/Cargo.toml
+++ b/cranelift/filetests/Cargo.toml
@@ -10,7 +10,7 @@ publish = false
 edition.workspace = true
 
 [dependencies]
-cranelift-codegen = { workspace = true, features = ["testing_hooks"] }
+cranelift-codegen = { workspace = true, features = ["testing_hooks", "disas"] }
 cranelift-frontend = { workspace = true }
 cranelift-interpreter = { workspace = true }
 cranelift-native = { workspace = true }
diff --git a/cranelift/filetests/filetests/egraph/multivalue.clif b/cranelift/filetests/filetests/egraph/multivalue.clif
index 261fbc75ae..9c664643dc 100644
--- a/cranelift/filetests/filetests/egraph/multivalue.clif
+++ b/cranelift/filetests/filetests/egraph/multivalue.clif
@@ -1,6 +1,7 @@
 test compile precise-output
 set opt_level=speed
 set use_egraphs=true
+set machine_code_cfg_info=true
 target x86_64
 
 ;; We want to make sure that this compiles successfully, so we are properly
@@ -15,6 +16,7 @@ function u0:359(i64) -> i8, i8 system_v {
 		return v3, v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -22,4 +24,13 @@ function u0:359(i64) -> i8, i8 system_v {
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   callq 9 ; reloc_external CallPCRel4 u0:521 -4
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/egraph/not_a_load.clif b/cranelift/filetests/filetests/egraph/not_a_load.clif
index 99eefaccaa..0e5b46f14d 100644
--- a/cranelift/filetests/filetests/egraph/not_a_load.clif
+++ b/cranelift/filetests/filetests/egraph/not_a_load.clif
@@ -13,6 +13,7 @@ function u0:1302(i64) -> i64 system_v {
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -21,4 +22,18 @@ function u0:1302(i64) -> i64 system_v {
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rdi), %rax ; trap: heap_oob
+;   movq %rax, %rcx
+;   addq %rdi, %rcx
+;   lock cmpxchgq %rcx, (%rdi) ; trap: heap_oob
+;   jne 7
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/amodes.clif b/cranelift/filetests/filetests/isa/aarch64/amodes.clif
index 7645c98413..e91bf804aa 100644
--- a/cranelift/filetests/filetests/isa/aarch64/amodes.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/amodes.clif
@@ -10,9 +10,15 @@ block0(v0: i64, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   ldr w0, [x0, w1, SXTW]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr w0, [x0, w1, sxtw]
+;   ret
 
 function %f6(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -22,9 +28,15 @@ block0(v0: i64, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   ldr w0, [x0, w1, SXTW]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr w0, [x0, w1, sxtw]
+;   ret
 
 function %f7(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -35,10 +47,17 @@ block0(v0: i32, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   mov w3, w0
 ;   ldr w0, [x3, w1, UXTW]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, w0
+;   ldr w0, [x3, w1, uxtw]
+;   ret
 
 function %f8(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -51,12 +70,21 @@ block0(v0: i64, v1: i32):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   add x3, x0, #68
 ;   add x5, x3, x0
 ;   add x7, x5, x1, SXTW
 ;   ldr w0, [x7, w1, SXTW]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x3, x0, #0x44
+;   add x5, x3, x0
+;   add x7, x5, w1, sxtw
+;   ldr w0, [x7, w1, sxtw]
+;   ret
 
 function %f9(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -68,11 +96,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   add x4, x0, x2
 ;   add x6, x4, x1
 ;   ldr w0, [x6, #48]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x4, x0, x2
+;   add x6, x4, x1
+;   ldur w0, [x6, #0x30]
+;   ret
 
 function %f10(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -84,12 +120,21 @@ block0(v0: i64, v1: i64, v2: i64):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   movz x5, #4100
 ;   add x5, x5, x1
 ;   add x8, x5, x2
 ;   ldr w0, [x8, x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, #0x1004
+;   add x5, x5, x1
+;   add x8, x5, x2
+;   ldr w0, [x8, x0]
+;   ret
 
 function %f10() -> i32 {
 block0:
@@ -98,10 +143,17 @@ block0:
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #1234
 ;   ldr w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0x4d2
+;   ldr w0, [x0]
+;   ret
 
 function %f11(i64) -> i32 {
 block0(v0: i64):
@@ -111,10 +163,17 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   add x2, x0, #8388608
 ;   ldr w0, [x2]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x2, x0, #0x800, lsl #12
+;   ldr w0, [x2]
+;   ret
 
 function %f12(i64) -> i32 {
 block0(v0: i64):
@@ -124,10 +183,17 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sub x2, x0, #4
 ;   ldr w0, [x2]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub x2, x0, #4
+;   ldr w0, [x2]
+;   ret
 
 function %f13(i64) -> i32 {
 block0(v0: i64):
@@ -137,12 +203,21 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #51712
 ;   movk w3, w3, #15258, LSL #16
 ;   add x4, x3, x0
 ;   ldr w0, [x4]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #0xca00
+;   movk w3, #0x3b9a, lsl #16
+;   add x4, x3, x0
+;   ldr w0, [x4]
+;   ret
 
 function %f14(i32) -> i32 {
 block0(v0: i32):
@@ -151,10 +226,17 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtw x2, w0
 ;   ldr w0, [x2]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x2, w0
+;   ldr w0, [x2]
+;   ret
 
 function %f15(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -165,10 +247,17 @@ block0(v0: i32, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   sxtw x3, w0
 ;   ldr w0, [x3, w1, SXTW]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x3, w0
+;   ldr w0, [x3, w1, sxtw]
+;   ret
 
 function %f18(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -178,10 +267,17 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   movn w4, #4097
 ;   ldrsh x0, [x4]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w4, #-0x1002
+;   ldrsh x0, [x4]
+;   ret
 
 function %f19(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -191,10 +287,17 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   movz x4, #4098
 ;   ldrsh x0, [x4]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x4, #0x1002
+;   ldrsh x0, [x4]
+;   ret
 
 function %f20(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -204,11 +307,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   movn w4, #4097
 ;   sxtw x6, w4
 ;   ldrsh x0, [x6]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w4, #-0x1002
+;   sxtw x6, w4
+;   ldrsh x0, [x6]
+;   ret
 
 function %f21(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -218,11 +329,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   movz x4, #4098
 ;   sxtw x6, w4
 ;   ldrsh x0, [x6]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x4, #0x1002
+;   sxtw x6, w4
+;   ldrsh x0, [x6]
+;   ret
 
 function %i128(i64) -> i128 {
 block0(v0: i64):
@@ -231,11 +350,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x0
 ;   ldp x0, x1, [x5]
 ;   stp x0, x1, [x5]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x0
+;   ldp x0, x1, [x5]
+;   stp x0, x1, [x5]
+;   ret
 
 function %i128_imm_offset(i64) -> i128 {
 block0(v0: i64):
@@ -244,11 +371,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x0
 ;   ldp x0, x1, [x5, #16]
 ;   stp x0, x1, [x5, #16]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x0
+;   ldp x0, x1, [x5, #0x10]
+;   stp x0, x1, [x5, #0x10]
+;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
 block0(v0: i64):
@@ -257,11 +392,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x0
 ;   ldp x0, x1, [x5, #504]
 ;   stp x0, x1, [x5, #504]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x0
+;   ldp x0, x1, [x5, #0x1f8]
+;   stp x0, x1, [x5, #0x1f8]
+;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
 block0(v0: i64):
@@ -270,11 +413,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x0
 ;   ldp x0, x1, [x5, #-512]
 ;   stp x0, x1, [x5, #-512]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x0
+;   ldp x0, x1, [x5, #-0x200]
+;   stp x0, x1, [x5, #-0x200]
+;   ret
 
 function %i128_add_offset(i64) -> i128 {
 block0(v0: i64):
@@ -284,11 +435,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x0
 ;   ldp x0, x1, [x5, #32]
 ;   stp x0, x1, [x5, #32]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x0
+;   ldp x0, x1, [x5, #0x20]
+;   stp x0, x1, [x5, #0x20]
+;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
 block0(v0: i32):
@@ -298,6 +457,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtw x3, w0
 ;   mov x8, x0
@@ -305,6 +465,15 @@ block0(v0: i32):
 ;   sxtw x4, w8
 ;   stp x0, x1, [x4]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x3, w0
+;   mov x8, x0
+;   ldp x0, x1, [x3]
+;   sxtw x4, w8
+;   stp x0, x1, [x4]
+;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
 block0(v0: i64, v1: i32):
@@ -316,6 +485,7 @@ block0(v0: i64, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   add x4, x0, x1, SXTW
 ;   mov x11, x0
@@ -324,4 +494,14 @@ block0(v0: i64, v1: i32):
 ;   add x5, x11, x9, SXTW
 ;   stp x0, x1, [x5, #24]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x4, x0, w1, sxtw
+;   mov x11, x0
+;   mov x9, x1
+;   ldp x0, x1, [x4, #0x18]
+;   add x5, x11, w9, sxtw
+;   stp x0, x1, [x5, #0x18]
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif
index 164a6b5ba4..4f8669b161 100644
--- a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif
@@ -8,9 +8,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x0, x1
+;   ret
 
 function %f2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -18,9 +24,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub x0, x0, x1
+;   ret
 
 function %f3(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -28,9 +40,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   madd x0, x0, x1, xzr
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul x0, x0, x1
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -38,9 +56,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umulh x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umulh x0, x0, x1
+;   ret
 
 function %f5(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -48,9 +72,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smulh x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smulh x0, x0, x1
+;   ret
 
 function %f6(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -58,6 +88,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cbnz x1, 8 ; udf
 ;   adds xzr, x1, #1
@@ -65,6 +96,17 @@ block0(v0: i64, v1: i64):
 ;   b.vc 8 ; udf
 ;   sdiv x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cbnz x1, #8
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   cmn x1, #1
+;   ccmp x0, #1, #0, eq
+;   b.vc #0x18
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   sdiv x0, x0, x1
+;   ret
 
 function %f7(i64) -> i64 {
 block0(v0: i64):
@@ -73,10 +115,17 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w2, #2
 ;   sdiv x0, x0, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w2, #2
+;   sdiv x0, x0, x2
+;   ret
 
 function %f8(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -84,10 +133,18 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cbnz x1, 8 ; udf
 ;   udiv x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cbnz x1, #8
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   udiv x0, x0, x1
+;   ret
 
 function %f9(i64) -> i64 {
 block0(v0: i64):
@@ -96,10 +153,17 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #2
 ;   udiv x0, x0, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #2
+;   udiv x0, x0, x2
+;   ret
 
 function %f10(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -107,11 +171,20 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cbnz x1, 8 ; udf
 ;   sdiv x4, x0, x1
 ;   msub x0, x4, x1, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cbnz x1, #8
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   sdiv x4, x0, x1
+;   msub x0, x4, x1, x0
+;   ret
 
 function %f11(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -119,11 +192,20 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cbnz x1, 8 ; udf
 ;   udiv x4, x0, x1
 ;   msub x0, x4, x1, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cbnz x1, #8
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   udiv x4, x0, x1
+;   msub x0, x4, x1, x0
+;   ret
 
 function %f12(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -131,6 +213,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtw x3, w0
 ;   sxtw x5, w1
@@ -140,6 +223,19 @@ block0(v0: i32, v1: i32):
 ;   b.vc 8 ; udf
 ;   sdiv x0, x3, x5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x3, w0
+;   sxtw x5, w1
+;   cbnz x5, #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   cmn w5, #1
+;   ccmp w3, #1, #0, eq
+;   b.vc #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   sdiv x0, x3, x5
+;   ret
 
 function %f13(i32) -> i32 {
 block0(v0: i32):
@@ -148,11 +244,19 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtw x2, w0
 ;   movz w4, #2
 ;   sdiv x0, x2, x4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x2, w0
+;   mov w4, #2
+;   sdiv x0, x2, x4
+;   ret
 
 function %f14(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -160,12 +264,22 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mov w3, w0
 ;   mov w5, w1
 ;   cbnz x5, 8 ; udf
 ;   udiv x0, x3, x5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, w0
+;   mov w5, w1
+;   cbnz x5, #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   udiv x0, x3, x5
+;   ret
 
 function %f15(i32) -> i32 {
 block0(v0: i32):
@@ -174,11 +288,19 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mov w2, w0
 ;   movz w4, #2
 ;   udiv x0, x2, x4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w2, w0
+;   mov w4, #2
+;   udiv x0, x2, x4
+;   ret
 
 function %f16(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -186,6 +308,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtw x3, w0
 ;   sxtw x5, w1
@@ -193,6 +316,16 @@ block0(v0: i32, v1: i32):
 ;   sdiv x8, x3, x5
 ;   msub x0, x8, x5, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x3, w0
+;   sxtw x5, w1
+;   cbnz x5, #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   sdiv x8, x3, x5
+;   msub x0, x8, x5, x3
+;   ret
 
 function %f17(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -200,6 +333,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mov w3, w0
 ;   mov w5, w1
@@ -207,6 +341,16 @@ block0(v0: i32, v1: i32):
 ;   udiv x8, x3, x5
 ;   msub x0, x8, x5, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, w0
+;   mov w5, w1
+;   cbnz x5, #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_divz
+;   udiv x8, x3, x5
+;   msub x0, x8, x5, x3
+;   ret
 
 function %f18(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -214,9 +358,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, x1
+;   ret
 
 function %f19(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -224,9 +374,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, x1
+;   ret
 
 function %f20(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -234,9 +390,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, x1
+;   ret
 
 function %f21(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -244,9 +406,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   bic x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic x0, x0, x1
+;   ret
 
 function %f22(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -254,9 +422,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   orn x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn x0, x0, x1
+;   ret
 
 function %f23(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -264,9 +438,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x0, x0, x1
+;   ret
 
 function %f24(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -274,9 +454,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   orn x0, xzr, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn x0, x0
+;   ret
 
 function %f25(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -286,9 +472,15 @@ block0(v0: i32, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   sub w0, w1, w0, LSL 21
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub w0, w1, w0, lsl #21
+;   ret
 
 function %f26(i32) -> i32 {
 block0(v0: i32):
@@ -297,9 +489,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub w0, w0, #1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub w0, w0, #1
+;   ret
 
 function %f27(i32) -> i32 {
 block0(v0: i32):
@@ -308,9 +506,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, #1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, #1
+;   ret
 
 function %f28(i64) -> i64 {
 block0(v0: i64):
@@ -319,9 +523,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add x0, x0, #1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x0, #1
+;   ret
 
 function %f29(i64) -> i64 {
 block0(v0: i64):
@@ -330,10 +540,17 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #1
 ;   sub x0, xzr, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #1
+;   neg x0, x2
+;   ret
 
 function %f30(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -342,6 +559,7 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #1
 ;   and w4, w2, #7
@@ -349,6 +567,15 @@ block0(v0: i8x16):
 ;   dup v16.16b, w6
 ;   ushl v0.16b, v0.16b, v16.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #1
+;   and w4, w2, #7
+;   neg x6, x4
+;   dup v16.16b, w6
+;   ushl v0.16b, v0.16b, v16.16b
+;   ret
 
 function %add_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -356,10 +583,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   adds x0, x0, x2
 ;   adc x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adds x0, x0, x2
+;   adc x1, x1, x3
+;   ret
 
 function %sub_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -367,10 +601,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   subs x0, x0, x2
 ;   sbc x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   subs x0, x0, x2
+;   sbc x1, x1, x3
+;   ret
 
 function %mul_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -378,12 +619,21 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umulh x5, x0, x2
 ;   madd x7, x0, x3, x5
 ;   madd x1, x1, x2, x7
 ;   madd x0, x0, x2, xzr
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umulh x5, x0, x2
+;   madd x7, x0, x3, x5
+;   madd x1, x1, x2, x7
+;   mul x0, x0, x2
+;   ret
 
 function %add_mul_1(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -392,9 +642,15 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   madd w0, w1, w2, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   madd w0, w1, w2, w0
+;   ret
 
 function %add_mul_2(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -403,9 +659,15 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   madd w0, w1, w2, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   madd w0, w1, w2, w0
+;   ret
 
 function %msub_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -414,9 +676,15 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   msub w0, w1, w2, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msub w0, w1, w2, w0
+;   ret
 
 function %msub_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -425,9 +693,15 @@ block0(v0: i64, v1: i64, v2: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   msub x0, x1, x2, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msub x0, x1, x2, x0
+;   ret
 
 function %imul_sub_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -436,10 +710,17 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   madd w5, w1, w2, wzr
 ;   sub w0, w5, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul w5, w1, w2
+;   sub w0, w5, w0
+;   ret
 
 function %imul_sub_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -448,10 +729,17 @@ block0(v0: i64, v1: i64, v2: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   madd x5, x1, x2, xzr
 ;   sub x0, x5, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul x5, x1, x2
+;   sub x0, x5, x0
+;   ret
 
 function %srem_const (i64) -> i64 {
 block0(v0: i64):
@@ -460,11 +748,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w2, #2
 ;   sdiv x4, x0, x2
 ;   msub x0, x4, x2, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w2, #2
+;   sdiv x4, x0, x2
+;   msub x0, x4, x2, x0
+;   ret
 
 function %urem_const (i64) -> i64 {
 block0(v0: i64):
@@ -473,11 +769,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #2
 ;   udiv x4, x0, x2
 ;   msub x0, x4, x2, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #2
+;   udiv x4, x0, x2
+;   msub x0, x4, x2, x0
+;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
 block0(v0: i64):
@@ -486,6 +790,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movn x2, #0
 ;   adds xzr, x2, #1
@@ -493,4 +798,14 @@ block0(v0: i64):
 ;   b.vc 8 ; udf
 ;   sdiv x0, x0, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #-1
+;   cmn x2, #1
+;   ccmp x0, #1, #0, eq
+;   b.vc #0x14
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   sdiv x0, x0, x2
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/atomic-cas.clif b/cranelift/filetests/filetests/isa/aarch64/atomic-cas.clif
index 0508b68255..58fe258746 100644
--- a/cranelift/filetests/filetests/isa/aarch64/atomic-cas.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/atomic-cas.clif
@@ -10,6 +10,7 @@ block0(v0: i64, v1: i32, v2: i32):
     return v7
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -27,4 +28,27 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   mov x28, x2
+;   ldaxr w27, [x25]
+;   cmp x27, x26
+;   b.ne #0x34
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x20
+;   cmp w27, w26
+;   cset x0, eq
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/atomic-rmw-lse.clif b/cranelift/filetests/filetests/isa/aarch64/atomic-rmw-lse.clif
index 3d1871c83b..22cd655462 100644
--- a/cranelift/filetests/filetests/isa/aarch64/atomic-rmw-lse.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/atomic-rmw-lse.clif
@@ -7,9 +7,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldaddal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldaddal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_add_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -17,9 +23,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldaddal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldaddal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_add_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -27,9 +39,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldaddalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldaddalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_add_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -37,9 +55,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldaddalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldaddalb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_sub_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -47,10 +71,17 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub x3, xzr, x1
 ;   ldaddal x3, x5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg x3, x1
+;   ldaddal x3, x5, [x0]
+;   ret
 
 function %atomic_rmw_sub_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -58,10 +89,17 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   ldaddal w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   ldaddal w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_sub_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -69,10 +107,17 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   ldaddalh w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   ldaddalh w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_sub_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -80,10 +125,17 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   ldaddalb w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   ldaddalb w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_and_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -91,10 +143,17 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   eon x3, x1, xzr
 ;   ldclral x3, x5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x3, x1, xzr
+;   ldclral x3, x5, [x0]
+;   ret
 
 function %atomic_rmw_and_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -102,10 +161,17 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   eon w3, w1, wzr
 ;   ldclral w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w3, w1, wzr
+;   ldclral w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_and_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -113,10 +179,17 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   eon w3, w1, wzr
 ;   ldclralh w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w3, w1, wzr
+;   ldclralh w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_and_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -124,10 +197,17 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   eon w3, w1, wzr
 ;   ldclralb w3, w5, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w3, w1, wzr
+;   ldclralb w3, w5, [x0]
+;   ret
 
 function %atomic_rmw_nand_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -135,6 +215,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -149,6 +230,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   and x28, x27, x26
+;   mvn x28, x28
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -156,6 +257,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -170,6 +272,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -177,6 +299,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -191,6 +314,26 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -198,6 +341,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -212,6 +356,26 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_or_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -219,9 +383,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsetal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsetal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_or_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -229,9 +399,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsetal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsetal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_or_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -239,9 +415,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsetalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsetalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_or_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -249,9 +431,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsetalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsetalb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_xor_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -259,9 +447,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldeoral x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldeoral x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_xor_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -269,9 +463,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldeoral w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldeoral w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_xor_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -279,9 +479,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldeoralh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldeoralh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_xor_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -289,9 +495,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldeoralb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldeoralb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -299,9 +511,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsmaxal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsmaxal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_smax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -309,9 +527,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsmaxal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsmaxal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smax_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -319,9 +543,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsmaxalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsmaxalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smax_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -329,9 +559,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsmaxalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsmaxalb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -339,9 +575,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldumaxal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldumaxal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_umax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -349,9 +591,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldumaxal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldumaxal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umax_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -359,9 +607,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldumaxalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldumaxalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umax_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -369,9 +623,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldumaxalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldumaxalb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -379,9 +639,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsminal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsminal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_smin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -389,9 +655,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsminal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsminal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smin_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -399,9 +671,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsminalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsminalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_smin_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -409,9 +687,15 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   ldsminalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldsminalb w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -419,9 +703,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   lduminal x1, x3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lduminal x1, x3, [x0]
+;   ret
 
 function %atomic_rmw_umin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -429,9 +719,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   lduminal w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lduminal w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umin_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -439,9 +735,15 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ; block0:
 ;   lduminalh w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lduminalh w1, w3, [x0]
+;   ret
 
 function %atomic_rmw_umin_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -449,7 +751,13 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ; block0:
 ;   lduminalb w1, w3, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lduminalb w1, w3, [x0]
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/atomic-rmw.clif b/cranelift/filetests/filetests/isa/aarch64/atomic-rmw.clif
index d2ba234244..5887aa7167 100644
--- a/cranelift/filetests/filetests/isa/aarch64/atomic-rmw.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/atomic-rmw.clif
@@ -7,6 +7,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -21,6 +22,25 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   add x28, x27, x26
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_add_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -28,6 +48,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -42,6 +63,25 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   add w28, w27, w26
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_add_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -49,6 +89,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -63,6 +104,25 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   add w28, w27, w26
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_add_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -70,6 +130,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -84,6 +145,25 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   add w28, w27, w26
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_sub_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -91,6 +171,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -105,6 +186,25 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   sub x28, x27, x26
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_sub_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -112,6 +212,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -126,6 +227,25 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   sub w28, w27, w26
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_sub_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -133,6 +253,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -147,6 +268,25 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   sub w28, w27, w26
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_sub_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -154,6 +294,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -168,6 +309,25 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   sub w28, w27, w26
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_and_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -175,6 +335,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -189,6 +350,25 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   and x28, x27, x26
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_and_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -196,6 +376,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -210,6 +391,25 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   and w28, w27, w26
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_and_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -217,6 +417,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -231,6 +432,25 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   and w28, w27, w26
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_and_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -238,6 +458,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -252,6 +473,25 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   and w28, w27, w26
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -259,6 +499,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -273,6 +514,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   and x28, x27, x26
+;   mvn x28, x28
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -280,6 +541,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -294,6 +556,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -301,6 +583,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -315,6 +598,26 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_nand_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -322,6 +625,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -336,6 +640,26 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   and w28, w27, w26
+;   mvn w28, w28
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_or_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -343,6 +667,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -357,6 +682,25 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   orr x28, x27, x26
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_or_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -364,6 +708,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -378,6 +723,25 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   orr w28, w27, w26
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_or_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -385,6 +749,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -399,6 +764,25 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   orr w28, w27, w26
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_or_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -406,6 +790,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -420,6 +805,25 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   orr w28, w27, w26
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_xor_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -427,6 +831,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -441,6 +846,25 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   eor x28, x27, x26
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_xor_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -448,6 +872,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -462,6 +887,25 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   eor w28, w27, w26
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_xor_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -469,6 +913,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -483,6 +928,25 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   eor w28, w27, w26
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_xor_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -490,6 +954,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -504,6 +969,25 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   eor w28, w27, w26
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -511,6 +995,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -525,6 +1010,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   cmp x27, x26
+;   csel x28, x27, x26, gt
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -532,6 +1037,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -546,6 +1052,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, gt
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smax_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -553,6 +1079,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -567,6 +1094,27 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   sxth w27, w27
+;   cmp w27, w26, sxth
+;   csel x28, x27, x26, gt
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smax_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -574,6 +1122,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -588,6 +1137,27 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   sxtb w27, w27
+;   cmp w27, w26, sxtb
+;   csel x28, x27, x26, gt
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -595,6 +1165,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -609,6 +1180,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   cmp x27, x26
+;   csel x28, x27, x26, hi
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -616,6 +1207,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -630,6 +1222,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, hi
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umax_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -637,6 +1249,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -651,6 +1264,26 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, hi
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umax_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -658,6 +1291,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -672,6 +1306,26 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, hi
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -679,6 +1333,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -693,6 +1348,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   cmp x27, x26
+;   csel x28, x27, x26, lt
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -700,6 +1375,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -714,6 +1390,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, lt
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smin_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -721,6 +1417,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -735,6 +1432,27 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   sxth w27, w27
+;   cmp w27, w26, sxth
+;   csel x28, x27, x26, lt
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_smin_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -742,6 +1460,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -756,6 +1475,27 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   sxtb w27, w27
+;   cmp w27, w26, sxtb
+;   csel x28, x27, x26, lt
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -763,6 +1503,7 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -777,6 +1518,26 @@ block0(v0: i64, v1: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr x27, [x25]
+;   cmp x27, x26
+;   csel x28, x27, x26, lo
+;   stlxr w24, x28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -784,6 +1545,7 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -798,6 +1560,26 @@ block0(v0: i64, v1: i32):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxr w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, lo
+;   stlxr w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umin_i16(i64, i16) {
 block0(v0: i64, v1: i16):
@@ -805,6 +1587,7 @@ block0(v0: i64, v1: i16):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -819,6 +1602,26 @@ block0(v0: i64, v1: i16):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrh w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, lo
+;   stlxrh w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %atomic_rmw_umin_i8(i64, i8) {
 block0(v0: i64, v1: i8):
@@ -826,6 +1629,7 @@ block0(v0: i64, v1: i8):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -840,4 +1644,24 @@ block0(v0: i64, v1: i8):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x26, x27, [sp, #-0x10]!
+;   stp x24, x25, [sp, #-0x10]!
+; block0: ; offset 0x14
+;   mov x25, x0
+;   mov x26, x1
+;   ldaxrb w27, [x25]
+;   cmp w27, w26
+;   csel x28, x27, x26, lo
+;   stlxrb w24, w28, [x25]
+;   cbnz x24, #0x1c
+;   ldp x24, x25, [sp], #0x10
+;   ldp x26, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/atomic_load.clif b/cranelift/filetests/filetests/isa/aarch64/atomic_load.clif
index 9d5ff8e132..7d62ab74d0 100644
--- a/cranelift/filetests/filetests/isa/aarch64/atomic_load.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/atomic_load.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldar x0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldar x0, [x0]
+;   ret
 
 function %atomic_load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -17,9 +23,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldar w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldar w0, [x0]
+;   ret
 
 function %atomic_load_i16(i64) -> i16 {
 block0(v0: i64):
@@ -27,9 +39,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldarh w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarh w0, [x0]
+;   ret
 
 function %atomic_load_i8(i64) -> i8 {
 block0(v0: i64):
@@ -37,9 +55,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldarb w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarb w0, [x0]
+;   ret
 
 function %atomic_load_i32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -48,9 +72,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ldar w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldar w0, [x0]
+;   ret
 
 function %atomic_load_i16_i64(i64) -> i64 {
 block0(v0: i64):
@@ -59,9 +89,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ldarh w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarh w0, [x0]
+;   ret
 
 function %atomic_load_i8_i64(i64) -> i64 {
 block0(v0: i64):
@@ -70,9 +106,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ldarb w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarb w0, [x0]
+;   ret
 
 function %atomic_load_i16_i32(i64) -> i32 {
 block0(v0: i64):
@@ -81,9 +123,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ldarh w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarh w0, [x0]
+;   ret
 
 function %atomic_load_i8_i32(i64) -> i32 {
 block0(v0: i64):
@@ -92,7 +140,13 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ldarb w0, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldarb w0, [x0]
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/atomic_store.clif b/cranelift/filetests/filetests/isa/aarch64/atomic_store.clif
index 63bea58d84..e72634d4e0 100644
--- a/cranelift/filetests/filetests/isa/aarch64/atomic_store.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/atomic_store.clif
@@ -7,9 +7,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlr x0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlr x0, [x1]
+;   ret
 
 function %atomic_store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -17,9 +23,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlr w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlr w0, [x1]
+;   ret
 
 function %atomic_store_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -27,9 +39,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrh w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrh w0, [x1]
+;   ret
 
 function %atomic_store_i8(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -37,9 +55,15 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrb w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrb w0, [x1]
+;   ret
 
 function %atomic_store_i64_i32(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -48,9 +72,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlr w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlr w0, [x1]
+;   ret
 
 function %atomic_store_i64_i16(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -59,9 +89,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrh w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrh w0, [x1]
+;   ret
 
 function %atomic_store_i64_i8(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -70,9 +106,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrb w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrb w0, [x1]
+;   ret
 
 function %atomic_store_i32_i16(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -81,9 +123,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrh w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrh w0, [x1]
+;   ret
 
 function %atomic_store_i32_i8(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -92,7 +140,13 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stlrb w0, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stlrb w0, [x1]
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/basic1.clif b/cranelift/filetests/filetests/isa/aarch64/basic1.clif
index a6caf19f9c..7afe6a9181 100644
--- a/cranelift/filetests/filetests/isa/aarch64/basic1.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/basic1.clif
@@ -8,7 +8,13 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, w1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/bitcast.clif b/cranelift/filetests/filetests/isa/aarch64/bitcast.clif
index e16e088ec3..aa4255df8c 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bitcast.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bitcast.clif
@@ -7,9 +7,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov w0, v0.s[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, v0.s[0]
+;   ret
 
 function %f2(i32) -> f32 {
 block0(v0: i32):
@@ -17,9 +23,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, w0
+;   ret
 
 function %f3(f64) -> i64 {
 block0(v0: f64):
@@ -27,9 +39,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x0, v0.d[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, v0.d[0]
+;   ret
 
 function %f4(i64) -> f64 {
 block0(v0: i64):
@@ -37,7 +55,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov d0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d0, x0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/bitops.clif b/cranelift/filetests/filetests/isa/aarch64/bitops.clif
index 21eec6c51a..8dd69c514e 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bitops.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bitops.clif
@@ -8,10 +8,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w2, w0
 ;   lsr w0, w2, #24
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w2, w0
+;   lsr w0, w2, #0x18
+;   ret
 
 function %a(i16) -> i16 {
 block0(v0: i16):
@@ -19,10 +26,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w2, w0
 ;   lsr w0, w2, #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w2, w0
+;   lsr w0, w2, #0x10
+;   ret
 
 function %a(i32) -> i32 {
 block0(v0: i32):
@@ -30,9 +44,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w0, w0
+;   ret
 
 function %a(i64) -> i64 {
 block0(v0: i64):
@@ -40,9 +60,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit x0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit x0, x0
+;   ret
 
 function %a(i128) -> i128 {
 block0(v0: i128):
@@ -50,11 +76,19 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x6, x1
 ;   rbit x1, x0
 ;   rbit x0, x6
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, x1
+;   rbit x1, x0
+;   rbit x0, x6
+;   ret
 
 function %b(i8) -> i8 {
 block0(v0: i8):
@@ -62,11 +96,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w2, w0
 ;   clz w4, w2
 ;   sub w0, w4, #24
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w2, w0
+;   clz w4, w2
+;   sub w0, w4, #0x18
+;   ret
 
 function %b(i16) -> i16 {
 block0(v0: i16):
@@ -74,11 +116,19 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w2, w0
 ;   clz w4, w2
 ;   sub w0, w4, #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w2, w0
+;   clz w4, w2
+;   sub w0, w4, #0x10
+;   ret
 
 function %b(i32) -> i32 {
 block0(v0: i32):
@@ -86,9 +136,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   clz w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clz w0, w0
+;   ret
 
 function %b(i64) -> i64 {
 block0(v0: i64):
@@ -96,9 +152,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   clz x0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clz x0, x0
+;   ret
 
 function %b(i128) -> i128 {
 block0(v0: i128):
@@ -106,6 +168,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   clz x3, x1
 ;   clz x5, x0
@@ -113,6 +176,15 @@ block0(v0: i128):
 ;   madd x0, x5, x7, x3
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clz x3, x1
+;   clz x5, x0
+;   lsr x7, x3, #6
+;   madd x0, x5, x7, x3
+;   mov x1, #0
+;   ret
 
 function %c(i8) -> i8 {
 block0(v0: i8):
@@ -120,11 +192,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w2, w0
 ;   cls w4, w2
 ;   sub w0, w4, #24
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w2, w0
+;   cls w4, w2
+;   sub w0, w4, #0x18
+;   ret
 
 function %c(i16) -> i16 {
 block0(v0: i16):
@@ -132,11 +212,19 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth w2, w0
 ;   cls w4, w2
 ;   sub w0, w4, #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w2, w0
+;   cls w4, w2
+;   sub w0, w4, #0x10
+;   ret
 
 function %c(i32) -> i32 {
 block0(v0: i32):
@@ -144,9 +232,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   cls w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cls w0, w0
+;   ret
 
 function %c(i64) -> i64 {
 block0(v0: i64):
@@ -154,9 +248,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   cls x0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cls x0, x0
+;   ret
 
 function %c(i128) -> i128 {
 block0(v0: i128):
@@ -164,6 +264,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   cls x3, x0
 ;   cls x5, x1
@@ -175,6 +276,19 @@ block0(v0: i128):
 ;   add x0, x14, x5
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cls x3, x0
+;   cls x5, x1
+;   eon x7, x1, x0
+;   lsr x9, x7, #0x3f
+;   madd x11, x3, x9, x9
+;   cmp x5, #0x3f
+;   csel x14, x11, xzr, eq
+;   add x0, x14, x5
+;   mov x1, #0
+;   ret
 
 function %d(i8) -> i8 {
 block0(v0: i8):
@@ -182,11 +296,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w2, w0
 ;   orr w4, w2, #8388608
 ;   clz w0, w4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w2, w0
+;   orr w4, w2, #0x800000
+;   clz w0, w4
+;   ret
 
 function %d(i16) -> i16 {
 block0(v0: i16):
@@ -194,11 +316,19 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w2, w0
 ;   orr w4, w2, #32768
 ;   clz w0, w4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w2, w0
+;   orr w4, w2, #0x8000
+;   clz w0, w4
+;   ret
 
 function %d(i32) -> i32 {
 block0(v0: i32):
@@ -206,10 +336,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit w2, w0
 ;   clz w0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit w2, w0
+;   clz w0, w2
+;   ret
 
 function %d(i64) -> i64 {
 block0(v0: i64):
@@ -217,10 +354,17 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit x2, x0
 ;   clz x0, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit x2, x0
+;   clz x0, x2
+;   ret
 
 function %d(i128) -> i128 {
 block0(v0: i128):
@@ -228,6 +372,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rbit x3, x0
 ;   rbit x5, x1
@@ -237,6 +382,17 @@ block0(v0: i128):
 ;   madd x0, x9, x11, x7
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rbit x3, x0
+;   rbit x5, x1
+;   clz x7, x3
+;   clz x9, x5
+;   lsr x11, x7, #6
+;   madd x0, x9, x11, x7
+;   mov x1, #0
+;   ret
 
 function %d(i128) -> i128 {
 block0(v0: i128):
@@ -244,6 +400,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov d4, x0
 ;   mov v4.d[1], v4.d[1], x1
@@ -252,6 +409,16 @@ block0(v0: i128):
 ;   umov w0, v17.b[0]
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d4, x0
+;   mov v4.d[1], x1
+;   cnt v7.16b, v4.16b
+;   addv b17, v7.16b
+;   umov w0, v17.b[0]
+;   mov x1, #0
+;   ret
 
 function %d(i64) -> i64 {
 block0(v0: i64):
@@ -259,12 +426,21 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov d2, x0
 ;   cnt v4.8b, v2.8b
 ;   addv b6, v4.8b
 ;   umov w0, v6.b[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d2, x0
+;   cnt v4.8b, v2.8b
+;   addv b6, v4.8b
+;   umov w0, v6.b[0]
+;   ret
 
 function %d(i32) -> i32 {
 block0(v0: i32):
@@ -272,12 +448,21 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s2, w0
 ;   cnt v4.8b, v2.8b
 ;   addv b6, v4.8b
 ;   umov w0, v6.b[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   addv b6, v4.8b
+;   umov w0, v6.b[0]
+;   ret
 
 function %d(i16) -> i16 {
 block0(v0: i16):
@@ -285,12 +470,21 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s2, w0
 ;   cnt v4.8b, v2.8b
 ;   addp v6.8b, v4.8b, v4.8b
 ;   umov w0, v6.b[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   addp v6.8b, v4.8b, v4.8b
+;   umov w0, v6.b[0]
+;   ret
 
 function %d(i8) -> i8 {
 block0(v0: i8):
@@ -298,11 +492,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s2, w0
 ;   cnt v4.8b, v2.8b
 ;   umov w0, v4.b[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   umov w0, v4.b[0]
+;   ret
 
 function %sextend_i8() -> i32 {
 block0:
@@ -311,10 +513,17 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #255
 ;   sxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0xff
+;   sxtb w0, w0
+;   ret
 
 function %sextend_i8() -> i32 {
 block0:
@@ -323,10 +532,17 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #255
 ;   sxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0xff
+;   sxtb w0, w0
+;   ret
 
 function %bnot_i32(i32) -> i32 {
 block0(v0: i32):
@@ -334,9 +550,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   orn w0, wzr, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn w0, w0
+;   ret
 
 function %bnot_i64(i64) -> i64 {
 block0(v0: i64):
@@ -344,9 +566,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   orn x0, xzr, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn x0, x0
+;   ret
 
 function %bnot_i64_with_shift(i64) -> i64 {
 block0(v0: i64):
@@ -356,9 +584,15 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   orn x0, xzr, x0, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn x0, x0, lsl #3
+;   ret
 
 function %bnot_i128(i128) -> i128 {
 block0(v0: i128):
@@ -366,10 +600,17 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   orn x0, xzr, x0
 ;   orn x1, xzr, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn x0, x0
+;   mvn x1, x1
+;   ret
 
 function %bnot_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -377,9 +618,15 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mvn v0.16b, v0.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn v0.16b, v0.16b
+;   ret
 
 function %band_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -387,9 +634,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w0, w0, w1
+;   ret
 
 function %band_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -397,9 +650,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, x1
+;   ret
 
 function %band_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -407,10 +666,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, x2
 ;   and x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, x2
+;   and x1, x1, x3
+;   ret
 
 function %band_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -418,9 +684,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and v0.16b, v0.16b, v1.16b
+;   ret
 
 function %band_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -429,9 +701,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, #3
+;   ret
 
 function %band_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -440,9 +718,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, #3
+;   ret
 
 function %band_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -452,9 +736,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, x1, lsl #3
+;   ret
 
 function %band_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -464,9 +754,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   and x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, x1, lsl #3
+;   ret
 
 function %bor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -474,9 +770,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr w0, w0, w1
+;   ret
 
 function %bor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -484,9 +786,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, x1
+;   ret
 
 function %bor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -494,10 +802,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, x2
 ;   orr x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, x2
+;   orr x1, x1, x3
+;   ret
 
 function %bor_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -505,9 +820,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bor_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -516,9 +837,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, #3
+;   ret
 
 function %bor_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -527,9 +854,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, #3
+;   ret
 
 function %bor_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -539,9 +872,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, x1, lsl #3
+;   ret
 
 function %bor_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -551,9 +890,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   orr x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, x1, lsl #3
+;   ret
 
 function %bxor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -561,9 +906,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor w0, w0, w1
+;   ret
 
 function %bxor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -571,9 +922,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, x1
+;   ret
 
 function %bxor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -581,10 +938,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, x2
 ;   eor x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, x2
+;   eor x1, x1, x3
+;   ret
 
 function %bxor_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -592,9 +956,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bxor_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -603,9 +973,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, #3
+;   ret
 
 function %bxor_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -614,9 +990,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, #3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, #3
+;   ret
 
 function %bxor_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -626,9 +1008,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, x1, lsl #3
+;   ret
 
 function %bxor_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -638,9 +1026,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   eor x0, x0, x1, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, x1, lsl #3
+;   ret
 
 function %band_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -648,9 +1042,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bic w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic w0, w0, w1
+;   ret
 
 function %band_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -658,9 +1058,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bic x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic x0, x0, x1
+;   ret
 
 function %band_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -668,10 +1074,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bic x0, x0, x2
 ;   bic x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic x0, x0, x2
+;   bic x1, x1, x3
+;   ret
 
 function %band_not_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -679,9 +1092,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bic v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic v0.16b, v0.16b, v1.16b
+;   ret
 
 function %band_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -690,9 +1109,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bic x0, x0, #4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and x0, x0, #0xfffffffffffffffb
+;   ret
 
 function %band_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -702,9 +1127,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   bic x0, x0, x1, LSL 4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic x0, x0, x1, lsl #4
+;   ret
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -712,9 +1143,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orn w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn w0, w0, w1
+;   ret
 
 function %bor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -722,9 +1159,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orn x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn x0, x0, x1
+;   ret
 
 function %bor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -732,10 +1175,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orn x0, x0, x2
 ;   orn x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn x0, x0, x2
+;   orn x1, x1, x3
+;   ret
 
 function %bor_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -744,9 +1194,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orn x0, x0, #4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x0, x0, #0xfffffffffffffffb
+;   ret
 
 function %bor_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -756,9 +1212,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   orn x0, x0, x1, LSL 4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn x0, x0, x1, lsl #4
+;   ret
 
 function %bxor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -766,9 +1228,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eon w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w0, w0, w1
+;   ret
 
 function %bxor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -776,9 +1244,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x0, x0, x1
+;   ret
 
 function %bxor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -786,10 +1260,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, x2
 ;   eon x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x0, x0, x2
+;   eon x1, x1, x3
+;   ret
 
 function %bxor_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -798,9 +1279,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, #4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor x0, x0, #0xfffffffffffffffb
+;   ret
 
 function %bxor_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -810,9 +1297,15 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, x1, LSL 4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x0, x0, x1, lsl #4
+;   ret
 
 function %ishl_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -820,6 +1313,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl x4, x0, x2
 ;   lsl x6, x1, x2
@@ -831,6 +1325,19 @@ block0(v0: i128, v1: i8):
 ;   csel x0, xzr, x4, ne
 ;   csel x1, x4, x14, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl x4, x0, x2
+;   lsl x6, x1, x2
+;   mvn w8, w2
+;   lsr x10, x0, #1
+;   lsr x12, x10, x8
+;   orr x14, x6, x12
+;   tst x2, #0x40
+;   csel x0, xzr, x4, ne
+;   csel x1, x4, x14, ne
+;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -838,6 +1345,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl x5, x0, x2
 ;   lsl x7, x1, x2
@@ -849,6 +1357,19 @@ block0(v0: i128, v1: i128):
 ;   csel x0, xzr, x5, ne
 ;   csel x1, x5, x15, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl x5, x0, x2
+;   lsl x7, x1, x2
+;   mvn w9, w2
+;   lsr x11, x0, #1
+;   lsr x13, x11, x9
+;   orr x15, x7, x13
+;   tst x2, #0x40
+;   csel x0, xzr, x5, ne
+;   csel x1, x5, x15, ne
+;   ret
 
 function %ushr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -856,6 +1377,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x4, x0, x2
 ;   lsr x6, x1, x2
@@ -867,6 +1389,19 @@ block0(v0: i128, v1: i8):
 ;   csel x0, x6, x14, ne
 ;   csel x1, xzr, x6, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x4, x0, x2
+;   lsr x6, x1, x2
+;   mvn w8, w2
+;   lsl x10, x1, #1
+;   lsl x12, x10, x8
+;   orr x14, x4, x12
+;   tst x2, #0x40
+;   csel x0, x6, x14, ne
+;   csel x1, xzr, x6, ne
+;   ret
 
 function %ushr_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -874,6 +1409,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x5, x0, x2
 ;   lsr x7, x1, x2
@@ -885,6 +1421,19 @@ block0(v0: i128, v1: i128):
 ;   csel x0, x7, x15, ne
 ;   csel x1, xzr, x7, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x5, x0, x2
+;   lsr x7, x1, x2
+;   mvn w9, w2
+;   lsl x11, x1, #1
+;   lsl x13, x11, x9
+;   orr x15, x5, x13
+;   tst x2, #0x40
+;   csel x0, x7, x15, ne
+;   csel x1, xzr, x7, ne
+;   ret
 
 function %sshr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -892,6 +1441,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x4, x0, x2
 ;   asr x6, x1, x2
@@ -904,6 +1454,20 @@ block0(v0: i128, v1: i8):
 ;   csel x0, x6, x0, ne
 ;   csel x1, x14, x6, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x4, x0, x2
+;   asr x6, x1, x2
+;   mvn w8, w2
+;   lsl x10, x1, #1
+;   lsl x12, x10, x8
+;   asr x14, x1, #0x3f
+;   orr x0, x4, x12
+;   tst x2, #0x40
+;   csel x0, x6, x0, ne
+;   csel x1, x14, x6, ne
+;   ret
 
 function %sshr_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -911,6 +1475,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x5, x0, x2
 ;   asr x7, x1, x2
@@ -923,6 +1488,20 @@ block0(v0: i128, v1: i128):
 ;   csel x0, x7, x1, ne
 ;   csel x1, x15, x7, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x5, x0, x2
+;   asr x7, x1, x2
+;   mvn w9, w2
+;   lsl x11, x1, #1
+;   lsl x13, x11, x9
+;   asr x15, x1, #0x3f
+;   orr x1, x5, x13
+;   tst x2, #0x40
+;   csel x0, x7, x1, ne
+;   csel x1, x15, x7, ne
+;   ret
 
 function %bnot_of_bxor(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -931,9 +1510,15 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   eon w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w0, w0, w1
+;   ret
 
 function %bnot_of_bxor(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -942,8 +1527,15 @@ block0(v0: i128, v1: i128):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   eon x0, x0, x2
 ;   eon x1, x1, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon x0, x0, x2
+;   eon x1, x1, x3
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/bitopts-optimized.clif b/cranelift/filetests/filetests/isa/aarch64/bitopts-optimized.clif
index c46a729001..f9698fe56f 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bitopts-optimized.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bitopts-optimized.clif
@@ -10,9 +10,15 @@ block0(v0: i32, v1: i32):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   bic w0, w1, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bic w0, w1, w0
+;   ret
 
 function %bor_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -21,9 +27,15 @@ block0(v0: i32, v1: i32):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   orn w0, w1, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orn w0, w1, w0
+;   ret
 
 function %bxor_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -32,6 +44,13 @@ block0(v0: i32, v1: i32):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   eon w0, w1, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eon w0, w1, w0
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/bmask.clif b/cranelift/filetests/filetests/isa/aarch64/bmask.clif
index 6beefe6421..ac085b1f05 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bmask.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bmask.clif
@@ -8,10 +8,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i64_i32(i64) -> i32 {
 block0(v0: i64):
@@ -19,10 +26,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i64_i16(i64) -> i16 {
 block0(v0: i64):
@@ -30,10 +44,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i64_i8(i64) -> i8 {
 block0(v0: i64):
@@ -41,10 +62,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i32_i64(i32) -> i64 {
 block0(v0: i32):
@@ -52,10 +80,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i32_i32(i32) -> i32 {
 block0(v0: i32):
@@ -63,10 +98,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i32_i16(i32) -> i16 {
 block0(v0: i32):
@@ -74,10 +116,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i32_i8(i32) -> i8 {
 block0(v0: i32):
@@ -85,10 +134,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i16_i64(i16) -> i64 {
 block0(v0: i16):
@@ -96,11 +152,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #65535
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xffff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i16_i32(i16) -> i32 {
 block0(v0: i16):
@@ -108,11 +172,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #65535
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xffff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i16_i16(i16) -> i16 {
 block0(v0: i16):
@@ -120,11 +192,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #65535
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xffff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i16_i8(i16) -> i8 {
 block0(v0: i16):
@@ -132,11 +212,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #65535
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xffff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i8_i64(i8) -> i64 {
 block0(v0: i8):
@@ -144,11 +232,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #255
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i8_i32(i8) -> i32 {
 block0(v0: i8):
@@ -156,11 +252,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #255
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i8_i16(i8) -> i16 {
 block0(v0: i8):
@@ -168,11 +272,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #255
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i8_i8(i8) -> i8 {
 block0(v0: i8):
@@ -180,11 +292,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #255
 ;   subs wzr, w2, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xff
+;   cmp w2, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i128_i128(i128) -> i128 {
 block0(v0: i128):
@@ -192,12 +312,21 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   subs xzr, x3, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+;   cmp x3, #0
+;   csetm x1, ne
+;   mov x0, x1
+;   ret
 
 function %bmask_i128_i64(i128) -> i64 {
 block0(v0: i128):
@@ -205,11 +334,19 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+;   cmp x3, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i128_i32(i128) -> i32 {
 block0(v0: i128):
@@ -217,11 +354,19 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+;   cmp x3, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i128_i16(i128) -> i16 {
 block0(v0: i128):
@@ -229,11 +374,19 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+;   cmp x3, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i128_i8(i128) -> i8 {
 block0(v0: i128):
@@ -241,11 +394,19 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+;   cmp x3, #0
+;   csetm x0, ne
+;   ret
 
 function %bmask_i64_i128(i64) -> i128 {
 block0(v0: i64):
@@ -253,11 +414,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   csetm x1, ne
+;   mov x0, x1
+;   ret
 
 function %bmask_i32_i128(i32) -> i128 {
 block0(v0: i32):
@@ -265,11 +434,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   csetm x1, ne
+;   mov x0, x1
+;   ret
 
 function %bmask_i16_i128(i16) -> i128 {
 block0(v0: i16):
@@ -277,12 +454,21 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #65535
 ;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xffff
+;   cmp w2, #0
+;   csetm x1, ne
+;   mov x0, x1
+;   ret
 
 function %bmask_i8_i128(i8) -> i128 {
 block0(v0: i8):
@@ -290,10 +476,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   and w2, w0, #255
 ;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w2, w0, #0xff
+;   cmp w2, #0
+;   csetm x1, ne
+;   mov x0, x1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/bswap.clif b/cranelift/filetests/filetests/isa/aarch64/bswap.clif
index 117b6a49d8..c9c55f6157 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bswap.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bswap.clif
@@ -8,9 +8,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rev64 x0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rev x0, x0
+;   ret
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -18,9 +24,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rev32 w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rev w0, w0
+;   ret
 
 function %f2(i16) -> i16 {
 block0(v0: i16):
@@ -28,7 +40,13 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   rev16 w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rev16 w0, w0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/bti.clif b/cranelift/filetests/filetests/isa/aarch64/bti.clif
index 757068769b..86f7fcdd76 100644
--- a/cranelift/filetests/filetests/isa/aarch64/bti.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/bti.clif
@@ -27,6 +27,7 @@ block5(v5: i32):
     return v6
 }
 
+; VCode:
 ;   bti c
 ; block0:
 ;   emit_island 44
@@ -58,6 +59,41 @@ block5(v5: i32):
 ; block9:
 ;   add w0, w0, w5
 ;   ret
+; 
+; Disassembled:
+;   hint #0x22
+; block0: ; offset 0x4
+;   cmp w0, #3
+;   b.hs #0x30
+;   csel x15, xzr, x0, hs
+;   csdb
+;   adr x14, #0x24
+;   ldrsw x15, [x14, w15, uxtw #2]
+;   add x14, x14, x15
+;   br x14
+;   .byte 0x14, 0x00, 0x00, 0x00
+;   .byte 0x20, 0x00, 0x00, 0x00
+;   .byte 0x2c, 0x00, 0x00, 0x00
+; block1: ; offset 0x30
+;   mov w5, #4
+; block2: ; offset 0x34
+;   b #0x58
+; block3: ; offset 0x38
+;   hint #0x24
+;   mov w5, #1
+; block4: ; offset 0x40
+;   b #0x58
+; block5: ; offset 0x44
+;   hint #0x24
+;   mov w5, #2
+; block6: ; offset 0x4c
+;   b #0x58
+; block7: ; offset 0x50
+;   hint #0x24
+;   mov w5, #3
+; block8: ; offset 0x58
+;   add w0, w0, w5
+;   ret
 
 function %f2(i64) -> i64 {
 block0(v0: i64):
@@ -74,6 +110,7 @@ block2:
     return v4
 }
 
+; VCode:
 ;   bti c
 ; block0:
 ;   ldr x5, [x0]
@@ -89,6 +126,29 @@ block2:
 ;   mov x0, x8
 ;   add x0, x0, #42
 ;   ret
+; 
+; Disassembled:
+;   hint #0x22
+; block0: ; offset 0x4
+;   ldr x5, [x0]
+;   mov x8, x5
+;   cmp w0, #1
+;   b.hs #0x30
+;   csel x7, xzr, x0, hs
+;   csdb
+;   adr x6, #0x2c
+;   ldrsw x7, [x6, w7, uxtw #2]
+;   add x6, x6, x7
+;   br x6
+;   .byte 0x0c, 0x00, 0x00, 0x00
+; block1: ; offset 0x30
+;   mov x0, x8
+;   ret
+; block2: ; offset 0x38
+;   hint #0x24
+;   mov x0, x8
+;   add x0, x0, #0x2a
+;   ret
 
 function %f3(i64) -> i64 {
     fn0 = %g(i64) -> i64
@@ -98,6 +158,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   bti c
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
@@ -106,4 +167,17 @@ block0(v0: i64):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   hint #0x22
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0xc
+;   ldr x3, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/call-indirect.clif b/cranelift/filetests/filetests/isa/aarch64/call-indirect.clif
index ff0dcd2da5..05b54c2403 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call-indirect.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call-indirect.clif
@@ -9,10 +9,19 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
 ;   blr x1
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   blr x1
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
index 6d4feece87..c38c69d700 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif
@@ -10,6 +10,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   paciasp
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
@@ -18,6 +19,20 @@ block0(v0: i64):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
+; 
+; Disassembled:
+;   paciasp
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0xc
+;   ldr x3, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   autiasp
+;   ret
 
 function %f2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -25,6 +40,13 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   add x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x0, x1
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/call.clif b/cranelift/filetests/filetests/isa/aarch64/call.clif
index fd50a51faf..bae501abf7 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call.clif
@@ -11,6 +11,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -18,6 +19,18 @@ block0(v0: i64):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldr x3, #0x10
+;   b #0x18
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f2(i32) -> i64 {
     fn0 = %g(i32 uext) -> i64
@@ -27,6 +40,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -34,14 +48,31 @@ block0(v0: i32):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldr x3, #0x10
+;   b #0x18
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f3(i32) -> i32 uext {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %f4(i32) -> i64 {
     fn0 = %g(i32 sext) -> i64
@@ -51,6 +82,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -58,14 +90,31 @@ block0(v0: i32):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldr x3, #0x10
+;   b #0x18
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f5(i32) -> i32 sext {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %f6(i8) -> i64 {
     fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
@@ -76,6 +125,7 @@ block0(v0: i8):
     return v2
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -97,6 +147,30 @@ block0(v0: i8):
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x8, x0
+;   sub sp, sp, #0x10
+;   mov w0, #0x2a
+;   mov w1, #0x2a
+;   mov w2, #0x2a
+;   mov w3, #0x2a
+;   mov w4, #0x2a
+;   mov w5, #0x2a
+;   mov w6, #0x2a
+;   mov w7, #0x2a
+;   sturb w8, [sp]
+;   ldr x8, #0x3c
+;   b #0x44
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x8
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
 block0(v0: i8):
@@ -104,6 +178,7 @@ block0(v0: i8):
     return v1, v1, v1, v1, v1, v1, v1, v1, v0
 }
 
+; VCode:
 ; block0:
 ;   mov x9, x0
 ;   mov x8, x1
@@ -117,6 +192,21 @@ block0(v0: i8):
 ;   movz w7, #42
 ;   strb w9, [x8]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x9, x0
+;   mov x8, x1
+;   mov w0, #0x2a
+;   mov w1, #0x2a
+;   mov w2, #0x2a
+;   mov w3, #0x2a
+;   mov w4, #0x2a
+;   mov w5, #0x2a
+;   mov w6, #0x2a
+;   mov w7, #0x2a
+;   sturb w9, [x8]
+;   ret
 
 function %f8() {
     fn0 = %g0() -> f32
@@ -136,6 +226,7 @@ block0:
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #48
@@ -163,6 +254,56 @@ block0:
 ;   add sp, sp, #48
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x30
+; block0: ; offset 0xc
+;   ldr x9, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x20]
+;   ldr x9, #0x2c
+;   b #0x34
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x10]
+;   ldr x9, #0x44
+;   b #0x4c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp]
+;   ldr x9, #0x5c
+;   b #0x64
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   ldr x10, #0x70
+;   b #0x78
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g3 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x20]
+;   blr x10
+;   ldr x11, #0x88
+;   b #0x90
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g4 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x10]
+;   blr x11
+;   ldr x12, #0xa0
+;   b #0xa8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g4 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp]
+;   blr x12
+;   add sp, sp, #0x30
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f9() {
     fn0 = %g0() -> i8x16
@@ -180,6 +321,7 @@ block0:
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #48
@@ -207,6 +349,56 @@ block0:
 ;   add sp, sp, #48
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x30
+; block0: ; offset 0xc
+;   ldr x9, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x20]
+;   ldr x9, #0x2c
+;   b #0x34
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x10]
+;   ldr x9, #0x44
+;   b #0x4c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp]
+;   ldr x9, #0x5c
+;   b #0x64
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   ldr x10, #0x70
+;   b #0x78
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x20]
+;   blr x10
+;   ldr x11, #0x88
+;   b #0x90
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x10]
+;   blr x11
+;   ldr x12, #0xa0
+;   b #0xa8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp]
+;   blr x12
+;   add sp, sp, #0x30
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f10() {
     fn0 = %g0() -> f32
@@ -228,6 +420,7 @@ block0:
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #48
@@ -255,6 +448,56 @@ block0:
 ;   add sp, sp, #48
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x30
+; block0: ; offset 0xc
+;   ldr x9, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x20]
+;   ldr x9, #0x2c
+;   b #0x34
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp, #0x10]
+;   ldr x9, #0x44
+;   b #0x4c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   stur q0, [sp]
+;   ldr x9, #0x5c
+;   b #0x64
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g3 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x9
+;   ldr x10, #0x70
+;   b #0x78
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g4 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x20]
+;   blr x10
+;   ldr x11, #0x88
+;   b #0x90
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g5 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp, #0x10]
+;   blr x11
+;   ldr x12, #0xa0
+;   b #0xa8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g6 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ldur q0, [sp]
+;   blr x12
+;   add sp, sp, #0x30
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f11(i128, i64) -> i64 {
 block0(v0: i128, v1: i64):
@@ -262,9 +505,15 @@ block0(v0: i128, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, x1
+;   ret
 
 function %f11_call(i64) -> i64 {
     fn0 = %f11(i128, i64) -> i64
@@ -276,6 +525,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -286,6 +536,21 @@ block0(v0: i64):
 ;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x1, x0
+;   mov x0, #0x2a
+;   mov x2, #0x2a
+;   ldr x6, #0x1c
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f11 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x6
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f12(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -293,9 +558,15 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov x0, x2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, x2
+;   ret
 
 function %f12_call(i64) -> i64 {
     fn0 = %f12(i64, i128) -> i64
@@ -307,6 +578,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -317,6 +589,21 @@ block0(v0: i64):
 ;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x2, x0
+;   mov x3, #0x2a
+;   mov x0, #0x2a
+;   ldr x6, #0x1c
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f12 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x6
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f13(i64, i128) -> i64 apple_aarch64 {
 block0(v0: i64, v1: i128):
@@ -324,9 +611,15 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, x1
+;   ret
 
 function %f13_call(i64) -> i64 apple_aarch64 {
     fn0 = %f13(i64, i128) -> i64 apple_aarch64
@@ -338,6 +631,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -348,12 +642,28 @@ block0(v0: i64):
 ;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x1, x0
+;   mov x2, #0x2a
+;   mov x0, #0x2a
+;   ldr x6, #0x1c
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f13 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x6
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f14(i128, i128, i128, i64, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
     return v4
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -361,6 +671,15 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   ldr x1, [fp, #24]
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldur x0, [x29, #0x10]
+;   ldur x1, [x29, #0x18]
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f14_call(i128, i64) -> i128 {
     fn0 = %f14(i128, i128, i128, i64, i128) -> i128
@@ -370,6 +689,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -390,12 +710,36 @@ block0(v0: i128, v1: i64):
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x6, x2
+;   sub sp, sp, #0x10
+;   stur x0, [sp]
+;   mov x4, x0
+;   stur x1, [sp, #8]
+;   mov x5, x1
+;   ldr x10, #0x28
+;   b #0x30
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f14 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   mov x0, x4
+;   mov x2, x4
+;   mov x1, x5
+;   mov x3, x5
+;   blr x10
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64{
 block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
     return v4
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -403,6 +747,15 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   ldr x1, [fp, #24]
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldur x0, [x29, #0x10]
+;   ldur x1, [x29, #0x18]
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f15_call(i128, i64) -> i128 apple_aarch64 {
     fn0 = %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64
@@ -412,6 +765,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -432,6 +786,29 @@ block0(v0: i128, v1: i64):
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x6, x2
+;   sub sp, sp, #0x10
+;   stur x0, [sp]
+;   mov x4, x0
+;   stur x1, [sp, #8]
+;   mov x5, x1
+;   ldr x10, #0x28
+;   b #0x30
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f15 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   mov x0, x4
+;   mov x2, x4
+;   mov x1, x5
+;   mov x3, x5
+;   blr x10
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f16() -> i32, i32 wasmtime_system_v {
 block0:
@@ -440,12 +817,21 @@ block0:
     return v0, v1
 }
 
+; VCode:
 ; block0:
 ;   mov x6, x0
 ;   movz w0, #0
 ;   movz w4, #1
 ;   str w4, [x6]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, x0
+;   mov w0, #0
+;   mov w4, #1
+;   stur w4, [x6]
+;   ret
 
 function %f17(i64 sret) {
 block0(v0: i64):
@@ -454,11 +840,19 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   mov x5, x8
 ;   movz x4, #42
 ;   str x4, [x8]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, x8
+;   mov x4, #0x2a
+;   str x4, [x8]
+;   ret
 
 function %f18(i64) -> i64 {
     fn0 = %g(i64 sret) -> i64
@@ -468,6 +862,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
@@ -476,6 +871,19 @@ block0(v0: i64):
 ;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x8, x0
+;   ldr x3, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x3
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f18(i64 sret) {
     fn0 = %g(i64 sret)
@@ -485,6 +893,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x24, [sp, #-16]!
@@ -496,4 +905,20 @@ block0(v0: i64):
 ;   ldr x24, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x24, [sp, #-0x10]!
+; block0: ; offset 0xc
+;   mov x24, x8
+;   ldr x4, #0x18
+;   b #0x20
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x4
+;   mov x8, x24
+;   ldr x24, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif b/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif
index 4b13b8c150..3eb52abcc3 100644
--- a/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif
@@ -10,9 +10,15 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmeq v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v0.16b, v0.16b, #0
+;   ret
 
 function %f0_vconst(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -21,9 +27,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmeq v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v0.16b, v0.16b, #0
+;   ret
 
 function %f1(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -33,9 +45,15 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmeq v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v0.8h, v0.8h, #0
+;   ret
 
 function %f1_vconst(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -44,9 +62,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmeq v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v0.8h, v0.8h, #0
+;   ret
 
 function %f2(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -56,10 +80,17 @@ block0(v0: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.4s, v0.4s, #0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.4s, v0.4s, #0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f2_vconst(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -68,10 +99,17 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.4s, v0.4s, #0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.4s, v0.4s, #0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f3(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -81,10 +119,17 @@ block0(v0: i64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.2d, v0.2d, #0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.2d, v0.2d, #0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f3_vconst(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -93,10 +138,17 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.2d, v0.2d, #0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.2d, v0.2d, #0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f4(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -106,9 +158,15 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmle v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmle v0.16b, v0.16b, #0
+;   ret
 
 function %f4_vconst(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -117,9 +175,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmle v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmle v0.16b, v0.16b, #0
+;   ret
 
 function %f5(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -129,9 +193,15 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmge v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmge v0.8h, v0.8h, #0
+;   ret
 
 function %f5_vconst(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -140,9 +210,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmge v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmge v0.8h, v0.8h, #0
+;   ret
 
 function %f6(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -152,9 +228,15 @@ block0(v0: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmge v0.4s, v0.4s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmge v0.4s, v0.4s, #0
+;   ret
 
 function %f6_vconst(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -163,9 +245,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmge v0.4s, v0.4s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmge v0.4s, v0.4s, #0
+;   ret
 
 function %f7(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -175,9 +263,15 @@ block0(v0: i64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmle v0.2d, v0.2d, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmle v0.2d, v0.2d, #0
+;   ret
 
 function %f7_vconst(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -186,9 +280,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmle v0.2d, v0.2d, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmle v0.2d, v0.2d, #0
+;   ret
 
 function %f8(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -198,9 +298,15 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmlt v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmlt v0.16b, v0.16b, #0
+;   ret
 
 function %f8_vconst(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -209,9 +315,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmlt v0.16b, v0.16b, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmlt v0.16b, v0.16b, #0
+;   ret
 
 function %f9(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -221,9 +333,15 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmgt v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmgt v0.8h, v0.8h, #0
+;   ret
 
 function %f9_vconst(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -232,9 +350,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmgt v0.8h, v0.8h, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmgt v0.8h, v0.8h, #0
+;   ret
 
 function %f10(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -244,9 +368,15 @@ block0(v0: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmgt v0.4s, v0.4s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmgt v0.4s, v0.4s, #0
+;   ret
 
 function %f10_vconst(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -255,9 +385,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmgt v0.4s, v0.4s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmgt v0.4s, v0.4s, #0
+;   ret
 
 function %f11(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -267,9 +403,15 @@ block0(v0: i64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cmlt v0.2d, v0.2d, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmlt v0.2d, v0.2d, #0
+;   ret
 
 function %f11_vconst(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -278,9 +420,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cmlt v0.2d, v0.2d, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmlt v0.2d, v0.2d, #0
+;   ret
 
 function %f12(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -290,9 +438,15 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v0.4s, v0.4s, #0.0
+;   ret
 
 function %f12_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -301,9 +455,15 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v0.4s, v0.4s, #0.0
+;   ret
 
 function %f13(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -313,9 +473,15 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v0.2d, v0.2d, #0.0
+;   ret
 
 function %f13_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -324,9 +490,15 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v0.2d, v0.2d, #0.0
+;   ret
 
 function %f14(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -336,10 +508,17 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v2.2d, v0.2d, #0.0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v2.2d, v0.2d, #0.0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f14_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -348,10 +527,17 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v2.2d, v0.2d, #0.0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v2.2d, v0.2d, #0.0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f15(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -361,10 +547,17 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v2.4s, v0.4s, #0.0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v2.4s, v0.4s, #0.0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f15_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -373,10 +566,17 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmeq v2.4s, v0.4s, #0.0
 ;   mvn v0.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmeq v2.4s, v0.4s, #0.0
+;   mvn v0.16b, v2.16b
+;   ret
 
 function %f16(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -386,9 +586,15 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmle v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmle v0.4s, v0.4s, #0.0
+;   ret
 
 function %f16_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -397,9 +603,15 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmle v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmle v0.4s, v0.4s, #0.0
+;   ret
 
 function %f17(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -409,9 +621,15 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmge v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmge v0.2d, v0.2d, #0.0
+;   ret
 
 function %f17_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -420,9 +638,15 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmge v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmge v0.2d, v0.2d, #0.0
+;   ret
 
 function %f18(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -432,9 +656,15 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmge v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmge v0.2d, v0.2d, #0.0
+;   ret
 
 function %f18_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -443,9 +673,15 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmge v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmge v0.2d, v0.2d, #0.0
+;   ret
 
 function %f19(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -455,9 +691,15 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmle v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmle v0.4s, v0.4s, #0.0
+;   ret
 
 function %f19_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -466,9 +708,15 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmle v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmle v0.4s, v0.4s, #0.0
+;   ret
 
 function %f20(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -478,9 +726,15 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmlt v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmlt v0.4s, v0.4s, #0.0
+;   ret
 
 function %f20_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -489,9 +743,15 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmlt v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmlt v0.4s, v0.4s, #0.0
+;   ret
 
 function %f21(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -501,9 +761,15 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmgt v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmgt v0.2d, v0.2d, #0.0
+;   ret
 
 function %f21_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -512,9 +778,15 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmgt v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmgt v0.2d, v0.2d, #0.0
+;   ret
 
 function %f22(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -524,9 +796,15 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmgt v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmgt v0.2d, v0.2d, #0.0
+;   ret
 
 function %f22_vconst(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -535,9 +813,15 @@ block0(v0: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmgt v0.2d, v0.2d, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmgt v0.2d, v0.2d, #0.0
+;   ret
 
 function %f23(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -547,9 +831,15 @@ block0(v0: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fcmlt v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmlt v0.4s, v0.4s, #0.0
+;   ret
 
 function %f23_vconst(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -558,6 +848,13 @@ block0(v0: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fcmlt v0.4s, v0.4s, #0.0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmlt v0.4s, v0.4s, #0.0
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/condbr.clif b/cranelift/filetests/filetests/isa/aarch64/condbr.clif
index 95cc32e4b4..c0bca3b902 100644
--- a/cranelift/filetests/filetests/isa/aarch64/condbr.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/condbr.clif
@@ -8,10 +8,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x1
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x1
+;   cset x0, eq
+;   ret
 
 function %icmp_eq_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -19,11 +26,19 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   ccmp x1, x3, #nzcv, eq
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   ccmp x1, x3, #0, eq
+;   cset x0, eq
+;   ret
 
 function %icmp_ne_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -31,11 +46,19 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   ccmp x1, x3, #nzcv, eq
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   ccmp x1, x3, #0, eq
+;   cset x0, ne
+;   ret
 
 function %icmp_slt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -43,6 +66,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, lo
@@ -50,6 +74,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, lt
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, lo
+;   cmp x1, x3
+;   cset x9, lt
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -57,6 +90,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, lo
@@ -64,6 +98,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, lo
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, lo
+;   cmp x1, x3
+;   cset x9, lo
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -71,6 +114,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, ls
@@ -78,6 +122,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, le
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, ls
+;   cmp x1, x3
+;   cset x9, le
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -85,6 +138,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, ls
@@ -92,6 +146,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, ls
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, ls
+;   cmp x1, x3
+;   cset x9, ls
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -99,6 +162,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hi
@@ -106,6 +170,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, gt
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hi
+;   cmp x1, x3
+;   cset x9, gt
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -113,6 +186,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hi
@@ -120,6 +194,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, hi
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hi
+;   cmp x1, x3
+;   cset x9, hi
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -127,6 +210,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hs
@@ -134,6 +218,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, ge
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hs
+;   cmp x1, x3
+;   cset x9, ge
+;   csel x0, x6, x9, eq
+;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -141,6 +234,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hs
@@ -148,6 +242,15 @@ block0(v0: i128, v1: i128):
 ;   cset x9, hs
 ;   csel x0, x6, x9, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hs
+;   cmp x1, x3
+;   cset x9, hs
+;   csel x0, x6, x9, eq
+;   ret
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -164,6 +267,7 @@ block2:
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x1
 ;   b.eq label1 ; b label2
@@ -173,6 +277,17 @@ block2:
 ; block2:
 ;   movz x0, #2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x1
+;   b.ne #0x10
+; block1: ; offset 0x8
+;   mov x0, #1
+;   ret
+; block2: ; offset 0x10
+;   mov x0, #2
+;   ret
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -185,6 +300,7 @@ block1:
   return v4
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x1
 ;   b.eq label1 ; b label2
@@ -195,6 +311,13 @@ block1:
 ; block3:
 ;   movz x0, #1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x1
+; block1: ; offset 0x4
+;   mov x0, #1
+;   ret
 
 function %i128_brif_false(i128){
 block0(v0: i128):
@@ -205,6 +328,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   cbnz x3, label1 ; b label2
@@ -214,6 +338,12 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+; block1: ; offset 0x4
+;   ret
 
 function %i128_brif_true(i128){
 block0(v0: i128):
@@ -224,6 +354,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   orr x3, x0, x1
 ;   cbnz x3, label1 ; b label2
@@ -233,6 +364,12 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr x3, x0, x1
+; block1: ; offset 0x4
+;   ret
 
 function %i128_bricmp_eq(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -244,6 +381,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   ccmp x1, x3, #nzcv, eq
@@ -254,6 +392,13 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   ccmp x1, x3, #0, eq
+; block1: ; offset 0x8
+;   ret
 
 function %i128_bricmp_ne(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -265,6 +410,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   ccmp x1, x3, #nzcv, eq
@@ -275,6 +421,13 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   ccmp x1, x3, #0, eq
+; block1: ; offset 0x8
+;   ret
 
 function %i128_bricmp_slt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -286,6 +439,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, lo
@@ -300,6 +454,17 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, lo
+;   cmp x1, x3
+;   cset x9, lt
+;   csel x11, x6, x9, eq
+;   cmp xzr, x11
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_ult(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -311,6 +476,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, lo
@@ -325,6 +491,17 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, lo
+;   cmp x1, x3
+;   cset x9, lo
+;   csel x11, x6, x9, eq
+;   cmp xzr, x11
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_sle(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -336,6 +513,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, ls
@@ -351,6 +529,18 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, ls
+;   cmp x1, x3
+;   cset x9, le
+;   csel x11, x6, x9, eq
+;   mov w13, #1
+;   cmp x13, x11
+; block1: ; offset 0x1c
+;   ret
 
 function %i128_bricmp_ule(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -362,6 +552,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, ls
@@ -377,6 +568,18 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, ls
+;   cmp x1, x3
+;   cset x9, ls
+;   csel x11, x6, x9, eq
+;   mov x13, #1
+;   cmp x13, x11
+; block1: ; offset 0x1c
+;   ret
 
 function %i128_bricmp_sgt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -388,6 +591,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hi
@@ -402,6 +606,17 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hi
+;   cmp x1, x3
+;   cset x9, gt
+;   csel x11, x6, x9, eq
+;   cmp x11, xzr
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_ugt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -413,6 +628,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hi
@@ -427,6 +643,17 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hi
+;   cmp x1, x3
+;   cset x9, hi
+;   csel x11, x6, x9, eq
+;   cmp x11, xzr
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_sge(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -438,6 +665,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hs
@@ -453,6 +681,18 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hs
+;   cmp x1, x3
+;   cset x9, ge
+;   csel x11, x6, x9, eq
+;   mov w13, #1
+;   cmp x11, x13
+; block1: ; offset 0x1c
+;   ret
 
 function %i128_bricmp_uge(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -464,6 +704,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, x2
 ;   cset x6, hs
@@ -479,4 +720,16 @@ block1:
 ;   b label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, x2
+;   cset x6, hs
+;   cmp x1, x3
+;   cset x9, hs
+;   csel x11, x6, x9, eq
+;   mov x13, #1
+;   cmp x11, x13
+; block1: ; offset 0x1c
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/condops.clif b/cranelift/filetests/filetests/isa/aarch64/condops.clif
index 5c878b484c..d7e92269f8 100644
--- a/cranelift/filetests/filetests/isa/aarch64/condops.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/condops.clif
@@ -10,11 +10,19 @@ block0(v0: i8, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i8, i16, i16) -> i16 {
 block0(v0: i8, v1: i16, v2: i16):
@@ -24,11 +32,19 @@ block0(v0: i8, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i8, i32, i32) -> i32 {
 block0(v0: i8, v1: i32, v2: i32):
@@ -38,11 +54,19 @@ block0(v0: i8, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i8, i64, i64) -> i64 {
 block0(v0: i8, v1: i64, v2: i64):
@@ -52,11 +76,19 @@ block0(v0: i8, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i8, i128, i128) -> i128 {
 block0(v0: i8, v1: i128, v2: i128):
@@ -66,12 +98,21 @@ block0(v0: i8, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w6, w0
 ;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w6, w0
+;   cmp w6, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
 
 function %f(i16, i8, i8) -> i8 {
 block0(v0: i16, v1: i8, v2: i8):
@@ -81,11 +122,19 @@ block0(v0: i16, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i16, i16, i16) -> i16 {
 block0(v0: i16, v1: i16, v2: i16):
@@ -95,11 +144,19 @@ block0(v0: i16, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i16, i32, i32) -> i32 {
 block0(v0: i16, v1: i32, v2: i32):
@@ -109,11 +166,19 @@ block0(v0: i16, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i16, i64, i64) -> i64 {
 block0(v0: i16, v1: i64, v2: i64):
@@ -123,11 +188,19 @@ block0(v0: i16, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i16, i128, i128) -> i128 {
 block0(v0: i16, v1: i128, v2: i128):
@@ -137,12 +210,21 @@ block0(v0: i16, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w6, w0
 ;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w6, w0
+;   cmp w6, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
 
 function %f(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -152,10 +234,17 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i32, i16, i16) -> i16 {
 block0(v0: i32, v1: i16, v2: i16):
@@ -165,10 +254,17 @@ block0(v0: i32, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -178,10 +274,17 @@ block0(v0: i32, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i32, i64, i64) -> i64 {
 block0(v0: i32, v1: i64, v2: i64):
@@ -191,10 +294,17 @@ block0(v0: i32, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i32, i128, i128) -> i128 {
 block0(v0: i32, v1: i128, v2: i128):
@@ -204,11 +314,19 @@ block0(v0: i32, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
 
 function %f(i64, i8, i8) -> i8 {
 block0(v0: i64, v1: i8, v2: i8):
@@ -218,10 +336,17 @@ block0(v0: i64, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i64, i16, i16) -> i16 {
 block0(v0: i64, v1: i16, v2: i16):
@@ -231,10 +356,17 @@ block0(v0: i64, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i64, i32, i32) -> i32 {
 block0(v0: i64, v1: i32, v2: i32):
@@ -244,10 +376,17 @@ block0(v0: i64, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -257,10 +396,17 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %f(i64, i128, i128) -> i128 {
 block0(v0: i64, v1: i128, v2: i128):
@@ -270,11 +416,19 @@ block0(v0: i64, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
 
 function %f(i128, i8, i8) -> i8 {
 block0(v0: i128, v1: i8, v2: i8):
@@ -285,6 +439,7 @@ block0(v0: i128, v1: i8, v2: i8):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -292,6 +447,15 @@ block0(v0: i128, v1: i8, v2: i8):
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   ret
 
 function %f(i128, i16, i16) -> i16 {
 block0(v0: i128, v1: i16, v2: i16):
@@ -302,6 +466,7 @@ block0(v0: i128, v1: i16, v2: i16):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -309,6 +474,15 @@ block0(v0: i128, v1: i16, v2: i16):
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   ret
 
 function %f(i128, i32, i32) -> i32 {
 block0(v0: i128, v1: i32, v2: i32):
@@ -319,6 +493,7 @@ block0(v0: i128, v1: i32, v2: i32):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -326,6 +501,15 @@ block0(v0: i128, v1: i32, v2: i32):
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   ret
 
 function %f(i128, i64, i64) -> i64 {
 block0(v0: i128, v1: i64, v2: i64):
@@ -336,6 +520,7 @@ block0(v0: i128, v1: i64, v2: i64):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -343,6 +528,15 @@ block0(v0: i128, v1: i64, v2: i64):
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   ret
 
 function %f(i128, i128, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128):
@@ -353,6 +547,7 @@ block0(v0: i128, v1: i128, v2: i128):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x9, #42
 ;   movz x11, #0
@@ -361,6 +556,16 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x9, #0x2a
+;   mov x11, #0
+;   cmp x0, x9
+;   ccmp x1, x11, #0, eq
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
 
 function %f(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -370,12 +575,21 @@ block0(v0: i8, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i8, i16, i16) -> i16 {
 block0(v0: i8, v1: i16, v2: i16):
@@ -385,12 +599,21 @@ block0(v0: i8, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i8, i32, i32) -> i32 {
 block0(v0: i8, v1: i32, v2: i32):
@@ -400,12 +623,21 @@ block0(v0: i8, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i8, i64, i64) -> i64 {
 block0(v0: i8, v1: i64, v2: i64):
@@ -415,12 +647,21 @@ block0(v0: i8, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i8, i128, i128) -> i128 {
 block0(v0: i8, v1: i128, v2: i128):
@@ -430,6 +671,7 @@ block0(v0: i8, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxtb w6, w0
 ;   subs wzr, w6, #42
@@ -437,6 +679,15 @@ block0(v0: i8, v1: i128, v2: i128):
 ;   csel x1, x3, x5, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w6, w0
+;   cmp w6, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
 
 function %f(i16, i8, i8) -> i8 {
 block0(v0: i16, v1: i8, v2: i8):
@@ -446,12 +697,21 @@ block0(v0: i16, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i16, i16, i16) -> i16 {
 block0(v0: i16, v1: i16, v2: i16):
@@ -461,12 +721,21 @@ block0(v0: i16, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i16, i32, i32) -> i32 {
 block0(v0: i16, v1: i32, v2: i32):
@@ -476,12 +745,21 @@ block0(v0: i16, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i16, i64, i64) -> i64 {
 block0(v0: i16, v1: i64, v2: i64):
@@ -491,12 +769,21 @@ block0(v0: i16, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w4, w0
 ;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w4, w0
+;   cmp w4, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i16, i128, i128) -> i128 {
 block0(v0: i16, v1: i128, v2: i128):
@@ -506,6 +793,7 @@ block0(v0: i16, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uxth w6, w0
 ;   subs wzr, w6, #42
@@ -513,6 +801,15 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   csel x1, x3, x5, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w6, w0
+;   cmp w6, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
 
 function %f(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -522,11 +819,19 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i32, i16, i16) -> i16 {
 block0(v0: i32, v1: i16, v2: i16):
@@ -536,11 +841,19 @@ block0(v0: i32, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -550,11 +863,19 @@ block0(v0: i32, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i32, i64, i64) -> i64 {
 block0(v0: i32, v1: i64, v2: i64):
@@ -564,11 +885,19 @@ block0(v0: i32, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i32, i128, i128) -> i128 {
 block0(v0: i32, v1: i128, v2: i128):
@@ -578,12 +907,21 @@ block0(v0: i32, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
 
 function %f(i64, i8, i8) -> i8 {
 block0(v0: i64, v1: i8, v2: i8):
@@ -593,11 +931,19 @@ block0(v0: i64, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i64, i16, i16) -> i16 {
 block0(v0: i64, v1: i16, v2: i16):
@@ -607,11 +953,19 @@ block0(v0: i64, v1: i16, v2: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i64, i32, i32) -> i32 {
 block0(v0: i64, v1: i32, v2: i32):
@@ -621,11 +975,19 @@ block0(v0: i64, v1: i32, v2: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -635,11 +997,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
 
 function %f(i64, i128, i128) -> i128 {
 block0(v0: i64, v1: i128, v2: i128):
@@ -649,12 +1019,21 @@ block0(v0: i64, v1: i128, v2: i128):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0x2a
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
 
 function %f(i128, i8, i8) -> i8 {
 block0(v0: i128, v1: i8, v2: i8):
@@ -665,6 +1044,7 @@ block0(v0: i128, v1: i8, v2: i8):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -673,6 +1053,16 @@ block0(v0: i128, v1: i8, v2: i8):
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
 
 function %f(i128, i16, i16) -> i16 {
 block0(v0: i128, v1: i16, v2: i16):
@@ -683,6 +1073,7 @@ block0(v0: i128, v1: i16, v2: i16):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -691,6 +1082,16 @@ block0(v0: i128, v1: i16, v2: i16):
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
 
 function %f(i128, i32, i32) -> i32 {
 block0(v0: i128, v1: i32, v2: i32):
@@ -701,6 +1102,7 @@ block0(v0: i128, v1: i32, v2: i32):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -709,6 +1111,16 @@ block0(v0: i128, v1: i32, v2: i32):
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
 
 function %f(i128, i64, i64) -> i64 {
 block0(v0: i128, v1: i64, v2: i64):
@@ -719,6 +1131,7 @@ block0(v0: i128, v1: i64, v2: i64):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x6, #42
 ;   movz x8, #0
@@ -727,6 +1140,16 @@ block0(v0: i128, v1: i64, v2: i64):
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x6, #0x2a
+;   mov x8, #0
+;   cmp x0, x6
+;   ccmp x1, x8, #0, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
 
 function %f(i128, i128, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128):
@@ -737,6 +1160,7 @@ block0(v0: i128, v1: i128, v2: i128):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   movz x9, #42
 ;   movz x11, #0
@@ -746,6 +1170,17 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   csel x1, x3, x5, eq
 ;   csdb
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x9, #0x2a
+;   mov x11, #0
+;   cmp x0, x9
+;   ccmp x1, x11, #0, eq
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
 
 function %g(i8) -> i8 {
 block0(v0: i8):
@@ -754,11 +1189,19 @@ block0(v0: i8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   uxtb w2, w0
 ;   subs wzr, w2, #42
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w2, w0
+;   cmp w2, #0x2a
+;   cset x0, eq
+;   ret
 
 function %h(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -766,11 +1209,19 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   and w4, w1, w0
 ;   bic w6, w2, w0
 ;   orr w0, w4, w6
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w4, w1, w0
+;   bic w6, w2, w0
+;   orr w0, w4, w6
+;   ret
 
 function %i(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -778,10 +1229,17 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ands wzr, w0, #255
 ;   csel x0, x1, x2, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   tst w0, #0xff
+;   csel x0, x1, x2, ne
+;   ret
 
 function %i(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -791,10 +1249,17 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #42
 ;   csel x0, x1, x2, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x2a
+;   csel x0, x1, x2, eq
+;   ret
 
 function %i128_select(i8, i128, i128) -> i128 {
 block0(v0: i8, v1: i128, v2: i128):
@@ -802,9 +1267,17 @@ block0(v0: i8, v1: i128, v2: i128):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ands wzr, w0, #255
 ;   csel x0, x2, x4, ne
 ;   csel x1, x3, x5, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   tst w0, #0xff
+;   csel x0, x2, x4, ne
+;   csel x1, x3, x5, ne
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/constants.clif b/cranelift/filetests/filetests/isa/aarch64/constants.clif
index 8eaeb75d02..53795f2ec1 100644
--- a/cranelift/filetests/filetests/isa/aarch64/constants.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/constants.clif
@@ -8,9 +8,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #255
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0xff
+;   ret
 
 function %f() -> i16 {
 block0:
@@ -18,9 +24,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -28,9 +40,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -38,9 +56,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #65535
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0xffff
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -48,9 +72,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #65535, LSL #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0xffff0000
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -58,9 +88,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #65535, LSL #32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0xffff00000000
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -68,9 +104,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #65535, LSL #48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-0x1000000000000
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -78,9 +120,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-1
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -88,9 +136,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #65535
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-0x10000
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -98,9 +152,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #65535, LSL #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-0xffff0001
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -108,9 +168,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #65535, LSL #32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-0xffff00000001
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -118,9 +184,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #65535, LSL #48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0xffffffffffff
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -128,12 +200,21 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #58
 ;   movk x0, x0, #4626, LSL #16
 ;   movk x0, x0, #61603, LSL #32
 ;   movk x0, x0, #62283, LSL #48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0x3a
+;   movk x0, #0x1212, lsl #16
+;   movk x0, #0xf0a3, lsl #32
+;   movk x0, #0xf34b, lsl #48
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -141,10 +222,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #7924, LSL #16
 ;   movk x0, x0, #4841, LSL #48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0x1ef40000
+;   movk x0, #0x12e9, lsl #48
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -152,10 +240,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #57611, LSL #16
 ;   movk x0, x0, #4841, LSL #48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-0xe10b0001
+;   movk x0, #0x12e9, lsl #48
+;   ret
 
 function %f() -> i32 {
 block0:
@@ -163,9 +258,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn w0, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #-1
+;   ret
 
 function %f() -> i32 {
 block0:
@@ -173,9 +274,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn w0, #8
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #-9
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -183,9 +290,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn w0, #8
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #-9
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -193,9 +306,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movn x0, #8
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #-9
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -203,9 +322,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   fmov d0, #1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d0, #1.00000000
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -213,9 +338,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, #5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, #5.00000000
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -223,10 +354,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #16457, LSL #48
 ;   fmov d0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #0x4049000000000000
+;   fmov d0, x1
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -234,10 +372,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #16968, LSL #16
 ;   fmov s0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #0x42480000
+;   fmov s0, w1
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -245,9 +390,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movi v0.2s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v0.2s, #0
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -255,9 +406,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movi v0.2s, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v0.2s, #0
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -265,9 +422,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   fmov d0, #-16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d0, #-16.00000000
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -275,7 +438,13 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, #-16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, #-16.00000000
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif
index 9c9123f356..cbd39adc39 100644
--- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif
@@ -14,11 +14,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.4h, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   sqxtn v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[0]
+;   sqxtn v0.8b, v3.8h
+;   ret
 
 function %snarrow_i16x8(i16) -> i8x16 {
   gv0 = dyn_scale_target_const.i16x8
@@ -33,11 +41,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.8h, w0
 ;   sqxtn v0.8b, v5.8h
 ;   sqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.8h, w0
+;   sqxtn v0.8b, v5.8h
+;   sqxtn2 v0.16b, v5.8h
+;   ret
 
 function %snarrow_i32x2(i32) -> i16x4 {
   gv0 = dyn_scale_target_const.i32x2
@@ -52,11 +68,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.2s, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   sqxtn v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[0]
+;   sqxtn v0.4h, v3.4s
+;   ret
 
 function %snarrow_i32x4(i32) -> i16x8 {
   gv0 = dyn_scale_target_const.i32x4
@@ -71,11 +95,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.4s, w0
 ;   sqxtn v0.4h, v5.4s
 ;   sqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.4s, w0
+;   sqxtn v0.4h, v5.4s
+;   sqxtn2 v0.8h, v5.4s
+;   ret
 
 function %snarrow_i64x2(i64) -> i32x4 {
   gv0 = dyn_scale_target_const.i64x2
@@ -90,11 +122,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.2d, x0
 ;   sqxtn v0.2s, v5.2d
 ;   sqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.2d, x0
+;   sqxtn v0.2s, v5.2d
+;   sqxtn2 v0.4s, v5.2d
+;   ret
 
 function %unarrow_i16x4(i16) -> i8x8 {
   gv0 = dyn_scale_target_const.i16x4
@@ -109,11 +149,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.4h, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   sqxtun v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[0]
+;   sqxtun v0.8b, v3.8h
+;   ret
 
 function %unarrow_i16x8(i16) -> i8x16 {
   gv0 = dyn_scale_target_const.i16x8
@@ -128,11 +176,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.8h, w0
 ;   sqxtun v0.8b, v5.8h
 ;   sqxtun2 v0.16b, v0.16b, v5.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.8h, w0
+;   sqxtun v0.8b, v5.8h
+;   sqxtun2 v0.16b, v5.8h
+;   ret
 
 function %unarrow_i32x2(i32) -> i16x4 {
   gv0 = dyn_scale_target_const.i32x2
@@ -147,11 +203,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.2s, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   sqxtun v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[0]
+;   sqxtun v0.4h, v3.4s
+;   ret
 
 function %unarrow_i32x4(i32) -> i16x8 {
   gv0 = dyn_scale_target_const.i32x4
@@ -166,11 +230,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.4s, w0
 ;   sqxtun v0.4h, v5.4s
 ;   sqxtun2 v0.8h, v0.8h, v5.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.4s, w0
+;   sqxtun v0.4h, v5.4s
+;   sqxtun2 v0.8h, v5.4s
+;   ret
 
 function %unarrow_i64x2(i64) -> i32x4 {
   gv0 = dyn_scale_target_const.i64x2
@@ -185,11 +257,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.2d, x0
 ;   sqxtun v0.2s, v5.2d
 ;   sqxtun2 v0.4s, v0.4s, v5.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.2d, x0
+;   sqxtun v0.2s, v5.2d
+;   sqxtun2 v0.4s, v5.2d
+;   ret
 
 function %uunarrow_i16x4(i16) -> i8x8 {
   gv0 = dyn_scale_target_const.i16x4
@@ -204,11 +284,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.4h, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   uqxtn v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[0]
+;   uqxtn v0.8b, v3.8h
+;   ret
 
 function %uunarrow_i16x8(i16) -> i8x16 {
   gv0 = dyn_scale_target_const.i16x8
@@ -223,11 +311,19 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.8h, w0
 ;   uqxtn v0.8b, v5.8h
 ;   uqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.8h, w0
+;   uqxtn v0.8b, v5.8h
+;   uqxtn2 v0.16b, v5.8h
+;   ret
 
 function %uunarrow_i32x2(i32) -> i16x4 {
   gv0 = dyn_scale_target_const.i32x2
@@ -242,11 +338,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v3.2s, w0
 ;   mov v3.d[1], v3.d[1], v3.d[0]
 ;   uqxtn v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[0]
+;   uqxtn v0.4h, v3.4s
+;   ret
 
 function %uunarrow_i32x4(i32) -> i16x8 {
   gv0 = dyn_scale_target_const.i32x4
@@ -261,11 +365,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.4s, w0
 ;   uqxtn v0.4h, v5.4s
 ;   uqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.4s, w0
+;   uqxtn v0.4h, v5.4s
+;   uqxtn2 v0.8h, v5.4s
+;   ret
 
 function %uunarrow_i64x2(i64) -> i32x4 {
   gv0 = dyn_scale_target_const.i64x2
@@ -280,9 +392,17 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v5.2d, x0
 ;   uqxtn v0.2s, v5.2d
 ;   uqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v5.2d, x0
+;   uqxtn v0.2s, v5.2d
+;   uqxtn2 v0.4s, v5.2d
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif
index 70ae36742a..6abdfa0b1b 100644
--- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif
@@ -13,11 +13,19 @@ block0(v0: i8, v1: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.16b, w0
 ;   dup v7.16b, w1
 ;   add v0.16b, v6.16b, v7.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.16b, w0
+;   dup v7.16b, w1
+;   add v0.16b, v6.16b, v7.16b
+;   ret
 
 function %i16x8_splat_add(i16, i16) -> i16x8 {
   gv0 = dyn_scale_target_const.i16x8
@@ -31,11 +39,19 @@ block0(v0: i16, v1: i16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.8h, w0
 ;   dup v7.8h, w1
 ;   add v0.8h, v6.8h, v7.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.8h, w0
+;   dup v7.8h, w1
+;   add v0.8h, v6.8h, v7.8h
+;   ret
 
 function %i32x4_splat_mul(i32, i32) -> i32x4 {
   gv0 = dyn_scale_target_const.i32x4
@@ -49,11 +65,19 @@ block0(v0: i32, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.4s, w0
 ;   dup v7.4s, w1
 ;   mul v0.4s, v6.4s, v7.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.4s, w0
+;   dup v7.4s, w1
+;   mul v0.4s, v6.4s, v7.4s
+;   ret
 
 function %i64x2_splat_sub(i64, i64) -> i64x2 {
   gv0 = dyn_scale_target_const.i64x2
@@ -67,11 +91,19 @@ block0(v0: i64, v1: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, x0
 ;   dup v7.2d, x1
 ;   sub v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, x0
+;   dup v7.2d, x1
+;   sub v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f32x4_splat_add(f32, f32) -> f32x4 {
   gv0 = dyn_scale_target_const.f32x4
@@ -85,11 +117,19 @@ block0(v0: f32, v1: f32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.4s, v0.s[0]
 ;   dup v7.4s, v1.s[0]
 ;   fadd v0.4s, v6.4s, v7.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.4s, v0.s[0]
+;   dup v7.4s, v1.s[0]
+;   fadd v0.4s, v6.4s, v7.4s
+;   ret
 
 function %f64x2_splat_sub(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -103,11 +143,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, v0.d[0]
 ;   dup v7.2d, v1.d[0]
 ;   fsub v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fsub v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f64x2_splat_mul(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -121,11 +169,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, v0.d[0]
 ;   dup v7.2d, v1.d[0]
 ;   fmul v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmul v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f64x2_splat_div(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -139,11 +195,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, v0.d[0]
 ;   dup v7.2d, v1.d[0]
 ;   fdiv v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fdiv v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f64x2_splat_min(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -157,11 +221,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, v0.d[0]
 ;   dup v7.2d, v1.d[0]
 ;   fmin v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmin v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f64x2_splat_max(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -175,11 +247,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v6.2d, v0.d[0]
 ;   dup v7.2d, v1.d[0]
 ;   fmax v0.2d, v6.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmax v0.2d, v6.2d, v7.2d
+;   ret
 
 function %f64x2_splat_min_pseudo(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -193,12 +273,21 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v7.2d, v0.d[0]
 ;   dup v16.2d, v1.d[0]
 ;   fcmgt v0.2d, v7.2d, v16.2d
 ;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v7.2d, v0.d[0]
+;   dup v16.2d, v1.d[0]
+;   fcmgt v0.2d, v7.2d, v16.2d
+;   bsl v0.16b, v16.16b, v7.16b
+;   ret
 
 function %f64x2_splat_max_pseudo(f64, f64) -> f64x2 {
   gv0 = dyn_scale_target_const.f64x2
@@ -212,10 +301,19 @@ block0(v0: f64, v1: f64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   dup v7.2d, v0.d[0]
 ;   dup v16.2d, v1.d[0]
 ;   fcmgt v0.2d, v16.2d, v7.2d
 ;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v7.2d, v0.d[0]
+;   dup v16.2d, v1.d[0]
+;   fcmgt v0.2d, v16.2d, v7.2d
+;   bsl v0.16b, v16.16b, v7.16b
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif
index 71f40eb360..4ce9201a98 100644
--- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif
@@ -14,10 +14,17 @@ block0(v0: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.16b, w0
 ;   sxtl2 v0.8h, v4.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.16b, w0
+;   sshll2 v0.8h, v4.16b, #0
+;   ret
 
 function %swidenhigh_i16x8(i16) -> i32x4 {
   gv0 = dyn_scale_target_const.i32x4
@@ -32,10 +39,17 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.8h, w0
 ;   sxtl2 v0.4s, v4.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.8h, w0
+;   sshll2 v0.4s, v4.8h, #0
+;   ret
 
 function %swidenhigh_i32x4(i32) -> i64x2 {
   gv0 = dyn_scale_target_const.i32x4
@@ -50,10 +64,17 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.4s, w0
 ;   sxtl2 v0.2d, v4.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.4s, w0
+;   sshll2 v0.2d, v4.4s, #0
+;   ret
 
 function %swidenlow_i8x16(i8) -> i16x8 {
   gv0 = dyn_scale_target_const.i16x8
@@ -68,10 +89,17 @@ block0(v0: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.16b, w0
 ;   sxtl v0.8h, v4.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.16b, w0
+;   sshll v0.8h, v4.8b, #0
+;   ret
 
 function %swidenlow_i16x8(i16) -> i32x4 {
   gv0 = dyn_scale_target_const.i32x4
@@ -86,10 +114,17 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.8h, w0
 ;   sxtl v0.4s, v4.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.8h, w0
+;   sshll v0.4s, v4.4h, #0
+;   ret
 
 function %swidenlow_i32x4(i32) -> i64x2 {
   gv0 = dyn_scale_target_const.i32x4
@@ -104,8 +139,15 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   dup v4.4s, w0
 ;   sxtl v0.2d, v4.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v4.4s, w0
+;   sshll v0.2d, v4.2s, #0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif
index e5cb3e5cb6..2284a0bb55 100644
--- a/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif
@@ -11,6 +11,7 @@ block0:
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -21,6 +22,18 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x1, sp
+;   mov x2, #1
+;   str x2, [x1]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %store_scale_lt_128() {
   gv0 = dyn_scale_target_const.i16x4
@@ -32,6 +45,7 @@ block0:
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -42,6 +56,18 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x1, sp
+;   mov x2, #1
+;   str x2, [x1]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %store_explicit(i32) {
   gv0 = dyn_scale_target_const.i32x4
@@ -54,6 +80,7 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -64,6 +91,18 @@ block0(v0: i32):
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   dup v3.4s, w0
+;   mov x3, sp
+;   str q3, [x3]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %load_explicit() -> i32x4 {
   gv0 = dyn_scale_target_const.i32x4
@@ -76,6 +115,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -85,6 +125,17 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x2, sp
+;   ldr q0, [x2]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %store_implicit(i32) {
   gv0 = dyn_scale_target_const.i32x4
@@ -97,6 +148,7 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -107,6 +159,18 @@ block0(v0: i32):
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   dup v3.4s, w0
+;   mov x3, sp
+;   str q3, [x3]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %addr() -> i64 {
   gv0 = dyn_scale_target_const.i32x4
@@ -118,6 +182,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -126,4 +191,14 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x0, sp
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/extend-op.clif b/cranelift/filetests/filetests/isa/aarch64/extend-op.clif
index be28f5c9ad..5694fb4abe 100644
--- a/cranelift/filetests/filetests/isa/aarch64/extend-op.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/extend-op.clif
@@ -10,10 +10,17 @@ block0(v0: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sxtb x3, w0
 ;   add x0, x3, #42
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb x3, w0
+;   add x0, x3, #0x2a
+;   ret
 
 function %f2(i8, i64) -> i64 {
 block0(v0: i8, v1: i64):
@@ -22,9 +29,15 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   add x0, x1, x0, SXTB
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x1, w0, sxtb
+;   ret
 
 function %i128_uextend_i64(i64) -> i128 {
 block0(v0: i64):
@@ -32,9 +45,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #0
+;   ret
 
 function %i128_sextend_i64(i64) -> i128 {
 block0(v0: i64):
@@ -42,9 +61,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i128_uextend_i32(i32) -> i128 {
 block0(v0: i32):
@@ -52,10 +77,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mov w0, w0
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, w0
+;   mov x1, #0
+;   ret
 
 function %i128_sextend_i32(i32) -> i128 {
 block0(v0: i32):
@@ -63,10 +95,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtw x0, w0
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x0, w0
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i128_uextend_i16(i16) -> i128 {
 block0(v0: i16):
@@ -74,10 +113,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w0, w0
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w0, w0
+;   mov x1, #0
+;   ret
 
 function %i128_sextend_i16(i16) -> i128 {
 block0(v0: i16):
@@ -85,10 +131,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth x0, w0
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth x0, w0
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i128_uextend_i8(i8) -> i128 {
 block0(v0: i8):
@@ -96,10 +149,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w0, w0
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w0, w0
+;   mov x1, #0
+;   ret
 
 function %i128_sextend_i8(i8) -> i128 {
 block0(v0: i8):
@@ -107,10 +167,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb x0, w0
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb x0, w0
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i8x16_uextend_i16(i8x16) -> i16 {
 block0(v0: i8x16):
@@ -119,9 +186,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.b[1]
+;   ret
 
 function %i8x16_uextend_i32(i8x16) -> i32 {
 block0(v0: i8x16):
@@ -130,9 +203,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.b[1]
+;   ret
 
 function %i8x16_uextend_i64(i8x16) -> i64 {
 block0(v0: i8x16):
@@ -141,9 +220,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.b[1]
+;   ret
 
 function %i8x16_uextend_i128(i8x16) -> i128 {
 block0(v0: i8x16):
@@ -152,10 +237,17 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.b[1]
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.b[1]
+;   mov x1, #0
+;   ret
 
 function %i8x16_sextend_i16(i8x16) -> i16 {
 block0(v0: i8x16):
@@ -164,9 +256,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov w0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov w0, v0.b[1]
+;   ret
 
 function %i8x16_sextend_i32(i8x16) -> i32 {
 block0(v0: i8x16):
@@ -175,9 +273,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov w0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov w0, v0.b[1]
+;   ret
 
 function %i8x16_sextend_i64(i8x16) -> i64 {
 block0(v0: i8x16):
@@ -186,9 +290,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.b[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.b[1]
+;   ret
 
 function %i8x16_sextend_i128(i8x16) -> i128 {
 block0(v0: i8x16):
@@ -197,10 +307,17 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.b[1]
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.b[1]
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i16x8_uextend_i32(i16x8) -> i32 {
 block0(v0: i16x8):
@@ -209,9 +326,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.h[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.h[1]
+;   ret
 
 function %i16x8_uextend_i64(i16x8) -> i64 {
 block0(v0: i16x8):
@@ -220,9 +343,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.h[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.h[1]
+;   ret
 
 function %i16x8_uextend_i128(i16x8) -> i128 {
 block0(v0: i16x8):
@@ -231,10 +360,17 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   umov w0, v0.h[1]
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umov w0, v0.h[1]
+;   mov x1, #0
+;   ret
 
 function %i16x8_sextend_i32(i16x8) -> i32 {
 block0(v0: i16x8):
@@ -243,9 +379,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov w0, v0.h[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov w0, v0.h[1]
+;   ret
 
 function %i16x8_sextend_i64(i16x8) -> i64 {
 block0(v0: i16x8):
@@ -254,9 +396,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.h[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.h[1]
+;   ret
 
 function %i16x8_sextend_i128(i16x8) -> i128 {
 block0(v0: i16x8):
@@ -265,10 +413,17 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.h[1]
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.h[1]
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i32x4_uextend_i64(i32x4) -> i64 {
 block0(v0: i32x4):
@@ -277,9 +432,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov w0, v0.s[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, v0.s[1]
+;   ret
 
 function %i32x4_uextend_i128(i32x4) -> i128 {
 block0(v0: i32x4):
@@ -288,10 +449,17 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov w0, v0.s[1]
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, v0.s[1]
+;   mov x1, #0
+;   ret
 
 function %i32x4_sextend_i64(i32x4) -> i64 {
 block0(v0: i32x4):
@@ -300,9 +468,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.s[1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.s[1]
+;   ret
 
 function %i32x4_sextend_i128(i32x4) -> i128 {
 block0(v0: i32x4):
@@ -311,10 +485,17 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   smov x0, v0.s[1]
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smov x0, v0.s[1]
+;   asr x1, x0, #0x3f
+;   ret
 
 function %i64x2_uextend_i128(i64x2) -> i128 {
 block0(v0: i64x2):
@@ -323,10 +504,17 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov x0, v0.d[1]
 ;   movz x1, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, v0.d[1]
+;   mov x1, #0
+;   ret
 
 function %i64x2_sextend_i128(i64x2) -> i128 {
 block0(v0: i64x2):
@@ -335,8 +523,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov x0, v0.d[1]
 ;   asr x1, x0, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, v0.d[1]
+;   asr x1, x0, #0x3f
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif b/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif
index d932bf4f06..2bd77df458 100644
--- a/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif
@@ -8,10 +8,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w2, w0
 ;   ucvtf s0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w2, w0
+;   ucvtf s0, w2
+;   ret
 
 function u0:0(i8) -> f64 {
 block0(v0: i8):
@@ -19,10 +26,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w2, w0
 ;   ucvtf d0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w2, w0
+;   ucvtf d0, w2
+;   ret
 
 function u0:0(i16) -> f32 {
 block0(v0: i16):
@@ -30,10 +44,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w2, w0
 ;   ucvtf s0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w2, w0
+;   ucvtf s0, w2
+;   ret
 
 function u0:0(i16) -> f64 {
 block0(v0: i16):
@@ -41,10 +62,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w2, w0
 ;   ucvtf d0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w2, w0
+;   ucvtf d0, w2
+;   ret
 
 function u0:0(f32) -> i8 {
 block0(v0: f32):
@@ -52,6 +80,7 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -64,6 +93,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x43800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, s0
+;   ret
 
 function u0:0(f64) -> i8 {
 block0(v0: f64):
@@ -71,6 +117,7 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -83,6 +130,23 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x4070000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, d0
+;   ret
 
 function u0:0(f32) -> i16 {
 block0(v0: f32):
@@ -90,6 +154,7 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -102,6 +167,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x47800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, s0
+;   ret
 
 function u0:0(f64) -> i16 {
 block0(v0: f64):
@@ -109,6 +191,7 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -121,4 +204,21 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x40f0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, d0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/fcvt.clif b/cranelift/filetests/filetests/isa/aarch64/fcvt.clif
index 7e9c337ea0..06ba98d8b5 100644
--- a/cranelift/filetests/filetests/isa/aarch64/fcvt.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/fcvt.clif
@@ -7,10 +7,17 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w2, w0
 ;   scvtf s0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w2, w0
+;   scvtf s0, w2
+;   ret
 
 function %f2(i16) -> f32 {
 block0(v0: i16):
@@ -18,10 +25,17 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth w2, w0
 ;   scvtf s0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w2, w0
+;   scvtf s0, w2
+;   ret
 
 function %f3(i32) -> f32 {
 block0(v0: i32):
@@ -29,9 +43,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf s0, w0
+;   ret
 
 function %f4(i64) -> f32 {
 block0(v0: i64):
@@ -39,9 +59,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf s0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf s0, x0
+;   ret
 
 function %f5(i8) -> f64 {
 block0(v0: i8):
@@ -49,10 +75,17 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w2, w0
 ;   scvtf d0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w2, w0
+;   scvtf d0, w2
+;   ret
 
 function %f6(i16) -> f64 {
 block0(v0: i16):
@@ -60,10 +93,17 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth w2, w0
 ;   scvtf d0, w2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w2, w0
+;   scvtf d0, w2
+;   ret
 
 function %f7(i32) -> f64 {
 block0(v0: i32):
@@ -71,9 +111,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf d0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf d0, w0
+;   ret
 
 function %f8(i64) -> f64 {
 block0(v0: i64):
@@ -81,9 +127,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf d0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf d0, x0
+;   ret
 
 function %f9(i32x4) -> f64x2 {
 block0(v0: i32x4):
@@ -91,10 +143,17 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtl v2.2d, v0.2s
 ;   scvtf v0.2d, v2.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sshll v2.2d, v0.2s, #0
+;   scvtf v0.2d, v2.2d
+;   ret
 
 function %f10(i8, i16, i32, i64) -> f32 {
 block0(v0: i8, v1: i16, v2: i32, v3: i64):
@@ -108,6 +167,7 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
   return v10
 }
 
+; VCode:
 ; block0:
 ;   uxtb w12, w0
 ;   ucvtf s22, w12
@@ -119,6 +179,19 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
 ;   fadd s21, s22, s21
 ;   fadd s0, s21, s24
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w12, w0
+;   ucvtf s22, w12
+;   uxth w12, w1
+;   ucvtf s23, w12
+;   ucvtf s21, w2
+;   ucvtf s24, x3
+;   fadd s22, s22, s23
+;   fadd s21, s22, s21
+;   fadd s0, s21, s24
+;   ret
 
 function %f11(i32x4) -> f64x2 {
 block0(v0: i32x4):
@@ -127,10 +200,17 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxtl v3.2d, v0.2s
 ;   ucvtf v0.2d, v3.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushll v3.2d, v0.2s, #0
+;   ucvtf v0.2d, v3.2d
+;   ret
 
 function %f12(i32x4) -> f32x4 {
 block0(v0: i32x4):
@@ -138,9 +218,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ucvtf v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ucvtf v0.4s, v0.4s
+;   ret
 
 function %f13(f32) -> i32 {
 block0(v0: f32):
@@ -148,6 +234,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -160,6 +247,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x4f800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, s0
+;   ret
 
 function %f14(f32) -> i64 {
 block0(v0: f32):
@@ -167,6 +271,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -179,6 +284,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x5f800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu x0, s0
+;   ret
 
 function %f15(f64) -> i32 {
 block0(v0: f64):
@@ -186,6 +308,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -198,6 +321,23 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x41f0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, d0
+;   ret
 
 function %f16(f64) -> i64 {
 block0(v0: f64):
@@ -205,6 +345,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -217,6 +358,23 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x43f0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu x0, d0
+;   ret
 
 function %f17(f32) -> i32 {
 block0(v0: f32):
@@ -224,9 +382,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w0, s0
+;   ret
 
 function %f18(f32) -> i64 {
 block0(v0: f32):
@@ -234,9 +398,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu x0, s0
+;   ret
 
 function %f19(f64) -> i32 {
 block0(v0: f64):
@@ -244,9 +414,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w0, d0
+;   ret
 
 function %f20(f64) -> i64 {
 block0(v0: f64):
@@ -254,9 +430,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu x0, d0
+;   ret
 
 function %f21(f32) -> i32 {
 block0(v0: f32):
@@ -264,6 +446,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -277,6 +460,24 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #0xcf000000
+;   fmov s5, w5
+;   fcmp s0, s5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x4f000000
+;   fmov s19, w11
+;   fcmp s0, s19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs w0, s0
+;   ret
 
 function %f22(f32) -> i64 {
 block0(v0: f32):
@@ -284,6 +485,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -297,6 +499,24 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #0xdf000000
+;   fmov s5, w5
+;   fcmp s0, s5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x5f000000
+;   fmov s19, w11
+;   fcmp s0, s19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs x0, s0
+;   ret
 
 function %f23(f64) -> i32 {
 block0(v0: f64):
@@ -304,6 +524,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -316,6 +537,26 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   ldr d4, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x20, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0xc1
+;   fcmp d0, d4
+;   b.gt #0x28
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x41e0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x3c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs w0, d0
+;   ret
 
 function %f24(f64) -> i64 {
 block0(v0: f64):
@@ -323,6 +564,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -336,6 +578,24 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #-0x3c20000000000000
+;   fmov d5, x5
+;   fcmp d0, d5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x43e0000000000000
+;   fmov d19, x11
+;   fcmp d0, d19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs x0, d0
+;   ret
 
 function %f25(f32) -> i32 {
 block0(v0: f32):
@@ -343,9 +603,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w0, s0
+;   ret
 
 function %f26(f32) -> i64 {
 block0(v0: f32):
@@ -353,9 +619,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs x0, s0
+;   ret
 
 function %f27(f64) -> i32 {
 block0(v0: f64):
@@ -363,9 +635,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w0, d0
+;   ret
 
 function %f28(f64) -> i64 {
 block0(v0: f64):
@@ -373,9 +651,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs x0, d0
+;   ret
 
 function %f29(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -383,9 +667,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu v0.4s, v0.4s
+;   ret
 
 function %f30(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -393,9 +683,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs v0.4s, v0.4s
+;   ret
 
 function %f31(f32) -> i8 {
 block0(v0: f32):
@@ -403,12 +699,21 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w2, s0
 ;   movz w4, #255
 ;   subs wzr, w2, w4
 ;   csel x0, x4, x2, hi
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w2, s0
+;   mov w4, #0xff
+;   cmp w2, w4
+;   csel x0, x4, x2, hi
+;   ret
 
 function %f32(f32) -> i8 {
 block0(v0: f32):
@@ -416,6 +721,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w2, s0
 ;   movz w4, #127
@@ -425,6 +731,17 @@ block0(v0: f32):
 ;   subs wzr, w9, w6
 ;   csel x0, x6, x9, lt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w2, s0
+;   mov w4, #0x7f
+;   mov x6, #-0x80
+;   cmp w2, w4
+;   csel x9, x4, x2, gt
+;   cmp w9, w6
+;   csel x0, x6, x9, lt
+;   ret
 
 function %f33(f32) -> i16 {
 block0(v0: f32):
@@ -432,12 +749,21 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w2, s0
 ;   movz w4, #65535
 ;   subs wzr, w2, w4
 ;   csel x0, x4, x2, hi
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w2, s0
+;   mov w4, #0xffff
+;   cmp w2, w4
+;   csel x0, x4, x2, hi
+;   ret
 
 function %f34(f32) -> i16 {
 block0(v0: f32):
@@ -445,6 +771,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w2, s0
 ;   movz w4, #32767
@@ -454,6 +781,17 @@ block0(v0: f32):
 ;   subs wzr, w9, w6
 ;   csel x0, x6, x9, lt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w2, s0
+;   mov w4, #0x7fff
+;   mov x6, #-0x8000
+;   cmp w2, w4
+;   csel x9, x4, x2, gt
+;   cmp w9, w6
+;   csel x0, x6, x9, lt
+;   ret
 
 function %f35(f64) -> i8 {
 block0(v0: f64):
@@ -461,12 +799,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w2, d0
 ;   movz w4, #255
 ;   subs wzr, w2, w4
 ;   csel x0, x4, x2, hi
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w2, d0
+;   mov w4, #0xff
+;   cmp w2, w4
+;   csel x0, x4, x2, hi
+;   ret
 
 function %f36(f64) -> i8 {
 block0(v0: f64):
@@ -474,6 +821,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w2, d0
 ;   movz w4, #127
@@ -483,6 +831,17 @@ block0(v0: f64):
 ;   subs wzr, w9, w6
 ;   csel x0, x6, x9, lt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w2, d0
+;   mov w4, #0x7f
+;   mov x6, #-0x80
+;   cmp w2, w4
+;   csel x9, x4, x2, gt
+;   cmp w9, w6
+;   csel x0, x6, x9, lt
+;   ret
 
 function %f37(f64) -> i16 {
 block0(v0: f64):
@@ -490,12 +849,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzu w2, d0
 ;   movz w4, #65535
 ;   subs wzr, w2, w4
 ;   csel x0, x4, x2, hi
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzu w2, d0
+;   mov w4, #0xffff
+;   cmp w2, w4
+;   csel x0, x4, x2, hi
+;   ret
 
 function %f38(f64) -> i16 {
 block0(v0: f64):
@@ -503,6 +871,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvtzs w2, d0
 ;   movz w4, #32767
@@ -512,4 +881,15 @@ block0(v0: f64):
 ;   subs wzr, w9, w6
 ;   csel x0, x6, x9, lt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvtzs w2, d0
+;   mov w4, #0x7fff
+;   mov x6, #-0x8000
+;   cmp w2, w4
+;   csel x9, x4, x2, gt
+;   cmp w9, w6
+;   csel x0, x6, x9, lt
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/floating-point.clif b/cranelift/filetests/filetests/isa/aarch64/floating-point.clif
index 78201ebb93..3ec6179544 100644
--- a/cranelift/filetests/filetests/isa/aarch64/floating-point.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/floating-point.clif
@@ -8,9 +8,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fadd s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fadd s0, s0, s1
+;   ret
 
 function %f2(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -18,9 +24,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fadd d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fadd d0, d0, d1
+;   ret
 
 function %f3(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -28,9 +40,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsub s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsub s0, s0, s1
+;   ret
 
 function %f4(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -38,9 +56,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsub d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsub d0, d0, d1
+;   ret
 
 function %f5(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -48,9 +72,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmul s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmul s0, s0, s1
+;   ret
 
 function %f6(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -58,9 +88,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmul d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmul d0, d0, d1
+;   ret
 
 function %f7(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -68,9 +104,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fdiv s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fdiv s0, s0, s1
+;   ret
 
 function %f8(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -78,9 +120,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fdiv d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fdiv d0, d0, d1
+;   ret
 
 function %f9(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -88,9 +136,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmin s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmin s0, s0, s1
+;   ret
 
 function %f10(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -98,9 +152,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmin d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmin d0, d0, d1
+;   ret
 
 function %f11(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -108,9 +168,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmax s0, s0, s1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmax s0, s0, s1
+;   ret
 
 function %f12(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -118,9 +184,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmax d0, d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmax d0, d0, d1
+;   ret
 
 function %f13(f32) -> f32 {
 block0(v0: f32):
@@ -128,9 +200,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt s0, s0
+;   ret
 
 function %f15(f64) -> f64 {
 block0(v0: f64):
@@ -138,9 +216,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt d0, d0
+;   ret
 
 function %f16(f32) -> f32 {
 block0(v0: f32):
@@ -148,9 +232,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs s0, s0
+;   ret
 
 function %f17(f64) -> f64 {
 block0(v0: f64):
@@ -158,9 +248,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs d0, d0
+;   ret
 
 function %f18(f32) -> f32 {
 block0(v0: f32):
@@ -168,9 +264,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg s0, s0
+;   ret
 
 function %f19(f64) -> f64 {
 block0(v0: f64):
@@ -178,9 +280,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg d0, d0
+;   ret
 
 function %f20(f32) -> f64 {
 block0(v0: f32):
@@ -188,9 +296,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt d0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt d0, s0
+;   ret
 
 function %f21(f64) -> f32 {
 block0(v0: f64):
@@ -198,9 +312,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt s0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt s0, d0
+;   ret
 
 function %f22(f32) -> f32 {
 block0(v0: f32):
@@ -208,9 +328,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintp s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintp s0, s0
+;   ret
 
 function %f22(f64) -> f64 {
 block0(v0: f64):
@@ -218,9 +344,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintp d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintp d0, d0
+;   ret
 
 function %f23(f32) -> f32 {
 block0(v0: f32):
@@ -228,9 +360,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintm s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintm s0, s0
+;   ret
 
 function %f24(f64) -> f64 {
 block0(v0: f64):
@@ -238,9 +376,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintm d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintm d0, d0
+;   ret
 
 function %f25(f32) -> f32 {
 block0(v0: f32):
@@ -248,9 +392,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintz s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintz s0, s0
+;   ret
 
 function %f26(f64) -> f64 {
 block0(v0: f64):
@@ -258,9 +408,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintz d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintz d0, d0
+;   ret
 
 function %f27(f32) -> f32 {
 block0(v0: f32):
@@ -268,9 +424,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintn s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintn s0, s0
+;   ret
 
 function %f28(f64) -> f64 {
 block0(v0: f64):
@@ -278,9 +440,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintn d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintn d0, d0
+;   ret
 
 function %f29(f32, f32, f32) -> f32 {
 block0(v0: f32, v1: f32, v2: f32):
@@ -288,9 +456,15 @@ block0(v0: f32, v1: f32, v2: f32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fmadd s0, s0, s1, s2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmadd s0, s0, s1, s2
+;   ret
 
 function %f30(f64, f64, f64) -> f64 {
 block0(v0: f64, v1: f64, v2: f64):
@@ -298,9 +472,15 @@ block0(v0: f64, v1: f64, v2: f64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fmadd d0, d0, d1, d2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmadd d0, d0, d1, d2
+;   ret
 
 function %f31(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -308,10 +488,17 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ushr v4.2s, v1.2s, #31
 ;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushr v4.2s, v1.2s, #0x1f
+;   sli v0.2s, v4.2s, #0x1f
+;   ret
 
 function %f32(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -319,10 +506,17 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ushr d4, d1, #63
 ;   sli d0, d0, d4, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushr d4, d1, #0x3f
+;   sli d0, d4, #0x3f
+;   ret
 
 function %f33(f32) -> i32 {
 block0(v0: f32):
@@ -330,6 +524,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -342,6 +537,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x4f800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, s0
+;   ret
 
 function %f34(f32) -> i32 {
 block0(v0: f32):
@@ -349,6 +561,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -362,6 +575,24 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #0xcf000000
+;   fmov s5, w5
+;   fcmp s0, s5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x4f000000
+;   fmov s19, w11
+;   fcmp s0, s19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs w0, s0
+;   ret
 
 function %f35(f32) -> i64 {
 block0(v0: f32):
@@ -369,6 +600,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -381,6 +613,23 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov s4, #-1.00000000
+;   fcmp s0, s4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x5f800000
+;   fmov s17, w9
+;   fcmp s0, s17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu x0, s0
+;   ret
 
 function %f36(f32) -> i64 {
 block0(v0: f32):
@@ -388,6 +637,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
@@ -401,6 +651,24 @@ block0(v0: f32):
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #0xdf000000
+;   fmov s5, w5
+;   fcmp s0, s5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x5f000000
+;   fmov s19, w11
+;   fcmp s0, s19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs x0, s0
+;   ret
 
 function %f37(f64) -> i32 {
 block0(v0: f64):
@@ -408,6 +676,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -420,6 +689,23 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x41f0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu w0, d0
+;   ret
 
 function %f38(f64) -> i32 {
 block0(v0: f64):
@@ -427,6 +713,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -439,6 +726,26 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   ldr d4, #0x14
+;   b #0x1c
+;   .byte 0x00, 0x00, 0x20, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0xc1
+;   fcmp d0, d4
+;   b.gt #0x28
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x41e0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x3c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs w0, d0
+;   ret
 
 function %f39(f64) -> i64 {
 block0(v0: f64):
@@ -446,6 +753,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -458,6 +766,23 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   fmov d4, #-1.00000000
+;   fcmp d0, d4
+;   b.gt #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x9, #0x43f0000000000000
+;   fmov d17, x9
+;   fcmp d0, d17
+;   b.lt #0x30
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzu x0, d0
+;   ret
 
 function %f40(f64) -> i64 {
 block0(v0: f64):
@@ -465,6 +790,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
@@ -478,6 +804,24 @@ block0(v0: f64):
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp d0, d0
+;   b.vc #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: bad_toint
+;   mov x5, #-0x3c20000000000000
+;   fmov d5, x5
+;   fcmp d0, d5
+;   b.ge #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   mov x11, #0x43e0000000000000
+;   fmov d19, x11
+;   fcmp d0, d19
+;   b.lt #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: int_ovf
+;   fcvtzs x0, d0
+;   ret
 
 function %f41(i32) -> f32 {
 block0(v0: i32):
@@ -485,9 +829,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ucvtf s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ucvtf s0, w0
+;   ret
 
 function %f42(i32) -> f32 {
 block0(v0: i32):
@@ -495,9 +845,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf s0, w0
+;   ret
 
 function %f43(i64) -> f32 {
 block0(v0: i64):
@@ -505,9 +861,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ucvtf s0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ucvtf s0, x0
+;   ret
 
 function %f44(i64) -> f32 {
 block0(v0: i64):
@@ -515,9 +877,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf s0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf s0, x0
+;   ret
 
 function %f45(i32) -> f64 {
 block0(v0: i32):
@@ -525,9 +893,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ucvtf d0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ucvtf d0, w0
+;   ret
 
 function %f46(i32) -> f64 {
 block0(v0: i32):
@@ -535,9 +909,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf d0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf d0, w0
+;   ret
 
 function %f47(i64) -> f64 {
 block0(v0: i64):
@@ -545,9 +925,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ucvtf d0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ucvtf d0, x0
+;   ret
 
 function %f48(i64) -> f64 {
 block0(v0: i64):
@@ -555,9 +941,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   scvtf d0, x0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   scvtf d0, x0
+;   ret
 
 function %f49(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -565,9 +957,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt v0.2s, v0.2s
+;   ret
 
 function %f50(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -575,9 +973,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt v0.4s, v0.4s
+;   ret
 
 function %f51(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -585,9 +989,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt v0.2d, v0.2d
+;   ret
 
 function %f52(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -595,9 +1005,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg v0.2s, v0.2s
+;   ret
 
 function %f53(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -605,9 +1021,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg v0.4s, v0.4s
+;   ret
 
 function %f54(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -615,9 +1037,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg v0.2d, v0.2d
+;   ret
 
 function %f55(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -625,9 +1053,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs v0.2s, v0.2s
+;   ret
 
 function %f56(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -635,9 +1069,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs v0.4s, v0.4s
+;   ret
 
 function %f57(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -645,9 +1085,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs v0.2d, v0.2d
+;   ret
 
 function %f58(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -655,9 +1101,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintp v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintp v0.2s, v0.2s
+;   ret
 
 function %f59(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -665,9 +1117,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintp v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintp v0.4s, v0.4s
+;   ret
 
 function %f60(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -675,9 +1133,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintp v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintp v0.2d, v0.2d
+;   ret
 
 function %f61(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -685,9 +1149,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintm v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintm v0.2s, v0.2s
+;   ret
 
 function %f62(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -695,9 +1165,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintm v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintm v0.4s, v0.4s
+;   ret
 
 function %f63(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -705,9 +1181,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintm v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintm v0.2d, v0.2d
+;   ret
 
 function %f64(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -715,9 +1197,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintz v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintz v0.2s, v0.2s
+;   ret
 
 function %f65(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -725,9 +1213,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintz v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintz v0.4s, v0.4s
+;   ret
 
 function %f66(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -735,9 +1229,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintz v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintz v0.2d, v0.2d
+;   ret
 
 function %f67(f32x2) -> f32x2 {
 block0(v0: f32x2):
@@ -745,9 +1245,15 @@ block0(v0: f32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintn v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintn v0.2s, v0.2s
+;   ret
 
 function %f68(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -755,9 +1261,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintn v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintn v0.4s, v0.4s
+;   ret
 
 function %f69(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -765,9 +1277,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   frintn v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   frintn v0.2d, v0.2d
+;   ret
 
 function %f70(f32x4, f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4, v2: f32x4):
@@ -775,11 +1293,19 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mov v5.16b, v0.16b
 ;   mov v0.16b, v2.16b
 ;   fmla v0.4s, v0.4s, v5.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.4s, v5.4s, v1.4s
+;   ret
 
 function %f71(f32x2, f32x2, f32x2) -> f32x2 {
 block0(v0: f32x2, v1: f32x2, v2: f32x2):
@@ -787,11 +1313,19 @@ block0(v0: f32x2, v1: f32x2, v2: f32x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mov v5.16b, v0.16b
 ;   mov v0.16b, v2.16b
 ;   fmla v0.2s, v0.2s, v5.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2s, v5.2s, v1.2s
+;   ret
 
 function %f72(f64x2, f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2, v2: f64x2):
@@ -799,11 +1333,19 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mov v5.16b, v0.16b
 ;   mov v0.16b, v2.16b
 ;   fmla v0.2d, v0.2d, v5.2d, v1.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2d, v5.2d, v1.2d
+;   ret
 
 function %f73(f32x2, f32x2) -> f32x2 {
 block0(v0: f32x2, v1: f32x2):
@@ -811,10 +1353,17 @@ block0(v0: f32x2, v1: f32x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ushr v4.2s, v1.2s, #31
 ;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushr v4.2s, v1.2s, #0x1f
+;   sli v0.2s, v4.2s, #0x1f
+;   ret
 
 function %f74(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -822,10 +1371,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ushr v4.4s, v1.4s, #31
 ;   sli v0.4s, v0.4s, v4.4s, #31
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushr v4.4s, v1.4s, #0x1f
+;   sli v0.4s, v4.4s, #0x1f
+;   ret
 
 function %f75(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -833,8 +1389,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ushr v4.2d, v1.2d, #63
 ;   sli v0.2d, v0.2d, v4.2d, #63
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ushr v4.2d, v1.2d, #0x3f
+;   sli v0.2d, v4.2d, #0x3f
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc-pauth.clif b/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc-pauth.clif
index 1d17050950..f320c6aec0 100644
--- a/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc-pauth.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc-pauth.clif
@@ -8,6 +8,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   paciasp
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
@@ -15,6 +16,16 @@ block0:
 ;   mov x0, fp
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
+; 
+; Disassembled:
+;   paciasp
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0xc
+;   mov x0, x29
+;   ldp x29, x30, [sp], #0x10
+;   autiasp
+;   ret
 
 function %sp() -> i64 {
 block0:
@@ -22,6 +33,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   paciasp
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
@@ -29,6 +41,16 @@ block0:
 ;   mov x0, sp
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
+; 
+; Disassembled:
+;   paciasp
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0xc
+;   mov x0, sp
+;   ldp x29, x30, [sp], #0x10
+;   autiasp
+;   ret
 
 function %return_address() -> i64 {
 block0:
@@ -36,6 +58,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   paciasp
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
@@ -45,3 +68,16 @@ block0:
 ;   mov x0, lr
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
+; 
+; Disassembled:
+;   paciasp
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0xc
+;   ldur x30, [x29, #8]
+;   xpaclri
+;   mov x0, x30
+;   ldp x29, x30, [sp], #0x10
+;   autiasp
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc.clif b/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc.clif
index 156b9bb548..82cb9bf484 100644
--- a/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/fp_sp_pc.clif
@@ -8,12 +8,21 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
 ;   mov x0, fp
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x0, x29
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %sp() -> i64 {
 block0:
@@ -21,12 +30,21 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
 ;   mov x0, sp
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   mov x0, sp
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %return_address() -> i64 {
 block0:
@@ -34,9 +52,19 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
 ;   ldr x0, [fp, #8]
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldur x0, [x29, #8]
+;   ldp x29, x30, [sp], #0x10
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/iabs.clif b/cranelift/filetests/filetests/isa/aarch64/iabs.clif
index 8c50cc4562..0a47f447b0 100644
--- a/cranelift/filetests/filetests/isa/aarch64/iabs.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/iabs.clif
@@ -8,9 +8,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.16b, v0.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.16b, v0.16b
+;   ret
 
 function %f2(i8x8) -> i8x8 {
 block0(v0: i8x8):
@@ -18,9 +24,15 @@ block0(v0: i8x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.8b, v0.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.8b, v0.8b
+;   ret
 
 function %f3(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -28,9 +40,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.8h, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.8h, v0.8h
+;   ret
 
 function %f4(i16x4) -> i16x4 {
 block0(v0: i16x4):
@@ -38,9 +56,15 @@ block0(v0: i16x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.4h, v0.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.4h, v0.4h
+;   ret
 
 function %f5(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -48,9 +72,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.4s, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.4s, v0.4s
+;   ret
 
 function %f6(i32x2) -> i32x2 {
 block0(v0: i32x2):
@@ -58,9 +88,15 @@ block0(v0: i32x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.2s, v0.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.2s, v0.2s
+;   ret
 
 function %f7(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -68,9 +104,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   abs v0.2d, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   abs v0.2d, v0.2d
+;   ret
 
 function %f8(i8) -> i8 {
 block0(v0: i8):
@@ -78,11 +120,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w2, w0
 ;   subs wzr, w2, #0
 ;   csneg x0, x2, x2, gt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w2, w0
+;   cmp w2, #0
+;   cneg x0, x2, le
+;   ret
 
 function %f9(i16) -> i16 {
 block0(v0: i16):
@@ -90,11 +140,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth w2, w0
 ;   subs wzr, w2, #0
 ;   csneg x0, x2, x2, gt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w2, w0
+;   cmp w2, #0
+;   cneg x0, x2, le
+;   ret
 
 function %f10(i32) -> i32 {
 block0(v0: i32):
@@ -102,10 +160,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #0
 ;   csneg x0, x0, x0, gt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0
+;   cneg x0, x0, le
+;   ret
 
 function %f11(i64) -> i64 {
 block0(v0: i64):
@@ -113,7 +178,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   csneg x0, x0, x0, gt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   cneg x0, x0, le
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/aarch64/icmp-const.clif b/cranelift/filetests/filetests/isa/aarch64/icmp-const.clif
index 9911422450..9645d9b82d 100644
--- a/cranelift/filetests/filetests/isa/aarch64/icmp-const.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/icmp-const.clif
@@ -12,10 +12,17 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #1118208
 ;   cset x0, hi
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x111, lsl #12
+;   cset x0, hi
+;   ret
 
 function %b(i32) -> i8 {
 block0(v0: i32):
@@ -24,10 +31,17 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #1118208
 ;   cset x0, hs
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x111, lsl #12
+;   cset x0, hs
+;   ret
 
 function %c(i32) -> i8 {
 block0(v0: i32):
@@ -36,12 +50,21 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #4369
 ;   movk w3, w3, #17, LSL #16
 ;   subs wzr, w0, w3
 ;   cset x0, hs
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #0x1111
+;   movk w3, #0x11, lsl #16
+;   cmp w0, w3
+;   cset x0, hs
+;   ret
 
 function %d(i32) -> i8 {
 block0(v0: i32):
@@ -50,12 +73,21 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #4368
 ;   movk w3, w3, #17, LSL #16
 ;   subs wzr, w0, w3
 ;   cset x0, hs
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #0x1110
+;   movk w3, #0x11, lsl #16
+;   cmp w0, w3
+;   cset x0, hs
+;   ret
 
 function %e(i32) -> i8 {
 block0(v0: i32):
@@ -64,10 +96,17 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #1118208
 ;   cset x0, gt
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x111, lsl #12
+;   cset x0, gt
+;   ret
 
 function %f(i32) -> i8 {
 block0(v0: i32):
@@ -76,10 +115,17 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, #1118208
 ;   cset x0, ge
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #0x111, lsl #12
+;   cset x0, ge
+;   ret
 
 function %g(i32) -> i8 {
 block0(v0: i32):
@@ -88,12 +134,21 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #4369
 ;   movk w3, w3, #17, LSL #16
 ;   subs wzr, w0, w3
 ;   cset x0, ge
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #0x1111
+;   movk w3, #0x11, lsl #16
+;   cmp w0, w3
+;   cset x0, ge
+;   ret
 
 function %h(i32) -> i8 {
 block0(v0: i32):
@@ -102,10 +157,19 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #4368
 ;   movk w3, w3, #17, LSL #16
 ;   subs wzr, w0, w3
 ;   cset x0, ge
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #0x1110
+;   movk w3, #0x11, lsl #16
+;   cmp w0, w3
+;   cset x0, ge
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif
index badca4c653..0afd8474ea 100644
--- a/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif
@@ -13,6 +13,7 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #56780
 ;   uxth w2, w0
@@ -20,4 +21,13 @@ block0:
 ;   subs wzr, w2, w4, UXTH
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0xddcc
+;   uxth w2, w0
+;   mov w4, #0xddcc
+;   cmp w2, w4, uxth
+;   cset x0, ne
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/inline-probestack.clif b/cranelift/filetests/filetests/isa/aarch64/inline-probestack.clif
index 38838174b9..d18b96a961 100644
--- a/cranelift/filetests/filetests/isa/aarch64/inline-probestack.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/inline-probestack.clif
@@ -15,6 +15,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #2048
@@ -23,6 +24,16 @@ block0:
 ;   add sp, sp, #2048
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x800
+; block0: ; offset 0xc
+;   mov x0, sp
+;   add sp, sp, #0x800
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %unrolled() -> i64 system_v {
 ss0 = explicit_slot 12288
@@ -32,6 +43,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movn x16, #4095 ; str wzr, [sp, x16, SXTX]
@@ -43,6 +55,22 @@ block0:
 ;   add sp, sp, #12288
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov x16, #-0x1000
+;   str wzr, [sp, x16, sxtx]
+;   mov x16, #-0x2000
+;   str wzr, [sp, x16, sxtx]
+;   mov x16, #-0x3000
+;   str wzr, [sp, x16, sxtx]
+;   sub sp, sp, #3, lsl #12
+; block0: ; offset 0x24
+;   mov x0, sp
+;   add sp, sp, #3, lsl #12
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %large() -> i64 system_v {
 ss0 = explicit_slot 100000
@@ -52,6 +80,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz x16, #0
@@ -68,4 +97,25 @@ block0:
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov x16, #0
+;   mov w17, #0x86a0
+;   movk w17, #1, lsl #16
+;   sub x16, x16, #1, lsl #12
+;   str wzr, [sp, x16]
+;   cmn x16, x17
+;   b.gt #0x14
+;   mov w16, #0x86a0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x30
+;   mov x0, sp
+;   mov w16, #0x86a0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/jumptable.clif b/cranelift/filetests/filetests/isa/aarch64/jumptable.clif
index 1b2b2fd09b..dff6b5054a 100644
--- a/cranelift/filetests/filetests/isa/aarch64/jumptable.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/jumptable.clif
@@ -27,6 +27,7 @@ block5(v5: i32):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   emit_island 44
 ;   subs wzr, w0, #3
@@ -54,4 +55,35 @@ block5(v5: i32):
 ; block9:
 ;   add w0, w0, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, #3
+;   b.hs #0x2c
+;   csel x15, xzr, x0, hs
+;   csdb
+;   adr x14, #0x20
+;   ldrsw x15, [x14, w15, uxtw #2]
+;   add x14, x14, x15
+;   br x14
+;   .byte 0x14, 0x00, 0x00, 0x00
+;   .byte 0x1c, 0x00, 0x00, 0x00
+;   .byte 0x24, 0x00, 0x00, 0x00
+; block1: ; offset 0x2c
+;   mov w5, #4
+; block2: ; offset 0x30
+;   b #0x48
+; block3: ; offset 0x34
+;   mov w5, #1
+; block4: ; offset 0x38
+;   b #0x48
+; block5: ; offset 0x3c
+;   mov w5, #2
+; block6: ; offset 0x40
+;   b #0x48
+; block7: ; offset 0x44
+;   mov w5, #3
+; block8: ; offset 0x48
+;   add w0, w0, w5
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/leaf.clif b/cranelift/filetests/filetests/isa/aarch64/leaf.clif
index 1e797eb0ec..d025e3341f 100644
--- a/cranelift/filetests/filetests/isa/aarch64/leaf.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/leaf.clif
@@ -10,6 +10,11 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/leaf_with_preserve_frame_pointers.clif b/cranelift/filetests/filetests/isa/aarch64/leaf_with_preserve_frame_pointers.clif
index e61389350a..8b662ade04 100644
--- a/cranelift/filetests/filetests/isa/aarch64/leaf_with_preserve_frame_pointers.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/leaf_with_preserve_frame_pointers.clif
@@ -10,9 +10,17 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+; block0: ; offset 0x8
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/multivalue-ret.clif b/cranelift/filetests/filetests/isa/aarch64/multivalue-ret.clif
index 1d93513ba3..dd95365acc 100644
--- a/cranelift/filetests/filetests/isa/aarch64/multivalue-ret.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/multivalue-ret.clif
@@ -9,8 +9,15 @@ block1:
   return v0, v1
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #1
 ;   movz x1, #2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #1
+;   mov x1, #2
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/narrow-arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/narrow-arithmetic.clif
index 30373affab..58b52ea244 100644
--- a/cranelift/filetests/filetests/isa/aarch64/narrow-arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/narrow-arithmetic.clif
@@ -8,9 +8,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, w1
+;   ret
 
 function %add16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -18,9 +24,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, w1
+;   ret
 
 function %add32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -28,9 +40,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, w1
+;   ret
 
 function %add32_8(i32, i8) -> i32 {
 block0(v0: i32, v1: i8):
@@ -39,9 +57,15 @@ block0(v0: i32, v1: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   add w0, w0, w1, SXTB
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add w0, w0, w1, sxtb
+;   ret
 
 function %add64_32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -50,7 +74,13 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   add x0, x0, x1, SXTW
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x0, w1, sxtw
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/pinned-reg.clif b/cranelift/filetests/filetests/isa/aarch64/pinned-reg.clif
index 1e2669d314..e9a14f2acc 100644
--- a/cranelift/filetests/filetests/isa/aarch64/pinned-reg.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/pinned-reg.clif
@@ -10,9 +10,17 @@ block0:
     return
 }
 
+; VCode:
 ; block0:
 ;   mov x1, x21
 ;   add x1, x1, #1
 ;   mov x21, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, x21
+;   add x1, x1, #1
+;   mov x21, x1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/prologue.clif b/cranelift/filetests/filetests/isa/aarch64/prologue.clif
index 28845df1a1..420ac5365b 100644
--- a/cranelift/filetests/filetests/isa/aarch64/prologue.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/prologue.clif
@@ -75,6 +75,7 @@ block0(v0: f64):
     return v62
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   stp d14, d15, [sp, #-16]!
@@ -150,6 +151,83 @@ block0(v0: f64):
 ;   ldp d14, d15, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   stp d14, d15, [sp, #-0x10]!
+;   stp d12, d13, [sp, #-0x10]!
+;   stp d10, d11, [sp, #-0x10]!
+;   stp d8, d9, [sp, #-0x10]!
+; block0: ; offset 0x18
+;   fadd d23, d0, d0
+;   fadd d24, d0, d0
+;   fadd d25, d0, d0
+;   fadd d26, d0, d0
+;   fadd d27, d0, d0
+;   fadd d28, d0, d0
+;   fadd d29, d0, d0
+;   fadd d30, d0, d0
+;   fadd d31, d0, d0
+;   fadd d1, d0, d0
+;   fadd d2, d0, d0
+;   fadd d3, d0, d0
+;   fadd d4, d0, d0
+;   fadd d5, d0, d0
+;   fadd d6, d0, d0
+;   fadd d7, d0, d0
+;   fadd d16, d0, d0
+;   fadd d17, d0, d0
+;   fadd d18, d0, d0
+;   fadd d19, d0, d0
+;   fadd d20, d0, d0
+;   fadd d21, d0, d0
+;   fadd d22, d0, d0
+;   fadd d15, d0, d0
+;   fadd d8, d0, d0
+;   fadd d9, d0, d0
+;   fadd d10, d0, d0
+;   fadd d11, d0, d0
+;   fadd d12, d0, d0
+;   fadd d13, d0, d0
+;   fadd d14, d0, d0
+;   fadd d23, d0, d23
+;   fadd d24, d24, d25
+;   fadd d25, d26, d27
+;   fadd d26, d28, d29
+;   fadd d27, d30, d31
+;   fadd d28, d1, d2
+;   fadd d29, d3, d4
+;   fadd d30, d5, d6
+;   fadd d31, d7, d16
+;   fadd d0, d17, d18
+;   fadd d1, d19, d20
+;   fadd d2, d21, d22
+;   fadd d3, d15, d8
+;   fadd d4, d9, d10
+;   fadd d5, d11, d12
+;   fadd d6, d13, d14
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d27, d31, d0
+;   fadd d28, d1, d2
+;   fadd d29, d3, d4
+;   fadd d30, d5, d6
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d0, d23, d24
+;   ldp d8, d9, [sp], #0x10
+;   ldp d10, d11, [sp], #0x10
+;   ldp d12, d13, [sp], #0x10
+;   ldp d14, d15, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %f2(i64) -> i64 {
 block0(v0: i64):
@@ -197,6 +275,7 @@ block0(v0: i64):
     return v36
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
@@ -242,4 +321,51 @@ block0(v0: i64):
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x28, [sp, #-0x10]!
+;   stp x21, x27, [sp, #-0x10]!
+; block0: ; offset 0x10
+;   add x5, x0, x0
+;   add x6, x0, x5
+;   add x7, x0, x6
+;   add x8, x0, x7
+;   add x9, x0, x8
+;   add x10, x0, x9
+;   add x11, x0, x10
+;   add x12, x0, x11
+;   add x13, x0, x12
+;   add x14, x0, x13
+;   add x15, x0, x14
+;   add x1, x0, x15
+;   add x2, x0, x1
+;   add x3, x0, x2
+;   add x4, x0, x3
+;   add x27, x0, x4
+;   add x28, x0, x27
+;   add x21, x0, x28
+;   add x5, x0, x5
+;   add x6, x6, x7
+;   add x7, x8, x9
+;   add x8, x10, x11
+;   add x9, x12, x13
+;   add x10, x14, x15
+;   add x11, x1, x2
+;   add x12, x3, x4
+;   add x13, x27, x28
+;   add x5, x21, x5
+;   add x6, x6, x7
+;   add x7, x8, x9
+;   add x8, x10, x11
+;   add x9, x12, x13
+;   add x5, x5, x6
+;   add x6, x7, x8
+;   add x5, x9, x5
+;   add x0, x6, x5
+;   ldp x21, x27, [sp], #0x10
+;   ldr x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/reduce.clif b/cranelift/filetests/filetests/isa/aarch64/reduce.clif
index 9f85ce9689..a1edec3427 100644
--- a/cranelift/filetests/filetests/isa/aarch64/reduce.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/reduce.clif
@@ -8,8 +8,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_32(i128) -> i32 {
 block0(v0: i128):
@@ -17,8 +22,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_16(i128) -> i16 {
 block0(v0: i128):
@@ -26,8 +36,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_8(i128) -> i8 {
 block0(v0: i128):
@@ -35,6 +50,11 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif b/cranelift/filetests/filetests/isa/aarch64/reftypes.clif
index db4934eee3..e4c7825a7f 100644
--- a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/reftypes.clif
@@ -7,8 +7,13 @@ block0(v0: r64):
   return v0
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %f1(r64) -> i8 {
 block0(v0: r64):
@@ -16,10 +21,17 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   subs xzr, x0, #0
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp x0, #0
+;   cset x0, eq
+;   ret
 
 function %f2(r64) -> i8 {
 block0(v0: r64):
@@ -27,10 +39,17 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   adds xzr, x0, #1
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmn x0, #1
+;   cset x0, eq
+;   ret
 
 function %f3() -> r64 {
 block0:
@@ -38,9 +57,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   movz x0, #0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x0, #0
+;   ret
 
 function %f4(r64, r64) -> r64, r64, r64 {
     fn0 = %f(r64) -> i8
@@ -62,6 +87,7 @@ block3(v7: r64, v8: r64):
     return v7, v8, v9
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #32
@@ -93,4 +119,35 @@ block3(v7: r64, v8: r64):
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x20
+; block0: ; offset 0xc
+;   stur x0, [sp, #8]
+;   stur x1, [sp, #0x10]
+;   ldr x1, #0x1c
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x1
+;   mov x15, sp
+;   ldur x6, [sp, #8]
+;   str x6, [x15]
+;   uxtb w0, w0
+;   cbz x0, #0x48
+; block1: ; offset 0x3c
+;   mov x0, x6
+;   ldur x1, [sp, #0x10]
+;   b #0x50
+; block2: ; offset 0x48
+;   mov x1, x6
+;   ldur x0, [sp, #0x10]
+; block3: ; offset 0x50
+;   mov x2, sp
+;   ldr x2, [x2]
+;   add sp, sp, #0x20
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/select.clif b/cranelift/filetests/filetests/isa/aarch64/select.clif
index 29406b6a9c..8ebdabaa73 100644
--- a/cranelift/filetests/filetests/isa/aarch64/select.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/select.clif
@@ -9,10 +9,17 @@ block0(v0: i32, v1: i32, v2: i64, v3: i64):
     return v6
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, w1
 ;   csel x0, x2, x3, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, w1
+;   csel x0, x2, x3, eq
+;   ret
 
 function %f0(f32, f32, i64, i64) -> i64 {
 block0(v0: f32, v1: f32, v2: i64, v3: i64):
@@ -22,8 +29,15 @@ block0(v0: f32, v1: f32, v2: i64, v3: i64):
     return v6
 }
 
+; VCode:
 ; block0:
 ;   fcmp s0, s1
 ;   csel x0, x0, x1, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcmp s0, s1
+;   csel x0, x0, x1, eq
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/shift-op.clif b/cranelift/filetests/filetests/isa/aarch64/shift-op.clif
index f2400cc8df..808f5f0926 100644
--- a/cranelift/filetests/filetests/isa/aarch64/shift-op.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/shift-op.clif
@@ -10,9 +10,15 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   add x0, x0, x0, LSL 3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add x0, x0, x0, lsl #3
+;   ret
 
 function %f(i32) -> i32 {
 block0(v0: i32):
@@ -21,7 +27,13 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl w0, w0, #21
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl w0, w0, #0x15
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif b/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif
index afb88e2009..e70b7ae1b8 100644
--- a/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif
@@ -12,6 +12,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x5, #128
 ;   sub x7, x5, x2
@@ -36,6 +37,32 @@ block0(v0: i128, v1: i128):
 ;   orr x1, x8, x9
 ;   orr x0, x6, x7
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, #0x80
+;   sub x7, x5, x2
+;   lsr x9, x0, x2
+;   lsr x11, x1, x2
+;   mvn w13, w2
+;   lsl x15, x1, #1
+;   lsl x3, x15, x13
+;   orr x3, x9, x3
+;   tst x2, #0x40
+;   csel x6, x11, x3, ne
+;   csel x8, xzr, x11, ne
+;   lsl x10, x0, x7
+;   lsl x12, x1, x7
+;   mvn w14, w7
+;   lsr x0, x0, #1
+;   lsr x2, x0, x14
+;   orr x4, x12, x2
+;   tst x7, #0x40
+;   csel x7, xzr, x10, ne
+;   csel x9, x10, x4, ne
+;   orr x1, x8, x9
+;   orr x0, x6, x7
+;   ret
 
 function %f0(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -43,9 +70,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ror x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ror x0, x0, x1
+;   ret
 
 function %f1(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -53,9 +86,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ror w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ror w0, w0, w1
+;   ret
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -63,6 +102,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxth w3, w0
 ;   and w5, w1, #15
@@ -72,6 +112,17 @@ block0(v0: i16, v1: i16):
 ;   lsl w13, w3, w9
 ;   orr w0, w13, w11
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w3, w0
+;   and w5, w1, #0xf
+;   sub w7, w5, #0x10
+;   neg w9, w7
+;   lsr w11, w3, w5
+;   lsl w13, w3, w9
+;   orr w0, w13, w11
+;   ret
 
 function %f3(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -79,6 +130,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxtb w3, w0
 ;   and w5, w1, #7
@@ -88,6 +140,17 @@ block0(v0: i8, v1: i8):
 ;   lsl w13, w3, w9
 ;   orr w0, w13, w11
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w3, w0
+;   and w5, w1, #7
+;   sub w7, w5, #8
+;   neg w9, w7
+;   lsr w11, w3, w5
+;   lsl w13, w3, w9
+;   orr w0, w13, w11
+;   ret
 
 function %i128_rotl(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -95,6 +158,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x5, #128
 ;   sub x7, x5, x2
@@ -119,6 +183,32 @@ block0(v0: i128, v1: i128):
 ;   orr x0, x6, x7
 ;   orr x1, x8, x9
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x5, #0x80
+;   sub x7, x5, x2
+;   lsl x9, x0, x2
+;   lsl x11, x1, x2
+;   mvn w13, w2
+;   lsr x15, x0, #1
+;   lsr x3, x15, x13
+;   orr x3, x11, x3
+;   tst x2, #0x40
+;   csel x6, xzr, x9, ne
+;   csel x8, x9, x3, ne
+;   lsr x10, x0, x7
+;   lsr x12, x1, x7
+;   mvn w14, w7
+;   lsl x0, x1, #1
+;   lsl x2, x0, x14
+;   orr x4, x10, x2
+;   tst x7, #0x40
+;   csel x7, x12, x4, ne
+;   csel x9, xzr, x12, ne
+;   orr x0, x6, x7
+;   orr x1, x8, x9
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -126,10 +216,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub x3, xzr, x1
 ;   ror x0, x0, x3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg x3, x1
+;   ror x0, x0, x3
+;   ret
 
 function %f5(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -137,10 +234,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   ror w0, w0, w3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   ror w0, w0, w3
+;   ret
 
 function %f6(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -148,6 +252,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   uxth w5, w0
@@ -158,6 +263,18 @@ block0(v0: i16, v1: i16):
 ;   lsl w15, w5, w11
 ;   orr w0, w15, w13
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   uxth w5, w0
+;   and w7, w3, #0xf
+;   sub w9, w7, #0x10
+;   neg w11, w9
+;   lsr w13, w5, w7
+;   lsl w15, w5, w11
+;   orr w0, w15, w13
+;   ret
 
 function %f7(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -165,6 +282,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub w3, wzr, w1
 ;   uxtb w5, w0
@@ -175,6 +293,18 @@ block0(v0: i8, v1: i8):
 ;   lsl w15, w5, w11
 ;   orr w0, w15, w13
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg w3, w1
+;   uxtb w5, w0
+;   and w7, w3, #7
+;   sub w9, w7, #8
+;   neg w11, w9
+;   lsr w13, w5, w7
+;   lsl w15, w5, w11
+;   orr w0, w15, w13
+;   ret
 
 function %f8(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -182,9 +312,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x0, x0, x1
+;   ret
 
 function %f9(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -192,9 +328,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr w0, w0, w1
+;   ret
 
 function %f10(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -202,11 +344,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxth w3, w0
 ;   and w5, w1, #15
 ;   lsr w0, w3, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w3, w0
+;   and w5, w1, #0xf
+;   lsr w0, w3, w5
+;   ret
 
 function %f11(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -214,11 +364,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxtb w3, w0
 ;   and w5, w1, #7
 ;   lsr w0, w3, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w3, w0
+;   and w5, w1, #7
+;   lsr w0, w3, w5
+;   ret
 
 function %f12(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -226,9 +384,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl x0, x0, x1
+;   ret
 
 function %f13(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -236,9 +400,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl w0, w0, w1
+;   ret
 
 function %f14(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -246,10 +416,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   and w3, w1, #15
 ;   lsl w0, w0, w3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w3, w1, #0xf
+;   lsl w0, w0, w3
+;   ret
 
 function %f15(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -257,10 +434,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   and w3, w1, #7
 ;   lsl w0, w0, w3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w3, w1, #7
+;   lsl w0, w0, w3
+;   ret
 
 function %f16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -268,9 +452,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   asr x0, x0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   asr x0, x0, x1
+;   ret
 
 function %f17(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -278,9 +468,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   asr w0, w0, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   asr w0, w0, w1
+;   ret
 
 function %f18(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -288,11 +484,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxth w3, w0
 ;   and w5, w1, #15
 ;   asr w0, w3, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w3, w0
+;   and w5, w1, #0xf
+;   asr w0, w3, w5
+;   ret
 
 function %f19(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -300,11 +504,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sxtb w3, w0
 ;   and w5, w1, #7
 ;   asr w0, w3, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w3, w0
+;   and w5, w1, #7
+;   asr w0, w3, w5
+;   ret
 
 function %f20(i64) -> i64 {
 block0(v0: i64):
@@ -313,9 +525,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ror x0, x0, #17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ror x0, x0, #0x11
+;   ret
 
 function %f21(i64) -> i64 {
 block0(v0: i64):
@@ -324,9 +542,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ror x0, x0, #47
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ror x0, x0, #0x2f
+;   ret
 
 function %f22(i32) -> i32 {
 block0(v0: i32):
@@ -335,9 +559,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ror w0, w0, #15
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ror w0, w0, #0xf
+;   ret
 
 function %f23(i16) -> i16 {
 block0(v0: i16):
@@ -346,12 +576,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxth w2, w0
 ;   lsr w4, w2, #6
 ;   lsl w6, w2, #10
 ;   orr w0, w6, w4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w2, w0
+;   lsr w4, w2, #6
+;   lsl w6, w2, #0xa
+;   orr w0, w6, w4
+;   ret
 
 function %f24(i8) -> i8 {
 block0(v0: i8):
@@ -360,12 +599,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uxtb w2, w0
 ;   lsr w4, w2, #5
 ;   lsl w6, w2, #3
 ;   orr w0, w6, w4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w2, w0
+;   lsr w4, w2, #5
+;   lsl w6, w2, #3
+;   orr w0, w6, w4
+;   ret
 
 function %f25(i64) -> i64 {
 block0(v0: i64):
@@ -374,9 +622,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsr x0, x0, #17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsr x0, x0, #0x11
+;   ret
 
 function %f26(i64) -> i64 {
 block0(v0: i64):
@@ -385,9 +639,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   asr x0, x0, #17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   asr x0, x0, #0x11
+;   ret
 
 function %f27(i64) -> i64 {
 block0(v0: i64):
@@ -396,7 +656,13 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lsl x0, x0, #17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lsl x0, x0, #0x11
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
index bae5a4f5c4..3487163f41 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
@@ -8,9 +8,15 @@ block0(v0: i8x8, v1: i8x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.8b, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.8b, v0.8b, v1.8b
+;   ret
 
 function %average_rounding_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -18,9 +24,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.16b, v0.16b, v1.16b
+;   ret
 
 function %average_rounding_i16x4(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
@@ -28,9 +40,15 @@ block0(v0: i16x4, v1: i16x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.4h, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.4h, v0.4h, v1.4h
+;   ret
 
 function %average_rounding_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -38,9 +56,15 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.8h, v0.8h, v1.8h
+;   ret
 
 function %average_rounding_i32x2(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
@@ -48,9 +72,15 @@ block0(v0: i32x2, v1: i32x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.2s, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.2s, v0.2s, v1.2s
+;   ret
 
 function %average_rounding_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -58,9 +88,15 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   urhadd v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   urhadd v0.4s, v0.4s, v1.4s
+;   ret
 
 function %average_rounding_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -68,6 +104,7 @@ block0(v0: i64x2, v1: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x4, #1
 ;   dup v4.2d, x4
@@ -78,4 +115,16 @@ block0(v0: i64x2, v1: i64x2):
 ;   add v23.2d, v19.2d, v21.2d
 ;   add v0.2d, v17.2d, v23.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x4, #1
+;   dup v4.2d, x4
+;   orr v7.16b, v0.16b, v1.16b
+;   and v17.16b, v7.16b, v4.16b
+;   ushr v19.2d, v0.2d, #1
+;   ushr v21.2d, v1.2d, #1
+;   add v23.2d, v19.2d, v21.2d
+;   add v0.2d, v17.2d, v23.2d
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif
index d14f2a31d4..0ae0eb407c 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif
@@ -8,9 +8,15 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and v0.16b, v0.16b, v1.16b
+;   ret
 
 function %band_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -18,9 +24,15 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and v0.16b, v0.16b, v1.16b
+;   ret
 
 function %band_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -28,9 +40,15 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bor_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -38,9 +56,15 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bor_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -48,9 +72,15 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -58,9 +88,15 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   orr v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   orr v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bxor_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -68,9 +104,15 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bxor_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -78,9 +120,15 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bxor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -88,9 +136,15 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   eor v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   eor v0.16b, v0.16b, v1.16b
+;   ret
 
 function %bitselect_i16x8() -> i16x8 {
 block0:
@@ -101,12 +155,21 @@ block0:
     return v3
 }
 
+; VCode:
 ; block0:
 ;   movi v0.16b, #0
 ;   movi v3.16b, #0
 ;   movi v4.16b, #0
 ;   bsl v0.16b, v0.16b, v3.16b, v4.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v0.16b, #0
+;   movi v3.16b, #0
+;   movi v4.16b, #0
+;   bsl v0.16b, v3.16b, v4.16b
+;   ret
 
 function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8, v2: i16x8):
@@ -114,9 +177,15 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   bsl v0.16b, v0.16b, v1.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bsl v0.16b, v1.16b, v2.16b
+;   ret
 
 function %vselect_f32x4(i32x4, f32x4, f32x4) -> f32x4 {
 block0(v0: i32x4, v1: f32x4, v2: f32x4):
@@ -124,9 +193,15 @@ block0(v0: i32x4, v1: f32x4, v2: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   bsl v0.16b, v0.16b, v1.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bsl v0.16b, v1.16b, v2.16b
+;   ret
 
 function %vselect_f64x2(i64x2, f64x2, f64x2) -> f64x2 {
 block0(v0: i64x2, v1: f64x2, v2: f64x2):
@@ -134,9 +209,15 @@ block0(v0: i64x2, v1: f64x2, v2: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   bsl v0.16b, v0.16b, v1.16b, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bsl v0.16b, v1.16b, v2.16b
+;   ret
 
 function %ishl_i8x16(i32) -> i8x16 {
 block0(v0: i32):
@@ -145,12 +226,26 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   and w3, w0, #7
 ;   dup v6.16b, w3
 ;   sshl v0.16b, v5.16b, v6.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr q5, #8
+;   b #0x18
+;   .byte 0x00, 0x01, 0x02, 0x03
+;   .byte 0x04, 0x05, 0x06, 0x07
+;   add w8, w8, w10, lsl #2
+;   .byte 0x0c, 0x0d, 0x0e, 0x0f
+;   and w3, w0, #7
+;   dup v6.16b, w3
+;   sshl v0.16b, v5.16b, v6.16b
+;   ret
 
 function %ushr_i8x16_imm() -> i8x16 {
 block0:
@@ -160,6 +255,7 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   movz w1, #1
@@ -168,6 +264,21 @@ block0:
 ;   dup v7.16b, w5
 ;   ushl v0.16b, v5.16b, v7.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr q5, #8
+;   b #0x18
+;   .byte 0x00, 0x01, 0x02, 0x03
+;   .byte 0x04, 0x05, 0x06, 0x07
+;   add w8, w8, w10, lsl #2
+;   .byte 0x0c, 0x0d, 0x0e, 0x0f
+;   mov w1, #1
+;   and w3, w1, #7
+;   neg x5, x3
+;   dup v7.16b, w5
+;   ushl v0.16b, v5.16b, v7.16b
+;   ret
 
 function %sshr_i8x16(i32) -> i8x16 {
 block0(v0: i32):
@@ -176,6 +287,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   and w3, w0, #7
@@ -183,6 +295,20 @@ block0(v0: i32):
 ;   dup v7.16b, w5
 ;   sshl v0.16b, v6.16b, v7.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr q6, #8
+;   b #0x18
+;   .byte 0x00, 0x01, 0x02, 0x03
+;   .byte 0x04, 0x05, 0x06, 0x07
+;   add w8, w8, w10, lsl #2
+;   .byte 0x0c, 0x0d, 0x0e, 0x0f
+;   and w3, w0, #7
+;   neg x5, x3
+;   dup v7.16b, w5
+;   sshl v0.16b, v6.16b, v7.16b
+;   ret
 
 function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
 block0(v0: i8x16, v1: i32):
@@ -190,6 +316,7 @@ block0(v0: i8x16, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w3, #3
 ;   and w5, w3, #7
@@ -197,6 +324,15 @@ block0(v0: i8x16, v1: i32):
 ;   dup v17.16b, w7
 ;   sshl v0.16b, v0.16b, v17.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w3, #3
+;   and w5, w3, #7
+;   neg x7, x5
+;   dup v17.16b, w7
+;   sshl v0.16b, v0.16b, v17.16b
+;   ret
 
 function %sshr_i64x2(i64x2, i32) -> i64x2 {
 block0(v0: i64x2, v1: i32):
@@ -204,10 +340,19 @@ block0(v0: i64x2, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and w3, w0, #63
 ;   sub x5, xzr, x3
 ;   dup v7.2d, x5
 ;   sshl v0.2d, v0.2d, v7.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and w3, w0, #0x3f
+;   neg x5, x3
+;   dup v7.2d, x5
+;   sshl v0.2d, v0.2d, v7.2d
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif b/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif
index 03a609296f..ab246283e4 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif
@@ -8,10 +8,17 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   cmeq v3.4s, v0.4s, v1.4s
 ;   mvn v0.16b, v3.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v3.4s, v0.4s, v1.4s
+;   mvn v0.16b, v3.16b
+;   ret
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -19,9 +26,15 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   cmhi v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmhi v0.4s, v0.4s, v1.4s
+;   ret
 
 function %icmp_sge_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -29,9 +42,15 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   cmge v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmge v0.8h, v0.8h, v1.8h
+;   ret
 
 function %icmp_uge_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -39,7 +58,13 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   cmhs v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmhs v0.16b, v0.16b, v1.16b
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-extmul.clif b/cranelift/filetests/filetests/isa/aarch64/simd-extmul.clif
index 532cdb82d2..f61d6b0072 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-extmul.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-extmul.clif
@@ -10,9 +10,15 @@ block0(v0: i8x16, v1: i8x16):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull v0.8h, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull v0.8h, v0.8b, v1.8b
+;   ret
 
 function %fn2(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -22,9 +28,15 @@ block0(v0: i8x16, v1: i8x16):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull2 v0.8h, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull2 v0.8h, v0.16b, v1.16b
+;   ret
 
 function %fn3(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -34,9 +46,15 @@ block0(v0: i16x8, v1: i16x8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull v0.4s, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull v0.4s, v0.4h, v1.4h
+;   ret
 
 function %fn4(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -46,9 +64,15 @@ block0(v0: i16x8, v1: i16x8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull2 v0.4s, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull2 v0.4s, v0.8h, v1.8h
+;   ret
 
 function %fn5(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -58,9 +82,15 @@ block0(v0: i32x4, v1: i32x4):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull v0.2d, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull v0.2d, v0.2s, v1.2s
+;   ret
 
 function %fn6(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -70,9 +100,15 @@ block0(v0: i32x4, v1: i32x4):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   smull2 v0.2d, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smull2 v0.2d, v0.4s, v1.4s
+;   ret
 
 function %fn7(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -82,9 +118,15 @@ block0(v0: i8x16, v1: i8x16):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull v0.8h, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull v0.8h, v0.8b, v1.8b
+;   ret
 
 function %fn8(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -94,9 +136,15 @@ block0(v0: i8x16, v1: i8x16):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull2 v0.8h, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull2 v0.8h, v0.16b, v1.16b
+;   ret
 
 function %fn9(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -106,9 +154,15 @@ block0(v0: i16x8, v1: i16x8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull v0.4s, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull v0.4s, v0.4h, v1.4h
+;   ret
 
 function %fn10(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -118,9 +172,15 @@ block0(v0: i16x8, v1: i16x8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull2 v0.4s, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull2 v0.4s, v0.8h, v1.8h
+;   ret
 
 function %fn11(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -130,9 +190,15 @@ block0(v0: i32x4, v1: i32x4):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull v0.2d, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull v0.2d, v0.2s, v1.2s
+;   ret
 
 function %fn12(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -142,7 +208,13 @@ block0(v0: i32x4, v1: i32x4):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   umull2 v0.2d, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umull2 v0.2d, v0.4s, v1.4s
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif
index 3f725cae58..c83e56142d 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif
@@ -12,6 +12,7 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movi v30.16b, #0
 ;   movz x4, #1
@@ -19,6 +20,20 @@ block0:
 ;   ldr q3, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000
 ;   tbl v0.16b, { v30.16b, v31.16b }, v3.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v30.16b, #0
+;   mov x4, #1
+;   fmov s31, w4
+;   ldr q3, #0x14
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   add w0, w0, #0
+;   tbl v0.16b, {v30.16b, v31.16b}, v3.16b
+;   ret
 
 function %shuffle_same_ssa_value() -> i8x16 {
 block0:
@@ -27,6 +42,7 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x3, #1
 ;   fmov s31, w3
@@ -34,6 +50,20 @@ block0:
 ;   mov v30.16b, v31.16b
 ;   tbl v0.16b, { v30.16b, v31.16b }, v2.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x3, #1
+;   fmov s31, w3
+;   ldr q2, #0x10
+;   b #0x20
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   sbfx w0, w0, #0, #1
+;   mov v30.16b, v31.16b
+;   tbl v0.16b, {v30.16b, v31.16b}, v2.16b
+;   ret
 
 function %swizzle() -> i8x16 {
 block0:
@@ -43,11 +73,29 @@ block0:
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ldr q2, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   ldr q3, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   tbl v0.16b, { v2.16b }, v3.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr q2, #8
+;   b #0x18
+;   .byte 0x00, 0x01, 0x02, 0x03
+;   .byte 0x04, 0x05, 0x06, 0x07
+;   add w8, w8, w10, lsl #2
+;   .byte 0x0c, 0x0d, 0x0e, 0x0f
+;   ldr q3, #0x20
+;   b #0x30
+;   .byte 0x00, 0x01, 0x02, 0x03
+;   .byte 0x04, 0x05, 0x06, 0x07
+;   add w8, w8, w10, lsl #2
+;   .byte 0x0c, 0x0d, 0x0e, 0x0f
+;   tbl v0.16b, {v2.16b}, v3.16b
+;   ret
 
 function %splat_i8(i8) -> i8x16 {
 block0(v0: i8):
@@ -55,9 +103,15 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   dup v0.16b, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v0.16b, w0
+;   ret
 
 function %splat_i16() -> i16x8 {
 block0:
@@ -66,9 +120,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   movi v0.16b, #255
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v0.16b, #0xff
+;   ret
 
 function %splat_i32(i32) -> i32x4 {
 block0(v0: i32):
@@ -76,9 +136,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   dup v0.4s, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v0.4s, w0
+;   ret
 
 function %splat_f64(f64) -> f64x2 {
 block0(v0: f64):
@@ -86,9 +152,15 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   dup v0.2d, v0.d[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   dup v0.2d, v0.d[0]
+;   ret
 
 function %load32_zero_coalesced(i64) -> i32x4 {
 block0(v0: i64):
@@ -97,10 +169,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ldr w3, [x0]
 ;   fmov s0, w3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr w3, [x0]
+;   fmov s0, w3
+;   ret
 
 function %load32_zero_int(i32) -> i32x4 {
 block0(v0: i32):
@@ -108,9 +187,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, w0
+;   ret
 
 function %load32_zero_float(f32) -> f32x4 {
 block0(v0: f32):
@@ -118,7 +203,13 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, s0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif
index 4a2486bffe..e66fc671c3 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif
@@ -8,9 +8,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mvn v0.16b, v0.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvn v0.16b, v0.16b
+;   ret
 
 function %vany_true_i32x4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -18,12 +24,21 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   umaxp v2.4s, v0.4s, v0.4s
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umaxp v2.4s, v0.4s, v0.4s
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %vall_true_i64x2(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -31,10 +46,19 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.2d, v0.2d, #0
 ;   addp v4.2d, v2.2d, v2.2d
 ;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.2d, v0.2d, #0
+;   addp v4.2d, v2.2d, v2.2d
+;   fcmp d4, d4
+;   cset x0, eq
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-min-max.clif b/cranelift/filetests/filetests/isa/aarch64/simd-min-max.clif
index 8c85fde8d2..04bdd3067f 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-min-max.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-min-max.clif
@@ -8,9 +8,15 @@ block0(v0: i8x8, v1: i8x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.8b, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.8b, v0.8b, v1.8b
+;   ret
 
 function %fn1(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -18,9 +24,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.16b, v0.16b, v1.16b
+;   ret
 
 function %fn2(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
@@ -28,9 +40,15 @@ block0(v0: i16x4, v1: i16x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.4h, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.4h, v0.4h, v1.4h
+;   ret
 
 function %fn3(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -38,9 +56,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.8h, v0.8h, v1.8h
+;   ret
 
 function %fn4(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
@@ -48,9 +72,15 @@ block0(v0: i32x2, v1: i32x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.2s, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.2s, v0.2s, v1.2s
+;   ret
 
 function %fn5(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -58,9 +88,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smin v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smin v0.4s, v0.4s, v1.4s
+;   ret
 
 function %fn6(i8x8, i8x8) -> i8x8 {
 block0(v0: i8x8, v1: i8x8):
@@ -68,9 +104,15 @@ block0(v0: i8x8, v1: i8x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.8b, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.8b, v0.8b, v1.8b
+;   ret
 
 function %fn7(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -78,9 +120,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.16b, v0.16b, v1.16b
+;   ret
 
 function %fn8(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
@@ -88,9 +136,15 @@ block0(v0: i16x4, v1: i16x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.4h, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.4h, v0.4h, v1.4h
+;   ret
 
 function %fn9(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -98,9 +152,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.8h, v0.8h, v1.8h
+;   ret
 
 function %fn10(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
@@ -108,9 +168,15 @@ block0(v0: i32x2, v1: i32x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.2s, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.2s, v0.2s, v1.2s
+;   ret
 
 function %fn11(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -118,9 +184,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umin v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umin v0.4s, v0.4s, v1.4s
+;   ret
 
 function %fn12(i8x8, i8x8) -> i8x8 {
 block0(v0: i8x8, v1: i8x8):
@@ -128,9 +200,15 @@ block0(v0: i8x8, v1: i8x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.8b, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.8b, v0.8b, v1.8b
+;   ret
 
 function %fn13(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -138,9 +216,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.16b, v0.16b, v1.16b
+;   ret
 
 function %fn14(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
@@ -148,9 +232,15 @@ block0(v0: i16x4, v1: i16x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.4h, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.4h, v0.4h, v1.4h
+;   ret
 
 function %fn15(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -158,9 +248,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.8h, v0.8h, v1.8h
+;   ret
 
 function %fn16(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
@@ -168,9 +264,15 @@ block0(v0: i32x2, v1: i32x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.2s, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.2s, v0.2s, v1.2s
+;   ret
 
 function %fn17(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -178,9 +280,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   smax v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   smax v0.4s, v0.4s, v1.4s
+;   ret
 
 function %fn18(i8x8, i8x8) -> i8x8 {
 block0(v0: i8x8, v1: i8x8):
@@ -188,9 +296,15 @@ block0(v0: i8x8, v1: i8x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.8b, v0.8b, v1.8b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.8b, v0.8b, v1.8b
+;   ret
 
 function %fn19(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -198,9 +312,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.16b, v0.16b, v1.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.16b, v0.16b, v1.16b
+;   ret
 
 function %fn20(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
@@ -208,9 +328,15 @@ block0(v0: i16x4, v1: i16x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.4h, v0.4h, v1.4h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.4h, v0.4h, v1.4h
+;   ret
 
 function %fn21(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -218,9 +344,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.8h, v0.8h, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.8h, v0.8h, v1.8h
+;   ret
 
 function %fn22(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
@@ -228,9 +360,15 @@ block0(v0: i32x2, v1: i32x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.2s, v0.2s, v1.2s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.2s, v0.2s, v1.2s
+;   ret
 
 function %fn23(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -238,7 +376,13 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   umax v0.4s, v0.4s, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   umax v0.4s, v0.4s, v1.4s
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif b/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif
index cd0e38d70d..4dd4e964b0 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif
@@ -8,11 +8,19 @@ block0(v0: i16x4, v1: i16x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   sqxtn v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   sqxtn v0.8b, v3.8h
+;   ret
 
 function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -20,10 +28,17 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.8b, v0.8h
 ;   sqxtn2 v0.16b, v0.16b, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.8b, v0.8h
+;   sqxtn2 v0.16b, v1.8h
+;   ret
 
 function %snarrow_i32x2(i32x2, i32x2) -> i16x4 {
 block0(v0: i32x2, v1: i32x2):
@@ -31,11 +46,19 @@ block0(v0: i32x2, v1: i32x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   sqxtn v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   sqxtn v0.4h, v3.4s
+;   ret
 
 function %snarrow_i32x4(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -43,10 +66,17 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.4h, v0.4s
 ;   sqxtn2 v0.8h, v0.8h, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.4h, v0.4s
+;   sqxtn2 v0.8h, v1.4s
+;   ret
 
 function %snarrow_i64x2(i64x2, i64x2) -> i32x4 {
 block0(v0: i64x2, v1: i64x2):
@@ -54,10 +84,17 @@ block0(v0: i64x2, v1: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.2s, v0.2d
 ;   sqxtn2 v0.4s, v0.4s, v1.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.2s, v0.2d
+;   sqxtn2 v0.4s, v1.2d
+;   ret
 
 function %unarrow_i16x4(i16x4, i16x4) -> i8x8 {
 block0(v0: i16x4, v1: i16x4):
@@ -65,11 +102,19 @@ block0(v0: i16x4, v1: i16x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   sqxtun v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   sqxtun v0.8b, v3.8h
+;   ret
 
 function %unarrow_i16x8(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -77,10 +122,17 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.8b, v0.8h
 ;   sqxtun2 v0.16b, v0.16b, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.8b, v0.8h
+;   sqxtun2 v0.16b, v1.8h
+;   ret
 
 function %unarrow_i32x2(i32x2, i32x2) -> i16x4 {
 block0(v0: i32x2, v1: i32x2):
@@ -88,11 +140,19 @@ block0(v0: i32x2, v1: i32x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   sqxtun v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   sqxtun v0.4h, v3.4s
+;   ret
 
 function %unarrow_i32x4(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -100,10 +160,17 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.4h, v0.4s
 ;   sqxtun2 v0.8h, v0.8h, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.4h, v0.4s
+;   sqxtun2 v0.8h, v1.4s
+;   ret
 
 function %unarrow_i64x2(i64x2, i64x2) -> i32x4 {
 block0(v0: i64x2, v1: i64x2):
@@ -111,10 +178,17 @@ block0(v0: i64x2, v1: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.2s, v0.2d
 ;   sqxtun2 v0.4s, v0.4s, v1.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.2s, v0.2d
+;   sqxtun2 v0.4s, v1.2d
+;   ret
 
 function %uunarrow_i16x4(i16x4, i16x4) -> i8x8 {
 block0(v0: i16x4, v1: i16x4):
@@ -122,11 +196,19 @@ block0(v0: i16x4, v1: i16x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   uqxtn v0.8b, v3.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   uqxtn v0.8b, v3.8h
+;   ret
 
 function %uunarrow_i16x8(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -134,10 +216,17 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.8b, v0.8h
 ;   uqxtn2 v0.16b, v0.16b, v1.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.8b, v0.8h
+;   uqxtn2 v0.16b, v1.8h
+;   ret
 
 function %uunarrow_i32x2(i32x2, i32x2) -> i16x4 {
 block0(v0: i32x2, v1: i32x2):
@@ -145,11 +234,19 @@ block0(v0: i32x2, v1: i32x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mov v3.16b, v0.16b
 ;   mov v3.d[1], v3.d[1], v1.d[0]
 ;   uqxtn v0.4h, v3.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v1.d[0]
+;   uqxtn v0.4h, v3.4s
+;   ret
 
 function %uunarrow_i32x4(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -157,10 +254,17 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.4h, v0.4s
 ;   uqxtn2 v0.8h, v0.8h, v1.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.4h, v0.4s
+;   uqxtn2 v0.8h, v1.4s
+;   ret
 
 function %uunarrow_i64x2(i64x2, i64x2) -> i32x4 {
 block0(v0: i64x2, v1: i64x2):
@@ -168,10 +272,17 @@ block0(v0: i64x2, v1: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.2s, v0.2d
 ;   uqxtn2 v0.4s, v0.4s, v1.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.2s, v0.2d
+;   uqxtn2 v0.4s, v1.2d
+;   ret
 
 function %snarrow_i16x8_zero(i16x8) -> i8x16 {
 block0(v0: i16x8):
@@ -180,9 +291,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.8b, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.8b, v0.8h
+;   ret
 
 function %snarrow_i32x4_zero(i32x4) -> i16x8 {
 block0(v0: i32x4):
@@ -191,9 +308,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.4h, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.4h, v0.4s
+;   ret
 
 function %snarrow_i64x2_zero(i64x2) -> i32x4 {
 block0(v0: i64x2):
@@ -202,9 +325,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtn v0.2s, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtn v0.2s, v0.2d
+;   ret
 
 function %unarrow_i16x8_zero(i16x8) -> i8x16 {
 block0(v0: i16x8):
@@ -213,9 +342,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.8b, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.8b, v0.8h
+;   ret
 
 function %unarrow_i32x4_zero(i32x4) -> i16x8 {
 block0(v0: i32x4):
@@ -224,9 +359,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.4h, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.4h, v0.4s
+;   ret
 
 function %unarrow_i64x2_zero(i64x2) -> i32x4 {
 block0(v0: i64x2):
@@ -235,9 +376,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sqxtun v0.2s, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqxtun v0.2s, v0.2d
+;   ret
 
 function %uunarrow_i16x8_zero(i16x8) -> i8x16 {
 block0(v0: i16x8):
@@ -246,9 +393,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.8b, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.8b, v0.8h
+;   ret
 
 function %uunarrow_i32x4_zero(i32x4) -> i16x8 {
 block0(v0: i32x4):
@@ -257,9 +410,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.4h, v0.4s
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.4h, v0.4s
+;   ret
 
 function %uunarrow_i64x2_zero(i64x2) -> i32x4 {
 block0(v0: i64x2):
@@ -268,7 +427,13 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uqxtn v0.2s, v0.2d
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uqxtn v0.2s, v0.2d
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-pairwise-add.clif b/cranelift/filetests/filetests/isa/aarch64/simd-pairwise-add.clif
index 9b3f24d5be..f4269385f7 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-pairwise-add.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-pairwise-add.clif
@@ -9,9 +9,15 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   saddlp v0.8h, v0.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   saddlp v0.8h, v0.16b
+;   ret
 
 function %fn2(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -21,9 +27,15 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   saddlp v0.4s, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   saddlp v0.4s, v0.8h
+;   ret
 
 function %fn3(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -33,9 +45,15 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   uaddlp v0.8h, v0.16b
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uaddlp v0.8h, v0.16b
+;   ret
 
 function %fn4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -45,7 +63,13 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   uaddlp v0.4s, v0.8h
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uaddlp v0.4s, v0.8h
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif b/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif
index 459ca00063..39b0ff6124 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif
@@ -8,12 +8,21 @@ block0(v0: i8x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uminv b2, v0.8b
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uminv b2, v0.8b
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %fn1(i8x16) -> i8 {
 block0(v0: i8x16):
@@ -21,12 +30,21 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uminv b2, v0.16b
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uminv b2, v0.16b
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %fn2(i16x4) -> i8 {
 block0(v0: i16x4):
@@ -34,12 +52,21 @@ block0(v0: i16x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uminv h2, v0.4h
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uminv h2, v0.4h
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %fn3(i16x8) -> i8 {
 block0(v0: i16x8):
@@ -47,12 +74,21 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uminv h2, v0.8h
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uminv h2, v0.8h
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %fn4(i32x2) -> i8 {
 block0(v0: i32x2):
@@ -60,12 +96,21 @@ block0(v0: i32x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x2, v0.d[0]
 ;   subs xzr, xzr, x2, LSR 32
 ;   ccmp w2, #0, #nZcv, ne
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, v0.d[0]
+;   cmp xzr, x2, lsr #32
+;   ccmp w2, #0, #4, ne
+;   cset x0, ne
+;   ret
 
 function %fn5(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -73,12 +118,21 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uminv s2, v0.4s
 ;   mov x4, v2.d[0]
 ;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uminv s2, v0.4s
+;   mov x4, v2.d[0]
+;   cmp x4, #0
+;   cset x0, ne
+;   ret
 
 function %fn6(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -86,10 +140,19 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   cmeq v2.2d, v0.2d, #0
 ;   addp v4.2d, v2.2d, v2.2d
 ;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmeq v2.2d, v0.2d, #0
+;   addp v4.2d, v2.2d, v2.2d
+;   fcmp d4, d4
+;   cset x0, eq
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd.clif b/cranelift/filetests/filetests/isa/aarch64/simd.clif
index 91da31460b..4933878ac3 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd.clif
@@ -9,11 +9,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #1
 ;   movk x1, x1, #1, LSL #48
 ;   dup v0.2d, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #1
+;   movk x1, #1, lsl #48
+;   dup v0.2d, x1
+;   ret
 
 function %f2() -> i16x8 {
 block0:
@@ -23,10 +31,17 @@ block0:
   return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #42679
 ;   dup v0.8h, w1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #0xa6b7
+;   dup v0.8h, w1
+;   ret
 
 function %f4(i32, i8x16, i8x16) -> i8x16 {
 block0(v0: i32, v1: i8x16, v2: i8x16):
@@ -34,10 +49,20 @@ block0(v0: i32, v1: i8x16, v2: i8x16):
    return v3
 }
 
+; VCode:
 ; block0:
 ;   subs wzr, w0, wzr
 ;   vcsel v0.16b, v0.16b, v1.16b, ne (if-then-else diamond)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cmp w0, wzr
+;   b.ne #0x10
+;   mov v0.16b, v1.16b
+;   b #0x14
+;   mov v0.16b, v0.16b
+;   ret
 
 function %f5(i64) -> i8x16 {
 block0(v0: i64):
@@ -46,9 +71,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ld1r { v0.16b }, [x0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld1r {v0.16b}, [x0]
+;   ret
 
 function %f6(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -59,10 +90,17 @@ block0(v0: i64, v1: i64):
   return v4, v5
 }
 
+; VCode:
 ; block0:
 ;   ld1r { v0.16b }, [x0]
 ;   ld1r { v1.16b }, [x1]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld1r {v0.16b}, [x0]
+;   ld1r {v1.16b}, [x1]
+;   ret
 
 function %f7(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -73,11 +111,19 @@ block0(v0: i64, v1: i64):
   return v4, v5
 }
 
+; VCode:
 ; block0:
 ;   ldrb w5, [x0]
 ;   ld1r { v0.16b }, [x1]
 ;   dup v1.16b, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldrb w5, [x0]
+;   ld1r {v0.16b}, [x1]
+;   dup v1.16b, w5
+;   ret
 
 function %f8(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -87,11 +133,19 @@ block0(v0: i64, v1: i64):
   return v3, v4
 }
 
+; VCode:
 ; block0:
 ;   ldrb w5, [x0]
 ;   dup v0.16b, w5
 ;   dup v1.16b, w5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldrb w5, [x0]
+;   dup v0.16b, w5
+;   dup v1.16b, w5
+;   ret
 
 function %f9() -> i32x2 {
 block0:
@@ -100,10 +154,17 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   movi v1.2d, #18374687579166474495
 ;   fmov d0, d1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v1.2d, #0xff0000ffff0000ff
+;   fmov d0, d1
+;   ret
 
 function %f10() -> i32x4 {
 block0:
@@ -112,9 +173,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mvni v0.4s, #15, MSL #16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvni v0.4s, #0xf, msl #16
+;   ret
 
 function %f11() -> f32x4 {
 block0:
@@ -123,7 +190,13 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov v0.4s, #1.3125
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov v0.4s, #1.31250000
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif b/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif
index 3ddef146b9..6da64c99a3 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif
@@ -9,11 +9,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   movz x1, #1
 ;   movk x1, x1, #1, LSL #48
 ;   fmov d0, x1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x1, #1
+;   movk x1, #1, lsl #48
+;   fmov d0, x1
+;   ret
 
 function %f2() -> i32x4 {
 block0:
@@ -22,10 +30,17 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   movz w0, #42679
 ;   fmov s0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, #0xa6b7
+;   fmov s0, w0
+;   ret
 
 function %f3() -> f32x4 {
 block0:
@@ -34,10 +49,17 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov s0, #1
 ;   fmov s0, s0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov s0, #1.00000000
+;   fmov s0, s0
+;   ret
 
 function %f4() -> f64x2 {
 block0:
@@ -46,8 +68,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmov d0, #1
 ;   fmov d0, d0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmov d0, #1.00000000
+;   fmov d0, d0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/stack-limit.clif b/cranelift/filetests/filetests/isa/aarch64/stack-limit.clif
index a0aeb0b281..beb04d9c08 100644
--- a/cranelift/filetests/filetests/isa/aarch64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/stack-limit.clif
@@ -7,16 +7,26 @@ block0:
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_leaf_zero(i64 stack_limit) {
 block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_gv_leaf_zero(i64 vmctx) {
     gv0 = vmctx
@@ -27,8 +37,13 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_call_zero(i64 stack_limit) {
     fn0 = %foo()
@@ -37,6 +52,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   subs xzr, sp, x0, UXTX
@@ -46,6 +62,21 @@ block0(v0: i64):
 ;   blr x2
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   cmp sp, x0
+;   b.hs #0x14
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+; block0: ; offset 0x14
+;   ldr x2, #0x1c
+;   b #0x24
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x2
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_limit_gv_call_zero(i64 vmctx) {
     gv0 = vmctx
@@ -58,6 +89,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   ldr x16, [x0]
@@ -69,6 +101,23 @@ block0(v0: i64):
 ;   blr x2
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   ldur x16, [x0]
+;   ldur x16, [x16, #4]
+;   cmp sp, x16
+;   b.hs #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+; block0: ; offset 0x1c
+;   ldr x2, #0x24
+;   b #0x2c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   blr x2
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 168
@@ -76,6 +125,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   add x16, x0, #176
@@ -86,6 +136,19 @@ block0(v0: i64):
 ;   add sp, sp, #176
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   add x16, x0, #0xb0
+;   cmp sp, x16
+;   b.hs #0x18
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   sub sp, sp, #0xb0
+; block0: ; offset 0x1c
+;   add sp, sp, #0xb0
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %huge_stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 400000
@@ -93,6 +156,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   subs xzr, sp, x0, UXTX
@@ -111,6 +175,28 @@ block0(v0: i64):
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   cmp sp, x0
+;   b.hs #0x14
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   mov w17, #0x1a80
+;   movk w17, #6, lsl #16
+;   add x16, x0, x17, uxtx
+;   cmp sp, x16
+;   b.hs #0x2c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   mov w16, #0x1a80
+;   movk w16, #6, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x38
+;   mov w16, #0x1a80
+;   movk w16, #6, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %limit_preamble(i64 vmctx) {
     gv0 = vmctx
@@ -122,6 +208,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   ldr x16, [x0]
@@ -134,6 +221,21 @@ block0(v0: i64):
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   ldur x16, [x0]
+;   ldur x16, [x16, #4]
+;   add x16, x16, #0x20
+;   cmp sp, x16
+;   b.hs #0x20
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   sub sp, sp, #0x20
+; block0: ; offset 0x24
+;   add sp, sp, #0x20
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %limit_preamble_huge(i64 vmctx) {
     gv0 = vmctx
@@ -145,6 +247,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   ldr x16, [x0]
@@ -165,6 +268,30 @@ block0(v0: i64):
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   ldur x16, [x0]
+;   ldur x16, [x16, #4]
+;   cmp sp, x16
+;   b.hs #0x1c
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   mov w17, #0x1a80
+;   movk w17, #6, lsl #16
+;   add x16, x16, x17, uxtx
+;   cmp sp, x16
+;   b.hs #0x34
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   mov w16, #0x1a80
+;   movk w16, #6, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x40
+;   mov w16, #0x1a80
+;   movk w16, #6, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %limit_preamble_huge_offset(i64 vmctx) {
     gv0 = vmctx
@@ -175,6 +302,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #6784 ; movk w16, w16, #6, LSL #16 ; ldr x16, [x0, x16, SXTX]
@@ -186,4 +314,20 @@ block0(v0: i64):
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x1a80
+;   movk w16, #6, lsl #16
+;   ldr x16, [x0, x16, sxtx]
+;   add x16, x16, #0x20
+;   cmp sp, x16
+;   b.hs #0x24
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: stk_ovf
+;   sub sp, sp, #0x20
+; block0: ; offset 0x28
+;   add sp, sp, #0x20
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/stack.clif b/cranelift/filetests/filetests/isa/aarch64/stack.clif
index e69532a143..aceed5e669 100644
--- a/cranelift/filetests/filetests/isa/aarch64/stack.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/stack.clif
@@ -10,6 +10,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -18,6 +19,16 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x0, sp
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_addr_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -28,6 +39,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #34480
@@ -40,6 +52,20 @@ block0:
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x14
+;   mov x0, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_load_small() -> i64 {
 ss0 = explicit_slot 8
@@ -49,6 +75,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -58,6 +85,17 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x1, sp
+;   ldr x0, [x1]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_load_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -68,6 +106,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #34480
@@ -81,6 +120,21 @@ block0:
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x14
+;   mov x1, sp
+;   ldr x0, [x1]
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_store_small(i64) {
 ss0 = explicit_slot 8
@@ -90,6 +144,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -99,6 +154,17 @@ block0(v0: i64):
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x2, sp
+;   str x0, [x2]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %stack_store_big(i64) {
 ss0 = explicit_slot 100000
@@ -109,6 +175,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #34480
@@ -122,6 +189,21 @@ block0(v0: i64):
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x14
+;   mov x2, sp
+;   str x0, [x2]
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i8_spill_slot(i8) -> i8, i64 {
     ss0 = explicit_slot 1000
@@ -274,6 +356,7 @@ block0(v0: i8):
   return v0, v137
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   stp x27, x28, [sp, #-16]!
@@ -429,6 +512,163 @@ block0(v0: i8):
 ;   ldp x27, x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   stp x27, x28, [sp, #-0x10]!
+;   stp x25, x26, [sp, #-0x10]!
+;   stp x23, x24, [sp, #-0x10]!
+;   stp x21, x22, [sp, #-0x10]!
+;   stp x19, x20, [sp, #-0x10]!
+;   sub sp, sp, #0x480
+; block0: ; offset 0x20
+;   str x0, [sp, #0x3e8]
+;   mov x6, #2
+;   add x9, x6, #1
+;   str x9, [sp, #0x470]
+;   mov x6, #4
+;   add x10, x6, #3
+;   str x10, [sp, #0x468]
+;   mov x6, #6
+;   add x11, x6, #5
+;   str x11, [sp, #0x460]
+;   mov x6, #8
+;   add x12, x6, #7
+;   str x12, [sp, #0x458]
+;   mov x6, #0xa
+;   add x13, x6, #9
+;   str x13, [sp, #0x450]
+;   mov x6, #0xc
+;   add x14, x6, #0xb
+;   str x14, [sp, #0x448]
+;   mov x6, #0xe
+;   add x15, x6, #0xd
+;   str x15, [sp, #0x440]
+;   mov x6, #0x10
+;   add x1, x6, #0xf
+;   str x1, [sp, #0x438]
+;   mov x6, #0x12
+;   add x2, x6, #0x11
+;   str x2, [sp, #0x430]
+;   mov x6, #0x14
+;   add x3, x6, #0x13
+;   str x3, [sp, #0x428]
+;   mov x6, #0x16
+;   add x4, x6, #0x15
+;   str x4, [sp, #0x420]
+;   mov x6, #0x18
+;   add x5, x6, #0x17
+;   str x5, [sp, #0x418]
+;   mov x6, #0x1a
+;   add x6, x6, #0x19
+;   str x6, [sp, #0x410]
+;   mov x6, #0x1c
+;   add x7, x6, #0x1b
+;   str x7, [sp, #0x408]
+;   mov x6, #0x1e
+;   add x24, x6, #0x1d
+;   str x24, [sp, #0x400]
+;   mov x6, #0x20
+;   add x25, x6, #0x1f
+;   str x25, [sp, #0x3f8]
+;   mov x6, #0x22
+;   add x26, x6, #0x21
+;   mov x6, #0x24
+;   add x27, x6, #0x23
+;   str x27, [sp, #0x3f0]
+;   mov x6, #0x26
+;   add x27, x6, #0x25
+;   mov x6, #0x1e
+;   add x28, x6, #0x27
+;   mov x6, #0x20
+;   add x21, x6, #0x1f
+;   mov x6, #0x22
+;   add x19, x6, #0x21
+;   mov x6, #0x24
+;   add x20, x6, #0x23
+;   mov x6, #0x26
+;   add x22, x6, #0x25
+;   mov x6, #0x1e
+;   add x23, x6, #0x27
+;   mov x6, #0x20
+;   add x0, x6, #0x1f
+;   mov x6, #0x22
+;   add x8, x6, #0x21
+;   mov x6, #0x24
+;   add x9, x6, #0x23
+;   mov x6, #0x26
+;   add x10, x6, #0x25
+;   mov x6, #0x1e
+;   add x11, x6, #0x27
+;   mov x6, #0x20
+;   add x12, x6, #0x1f
+;   mov x6, #0x22
+;   add x13, x6, #0x21
+;   mov x6, #0x24
+;   add x14, x6, #0x23
+;   mov x6, #0x26
+;   add x15, x6, #0x25
+;   ldr x1, [sp, #0x470]
+;   add x1, x1, #0x27
+;   ldr x3, [sp, #0x460]
+;   ldr x2, [sp, #0x468]
+;   add x2, x2, x3
+;   ldr x3, [sp, #0x450]
+;   ldr x6, [sp, #0x458]
+;   add x3, x6, x3
+;   ldr x4, [sp, #0x440]
+;   ldr x5, [sp, #0x448]
+;   add x4, x5, x4
+;   ldr x5, [sp, #0x430]
+;   ldr x6, [sp, #0x438]
+;   add x5, x6, x5
+;   ldr x7, [sp, #0x420]
+;   ldr x6, [sp, #0x428]
+;   add x6, x6, x7
+;   ldr x7, [sp, #0x410]
+;   ldr x24, [sp, #0x418]
+;   add x7, x24, x7
+;   ldr x24, [sp, #0x400]
+;   ldr x25, [sp, #0x408]
+;   add x24, x25, x24
+;   ldr x25, [sp, #0x3f8]
+;   add x25, x25, x26
+;   ldr x26, [sp, #0x3f0]
+;   add x26, x26, x27
+;   add x27, x28, x21
+;   add x28, x19, x20
+;   add x23, x22, x23
+;   add x8, x0, x8
+;   add x9, x9, x10
+;   add x10, x11, x12
+;   add x11, x13, x14
+;   add x12, x15, x1
+;   add x13, x2, x3
+;   add x14, x4, x5
+;   add x7, x6, x7
+;   add x15, x24, x25
+;   add x0, x26, x27
+;   add x1, x28, x23
+;   add x8, x8, x9
+;   add x9, x10, x11
+;   add x10, x12, x13
+;   add x7, x14, x7
+;   add x11, x15, x0
+;   add x8, x1, x8
+;   add x9, x9, x10
+;   add x7, x7, x11
+;   add x8, x8, x9
+;   add x1, x7, x8
+;   ldr x0, [sp, #0x3e8]
+;   add sp, sp, #0x480
+;   ldp x19, x20, [sp], #0x10
+;   ldp x21, x22, [sp], #0x10
+;   ldp x23, x24, [sp], #0x10
+;   ldp x25, x26, [sp], #0x10
+;   ldp x27, x28, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_store(i128) {
 ss0 = explicit_slot 16
@@ -438,6 +678,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -447,6 +688,17 @@ block0(v0: i128):
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x3, sp
+;   stp x0, x1, [x3]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_store_inst_offset(i128) {
 ss0 = explicit_slot 16
@@ -457,6 +709,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #32
@@ -466,6 +719,17 @@ block0(v0: i128):
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x20
+; block0: ; offset 0xc
+;   add x3, sp, #0x20
+;   stp x0, x1, [x3]
+;   add sp, sp, #0x20
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_store_big(i128) {
 ss0 = explicit_slot 100000
@@ -476,6 +740,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #34480
@@ -489,6 +754,21 @@ block0(v0: i128):
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x14
+;   mov x3, sp
+;   stp x0, x1, [x3]
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_load() -> i128 {
 ss0 = explicit_slot 16
@@ -498,6 +778,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #16
@@ -507,6 +788,17 @@ block0:
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x10
+; block0: ; offset 0xc
+;   mov x2, sp
+;   ldp x0, x1, [x2]
+;   add sp, sp, #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_load_inst_offset() -> i128 {
 ss0 = explicit_slot 16
@@ -517,6 +809,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   sub sp, sp, #32
@@ -526,6 +819,17 @@ block0:
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   sub sp, sp, #0x20
+; block0: ; offset 0xc
+;   add x2, sp, #0x20
+;   ldp x0, x1, [x2]
+;   add sp, sp, #0x20
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
 function %i128_stack_load_big() -> i128 {
 ss0 = explicit_slot 100000
@@ -536,6 +840,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   movz w16, #34480
@@ -549,4 +854,19 @@ block0:
 ;   add sp, sp, x16, UXTX
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   sub sp, sp, x16
+; block0: ; offset 0x14
+;   mov x2, sp
+;   ldp x0, x1, [x2]
+;   mov w16, #0x86b0
+;   movk w16, #1, lsl #16
+;   add sp, sp, x16
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/symbol-value-pic.clif b/cranelift/filetests/filetests/isa/aarch64/symbol-value-pic.clif
index 83b62c3405..39f141c8a5 100644
--- a/cranelift/filetests/filetests/isa/aarch64/symbol-value-pic.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/symbol-value-pic.clif
@@ -11,7 +11,14 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   load_ext_name x0, TestCase(%my_global)+0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adrp x0, #0 ; reloc_external Aarch64AdrGotPage21 %my_global 0
+;   ldr x0, [x0] ; reloc_external Aarch64AdrGotLo12Nc %my_global 0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/symbol-value.clif b/cranelift/filetests/filetests/isa/aarch64/symbol-value.clif
index 0ecc2c6052..4d2ad2a3ed 100644
--- a/cranelift/filetests/filetests/isa/aarch64/symbol-value.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/symbol-value.clif
@@ -10,7 +10,16 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   load_ext_name x0, TestCase(%my_global)+0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr x0, #8
+;   b #0x10
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %my_global 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif b/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif
index db46c96b30..cc7fcd1ebb 100644
--- a/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif
@@ -10,6 +10,7 @@ block0(v0: i32):
     return v0, v1
 }
 
+; VCode:
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x24, [sp, #-16]!
@@ -29,4 +30,28 @@ block0(v0: i32):
 ;   ldr x24, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+; 
+; Disassembled:
+;   stp x29, x30, [sp, #-0x10]!
+;   mov x29, sp
+;   str x24, [sp, #-0x10]!
+;   stp d14, d15, [sp, #-0x10]!
+;   stp d12, d13, [sp, #-0x10]!
+;   stp d10, d11, [sp, #-0x10]!
+;   stp d8, d9, [sp, #-0x10]!
+; block0: ; offset 0x1c
+;   mov x24, x0
+;   adrp x0, #0 ; reloc_external Aarch64TlsGdAdrPage21 u1:0 0
+;   add x0, x0, #0 ; reloc_external Aarch64TlsGdAddLo12Nc u1:0 0
+;   bl #0x28 ; reloc_external Call %ElfTlsGetAddr 0
+;   nop
+;   mov x1, x0
+;   mov x0, x24
+;   ldp d8, d9, [sp], #0x10
+;   ldp d10, d11, [sp], #0x10
+;   ldp d12, d13, [sp], #0x10
+;   ldp d14, d15, [sp], #0x10
+;   ldr x24, [sp], #0x10
+;   ldp x29, x30, [sp], #0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/traps.clif b/cranelift/filetests/filetests/isa/aarch64/traps.clif
index c2a89b0f70..c68d3ed01d 100644
--- a/cranelift/filetests/filetests/isa/aarch64/traps.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/traps.clif
@@ -6,8 +6,13 @@ block0:
   trap user0
 }
 
+; VCode:
 ; block0:
 ;   udf #0xc11f
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
 
 function %trap_iadd_ifcout(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -15,8 +20,16 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   adds x3, x0, x1
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adds x3, x0, x1
+;   b.lo #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif
index 10130dd18d..c6abb4054e 100644
--- a/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif
@@ -8,11 +8,20 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w2, #127
 ;   adds w0, w0, w2
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w2, #0x7f
+;   adds w0, w0, w2
+;   b.lo #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -21,11 +30,20 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz w2, #127
 ;   adds w0, w2, w0
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w2, #0x7f
+;   adds w0, w2, w0
+;   b.lo #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -33,10 +51,18 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   adds w0, w0, w1
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adds w0, w0, w1
+;   b.lo #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -45,11 +71,20 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #127
 ;   adds x0, x0, x2
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #0x7f
+;   adds x0, x0, x2
+;   b.lo #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -58,11 +93,20 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   movz x2, #127
 ;   adds x0, x2, x0
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, #0x7f
+;   adds x0, x2, x0
+;   b.lo #0x10
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -70,8 +114,16 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   adds x0, x0, x1
 ;   b.lo 8 ; udf
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adds x0, x0, x1
+;   b.lo #0xc
+;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/uextend-sextend.clif b/cranelift/filetests/filetests/isa/aarch64/uextend-sextend.clif
index a13f20c555..1fc6986272 100644
--- a/cranelift/filetests/filetests/isa/aarch64/uextend-sextend.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/uextend-sextend.clif
@@ -8,9 +8,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w0, w0
+;   ret
 
 function %f_u_8_32(i8) -> i32 {
 block0(v0: i8):
@@ -18,9 +24,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w0, w0
+;   ret
 
 function %f_u_8_16(i8) -> i16 {
 block0(v0: i8):
@@ -28,9 +40,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxtb w0, w0
+;   ret
 
 function %f_s_8_64(i8) -> i64 {
 block0(v0: i8):
@@ -38,9 +56,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb x0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb x0, w0
+;   ret
 
 function %f_s_8_32(i8) -> i32 {
 block0(v0: i8):
@@ -48,9 +72,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w0, w0
+;   ret
 
 function %f_s_8_16(i8) -> i16 {
 block0(v0: i8):
@@ -58,9 +88,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtb w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtb w0, w0
+;   ret
 
 function %f_u_16_64(i16) -> i64 {
 block0(v0: i16):
@@ -68,9 +104,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w0, w0
+;   ret
 
 function %f_u_16_32(i16) -> i32 {
 block0(v0: i16):
@@ -78,9 +120,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uxth w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   uxth w0, w0
+;   ret
 
 function %f_s_16_64(i16) -> i64 {
 block0(v0: i16):
@@ -88,9 +136,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth x0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth x0, w0
+;   ret
 
 function %f_s_16_32(i16) -> i32 {
 block0(v0: i16):
@@ -98,9 +152,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxth w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxth w0, w0
+;   ret
 
 function %f_u_32_64(i32) -> i64 {
 block0(v0: i32):
@@ -108,9 +168,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov w0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov w0, w0
+;   ret
 
 function %f_s_32_64(i32) -> i64 {
 block0(v0: i32):
@@ -118,7 +184,13 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sxtw x0, w0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sxtw x0, w0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif b/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif
index 970a31004c..e0034049af 100644
--- a/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif
@@ -7,6 +7,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sshr v2.16b, v0.16b, #7
 ;   movz x5, #513
@@ -20,6 +21,21 @@ block0(v0: i8x16):
 ;   addv h28, v26.8h
 ;   umov w0, v28.h[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sshr v2.16b, v0.16b, #7
+;   mov x5, #0x201
+;   movk x5, #0x804, lsl #16
+;   movk x5, #0x2010, lsl #32
+;   movk x5, #0x8040, lsl #48
+;   dup v16.2d, x5
+;   and v22.16b, v2.16b, v16.16b
+;   ext v24.16b, v22.16b, v22.16b, #8
+;   zip1 v26.16b, v22.16b, v24.16b
+;   addv h28, v26.8h
+;   umov w0, v28.h[0]
+;   ret
 
 function %f2(i8x16) -> i16 {
 block0(v0: i8x16):
@@ -27,6 +43,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sshr v2.16b, v0.16b, #7
 ;   movz x5, #513
@@ -40,6 +57,21 @@ block0(v0: i8x16):
 ;   addv h28, v26.8h
 ;   umov w0, v28.h[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sshr v2.16b, v0.16b, #7
+;   mov x5, #0x201
+;   movk x5, #0x804, lsl #16
+;   movk x5, #0x2010, lsl #32
+;   movk x5, #0x8040, lsl #48
+;   dup v16.2d, x5
+;   and v22.16b, v2.16b, v16.16b
+;   ext v24.16b, v22.16b, v22.16b, #8
+;   zip1 v26.16b, v22.16b, v24.16b
+;   addv h28, v26.8h
+;   umov w0, v28.h[0]
+;   ret
 
 function %f3(i16x8) -> i8 {
 block0(v0: i16x8):
@@ -47,6 +79,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sshr v2.8h, v0.8h, #15
 ;   ldr q4, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001
@@ -54,6 +87,20 @@ block0(v0: i16x8):
 ;   addv h16, v6.8h
 ;   umov w0, v16.h[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sshr v2.8h, v0.8h, #0xf
+;   ldr q4, #0xc
+;   b #0x1c
+;   .byte 0x01, 0x00, 0x02, 0x00
+;   .byte 0x04, 0x00, 0x08, 0x00
+;   .byte 0x10, 0x00, 0x20, 0x00
+;   .byte 0x40, 0x00, 0x80, 0x00
+;   and v6.16b, v2.16b, v4.16b
+;   addv h16, v6.8h
+;   umov w0, v16.h[0]
+;   ret
 
 function %f4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -61,6 +108,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sshr v2.4s, v0.4s, #31
 ;   ldr q4, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001
@@ -68,6 +116,20 @@ block0(v0: i32x4):
 ;   addv s16, v6.4s
 ;   mov w0, v16.s[0]
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sshr v2.4s, v0.4s, #0x1f
+;   ldr q4, #0xc
+;   b #0x1c
+;   .byte 0x01, 0x00, 0x00, 0x00
+;   .byte 0x02, 0x00, 0x00, 0x00
+;   .byte 0x04, 0x00, 0x00, 0x00
+;   .byte 0x08, 0x00, 0x00, 0x00
+;   and v6.16b, v2.16b, v4.16b
+;   addv s16, v6.4s
+;   mov w0, v16.s[0]
+;   ret
 
 function %f5(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -75,6 +137,7 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   mov x2, v0.d[1]
 ;   mov x4, v0.d[0]
@@ -82,4 +145,13 @@ block0(v0: i64x2):
 ;   lsr x8, x4, #63
 ;   add x0, x8, x6, LSL 1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mov x2, v0.d[1]
+;   mov x4, v0.d[0]
+;   lsr x6, x2, #0x3f
+;   lsr x8, x4, #0x3f
+;   add x0, x8, x6, lsl #1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/amodes.clif b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
index 8007ff3413..ea105b1e21 100644
--- a/cranelift/filetests/filetests/isa/riscv64/amodes.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
@@ -10,11 +10,20 @@ block0(v0: i64, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   sext.w a2,a1
 ;   add a2,a0,a2
 ;   lw a0,0(a2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a1, 0x20
+;   srai a2, a2, 0x20
+;   add a2, a0, a2
+;   lw a0, 0(a2)
+;   ret
 
 function %f6(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -24,11 +33,20 @@ block0(v0: i64, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   sext.w a2,a1
 ;   add a2,a2,a0
 ;   lw a0,0(a2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a1, 0x20
+;   srai a2, a2, 0x20
+;   add a2, a2, a0
+;   lw a0, 0(a2)
+;   ret
 
 function %f7(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -39,12 +57,23 @@ block0(v0: i32, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   uext.w a3,a0
 ;   uext.w a4,a1
 ;   add a3,a3,a4
 ;   lw a0,0(a3)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a3, a0, 0x20
+;   srli a3, a3, 0x20
+;   slli a4, a1, 0x20
+;   srli a4, a4, 0x20
+;   add a3, a3, a4
+;   lw a0, 0(a3)
+;   ret
 
 function %f8(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -57,6 +86,7 @@ block0(v0: i64, v1: i32):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   sext.w a4,a1
 ;   addi a4,a4,32
@@ -64,6 +94,16 @@ block0(v0: i64, v1: i32):
 ;   add a4,a4,a4
 ;   lw a0,4(a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a4, a1, 0x20
+;   srai a4, a4, 0x20
+;   addi a4, a4, 0x20
+;   add a4, a4, a0
+;   add a4, a4, a4
+;   lw a0, 4(a4)
+;   ret
 
 function %f9(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -75,12 +115,21 @@ block0(v0: i64, v1: i64, v2: i64):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   add a4,a0,a1
 ;   add a4,a4,a2
 ;   addi a4,a4,48
 ;   lw a0,0(a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add a4, a0, a1
+;   add a4, a4, a2
+;   addi a4, a4, 0x30
+;   lw a0, 0(a4)
+;   ret
 
 function %f10(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -92,6 +141,7 @@ block0(v0: i64, v1: i64, v2: i64):
   return v7
 }
 
+; VCode:
 ; block0:
 ;   add a6,a0,a1
 ;   add a6,a6,a2
@@ -100,6 +150,16 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   add t3,a6,a5
 ;   lw a0,0(t3)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add a6, a0, a1
+;   add a6, a6, a2
+;   lui a5, 1
+;   addi a5, a5, 4
+;   add t3, a6, a5
+;   lw a0, 0(t3)
+;   ret
 
 function %f10() -> i32 {
 block0:
@@ -108,10 +168,17 @@ block0:
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t0,1234
 ;   lw a0,0(t0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t0, zero, 0x4d2
+;   lw a0, 0(t0)
+;   ret
 
 function %f11(i64) -> i32 {
 block0(v0: i64):
@@ -121,11 +188,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lui a1,2048
 ;   add a2,a0,a1
 ;   lw a0,0(a2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 0x800
+;   add a2, a0, a1
+;   lw a0, 0(a2)
+;   ret
 
 function %f12(i64) -> i32 {
 block0(v0: i64):
@@ -135,10 +210,17 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   addi a0,a0,-4
 ;   lw a0,0(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, a0, -4
+;   lw a0, 0(a0)
+;   ret
 
 function %f13(i64) -> i32 {
 block0(v0: i64):
@@ -148,12 +230,21 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lui a1,244141
 ;   addi a1,a1,2560
 ;   add a4,a0,a1
 ;   lw a0,0(a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 0x3b9ad
+;   addi a1, a1, -0x600
+;   add a4, a0, a1
+;   lw a0, 0(a4)
+;   ret
 
 function %f14(i32) -> i32 {
 block0(v0: i32):
@@ -162,10 +253,18 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.w a0,a0
 ;   lw a0,0(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   lw a0, 0(a0)
+;   ret
 
 function %f15(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -176,12 +275,23 @@ block0(v0: i32, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   sext.w a3,a0
 ;   sext.w a4,a1
 ;   add a3,a3,a4
 ;   lw a0,0(a3)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a3, a0, 0x20
+;   srai a3, a3, 0x20
+;   slli a4, a1, 0x20
+;   srai a4, a4, 0x20
+;   add a3, a3, a4
+;   lw a0, 0(a3)
+;   ret
 
 function %f18(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -191,12 +301,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   lui a3,1048575
 ;   addi a3,a3,4094
 ;   uext.w a6,a3
 ;   lh a0,0(a6)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a3, 0xfffff
+;   addi a3, a3, -2
+;   slli a6, a3, 0x20
+;   srli a6, a6, 0x20
+;   lh a0, 0(a6)
+;   ret
 
 function %f19(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -206,12 +326,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   lui a3,1
 ;   addi a3,a3,2
 ;   uext.w a6,a3
 ;   lh a0,0(a6)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a3, 1
+;   addi a3, a3, 2
+;   slli a6, a3, 0x20
+;   srli a6, a6, 0x20
+;   lh a0, 0(a6)
+;   ret
 
 function %f20(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -221,12 +351,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   lui a3,1048575
 ;   addi a3,a3,4094
 ;   sext.w a6,a3
 ;   lh a0,0(a6)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a3, 0xfffff
+;   addi a3, a3, -2
+;   slli a6, a3, 0x20
+;   srai a6, a6, 0x20
+;   lh a0, 0(a6)
+;   ret
 
 function %f21(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -236,12 +376,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   lui a3,1
 ;   addi a3,a3,2
 ;   sext.w a6,a3
 ;   lh a0,0(a6)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a3, 1
+;   addi a3, a3, 2
+;   slli a6, a3, 0x20
+;   srai a6, a6, 0x20
+;   lh a0, 0(a6)
+;   ret
 
 function %i128(i64) -> i128 {
 block0(v0: i64):
@@ -250,6 +400,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld t2,0(a0)
 ;   mv a2,t2
@@ -259,6 +410,17 @@ block0(v0: i64):
 ;   sd a1,8(a0)
 ;   mv a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld t2, 0(a0)
+;   ori a2, t2, 0
+;   ld a1, 8(a0)
+;   ori a3, a2, 0
+;   sd a3, 0(a0)
+;   sd a1, 8(a0)
+;   ori a0, a2, 0
+;   ret
 
 function %i128_imm_offset(i64) -> i128 {
 block0(v0: i64):
@@ -267,6 +429,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld t2,16(a0)
 ;   mv a2,t2
@@ -276,6 +439,17 @@ block0(v0: i64):
 ;   sd a1,24(a0)
 ;   mv a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld t2, 0x10(a0)
+;   ori a2, t2, 0
+;   ld a1, 0x18(a0)
+;   ori a3, a2, 0
+;   sd a3, 0x10(a0)
+;   sd a1, 0x18(a0)
+;   ori a0, a2, 0
+;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
 block0(v0: i64):
@@ -284,6 +458,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld t2,504(a0)
 ;   mv a2,t2
@@ -293,6 +468,17 @@ block0(v0: i64):
 ;   sd a1,512(a0)
 ;   mv a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld t2, 0x1f8(a0)
+;   ori a2, t2, 0
+;   ld a1, 0x200(a0)
+;   ori a3, a2, 0
+;   sd a3, 0x1f8(a0)
+;   sd a1, 0x200(a0)
+;   ori a0, a2, 0
+;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
 block0(v0: i64):
@@ -301,6 +487,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld t2,-512(a0)
 ;   mv a2,t2
@@ -310,6 +497,17 @@ block0(v0: i64):
 ;   sd a1,-504(a0)
 ;   mv a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld t2, -0x200(a0)
+;   ori a2, t2, 0
+;   ld a1, -0x1f8(a0)
+;   ori a3, a2, 0
+;   sd a3, -0x200(a0)
+;   sd a1, -0x1f8(a0)
+;   ori a0, a2, 0
+;   ret
 
 function %i128_add_offset(i64) -> i128 {
 block0(v0: i64):
@@ -319,6 +517,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   addi a2,a0,32
 ;   ld a0,0(a2)
@@ -326,6 +525,15 @@ block0(v0: i64):
 ;   sd a0,0(a2)
 ;   sd a1,8(a2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a2, a0, 0x20
+;   ld a0, 0(a2)
+;   ld a1, 8(a2)
+;   sd a0, 0(a2)
+;   sd a1, 8(a2)
+;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
 block0(v0: i32):
@@ -335,6 +543,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.w a2,a0
 ;   ld a0,0(a2)
@@ -342,6 +551,16 @@ block0(v0: i32):
 ;   sd a0,0(a2)
 ;   sd a1,8(a2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a0, 0x20
+;   srai a2, a2, 0x20
+;   ld a0, 0(a2)
+;   ld a1, 8(a2)
+;   sd a0, 0(a2)
+;   sd a1, 8(a2)
+;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
 block0(v0: i64, v1: i32):
@@ -353,6 +572,7 @@ block0(v0: i64, v1: i32):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   sext.w a4,a1
 ;   add a4,a0,a4
@@ -362,4 +582,16 @@ block0(v0: i64, v1: i32):
 ;   sd a0,0(a4)
 ;   sd a1,8(a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a4, a1, 0x20
+;   srai a4, a4, 0x20
+;   add a4, a0, a4
+;   addi a4, a4, 0x18
+;   ld a0, 0(a4)
+;   ld a1, 8(a4)
+;   sd a0, 0(a4)
+;   sd a1, 8(a4)
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
index 0fca02ced9..0711c9f61b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
@@ -8,9 +8,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   add a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add a0, a0, a1
+;   ret
 
 function %f2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -18,9 +24,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sub a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub a0, a0, a1
+;   ret
 
 function %f3(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -28,9 +40,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mul a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul a0, a0, a1
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -38,9 +56,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mulhu a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mulhu a0, a0, a1
+;   ret
 
 function %f5(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -48,9 +72,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mulh a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mulh a0, a0, a1
+;   ret
 
 function %f6(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -58,6 +88,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li a2,-1
 ;   li a3,1
@@ -69,6 +100,27 @@ block0(v0: i64, v1: i64):
 ;   trap_ifc int_divz##(zero eq a1)
 ;   div a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a2, zero, -1
+;   addi a3, zero, 1
+;   slli a4, a3, 0x3f
+;   bne a2, a1, 0xc
+;   addi a6, zero, 1
+;   j 8
+;   mv a6, zero
+;   bne a4, a0, 0xc
+;   addi t3, zero, 1
+;   j 8
+;   mv t3, zero
+;   and t0, a6, t3
+;   beqz t0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   div a0, a0, a1
+;   ret
 
 function %f7(i64) -> i64 {
 block0(v0: i64):
@@ -77,6 +129,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,2
 ;   li a1,-1
@@ -91,6 +144,30 @@ block0(v0: i64):
 ;   li a4,2
 ;   div a0,a0,a4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 2
+;   addi a1, zero, -1
+;   addi a3, zero, 1
+;   slli a5, a3, 0x3f
+;   bne a1, t2, 0xc
+;   addi a7, zero, 1
+;   j 8
+;   mv a7, zero
+;   bne a5, a0, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   and t1, a7, t4
+;   beqz t1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   addi a1, zero, 2
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   addi a4, zero, 2
+;   div a0, a0, a4
+;   ret
 
 function %f8(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -98,10 +175,18 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   trap_ifc int_divz##(zero eq a1)
 ;   divu a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   divu a0, a0, a1
+;   ret
 
 function %f9(i64) -> i64 {
 block0(v0: i64):
@@ -110,12 +195,22 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,2
 ;   trap_ifc int_divz##(zero eq t2)
 ;   li a2,2
 ;   divu a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 2
+;   bne zero, t2, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   addi a2, zero, 2
+;   divu a0, a0, a2
+;   ret
 
 function %f10(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -123,10 +218,18 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   trap_ifc int_divz##(zero eq a1)
 ;   rem a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   rem a0, a0, a1
+;   ret
 
 function %f11(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -134,10 +237,18 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   trap_ifc int_divz##(zero eq a1)
 ;   remu a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   remu a0, a0, a1
+;   ret
 
 function %f12(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -145,6 +256,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.w a0,a0
 ;   sext.w a2,a1
@@ -159,6 +271,32 @@ block0(v0: i32, v1: i32):
 ;   trap_ifc int_divz##(zero eq a2)
 ;   divw a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   slli a2, a1, 0x20
+;   srai a2, a2, 0x20
+;   addi a4, zero, -1
+;   addi a6, zero, 1
+;   slli t3, a6, 0x3f
+;   slli t0, a0, 0x20
+;   bne a4, a2, 0xc
+;   addi t2, zero, 1
+;   j 8
+;   mv t2, zero
+;   bne t3, t0, 0xc
+;   addi a1, zero, 1
+;   j 8
+;   mv a1, zero
+;   and a3, t2, a1
+;   beqz a3, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   bne zero, a2, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   divw a0, a0, a2
+;   ret
 
 function %f13(i32) -> i32 {
 block0(v0: i32):
@@ -167,6 +305,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.w t2,a0
 ;   li a1,2
@@ -182,6 +321,33 @@ block0(v0: i32):
 ;   trap_ifc int_divz##(zero eq a3)
 ;   divw a0,t2,a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srai t2, t2, 0x20
+;   addi a1, zero, 2
+;   slli a3, a1, 0x20
+;   srai a3, a3, 0x20
+;   addi a5, zero, -1
+;   addi a7, zero, 1
+;   slli t4, a7, 0x3f
+;   slli t1, t2, 0x20
+;   bne a5, a3, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   bne t4, t1, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+;   and a4, a0, a2
+;   beqz a4, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   bne zero, a3, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   divw a0, t2, a3
+;   ret
 
 function %f14(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -189,6 +355,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a5,a0
 ;   uext.w a0,a1
@@ -196,6 +363,18 @@ block0(v0: i32, v1: i32):
 ;   uext.w a3,a5
 ;   divuw a0,a3,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a5, a0, 0
+;   slli a0, a1, 0x20
+;   srli a0, a0, 0x20
+;   bne zero, a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   slli a3, a5, 0x20
+;   srli a3, a3, 0x20
+;   divuw a0, a3, a0
+;   ret
 
 function %f15(i32) -> i32 {
 block0(v0: i32):
@@ -204,6 +383,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,2
 ;   uext.w a1,t2
@@ -211,6 +391,18 @@ block0(v0: i32):
 ;   uext.w a4,a0
 ;   divuw a0,a4,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 2
+;   slli a1, t2, 0x20
+;   srli a1, a1, 0x20
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   slli a4, a0, 0x20
+;   srli a4, a4, 0x20
+;   divuw a0, a4, a1
+;   ret
 
 function %f16(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -218,11 +410,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.w a1,a1
 ;   trap_ifc int_divz##(zero eq a1)
 ;   remw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 0x20
+;   srai a1, a1, 0x20
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   remw a0, a0, a1
+;   ret
 
 function %f17(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -230,11 +432,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.w a1,a1
 ;   trap_ifc int_divz##(zero eq a1)
 ;   remuw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 0x20
+;   srli a1, a1, 0x20
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   remuw a0, a0, a1
+;   ret
 
 function %f18(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -242,9 +454,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and a0, a0, a1
+;   ret
 
 function %f19(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -252,9 +470,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   ret
 
 function %f20(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -262,9 +486,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a1
+;   ret
 
 function %f21(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -272,10 +502,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   and a0, a0, a1
+;   ret
 
 function %f22(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -283,10 +520,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   or a0, a0, a1
+;   ret
 
 function %f23(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -294,10 +538,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   xor a0, a0, a1
+;   ret
 
 function %f24(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -305,9 +556,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   not a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a0, a0
+;   ret
 
 function %f25(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -317,10 +574,17 @@ block0(v0: i32, v1: i32):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   slliw a2,a0,53
 ;   subw a0,a1,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slliw a2, a0, 0x15
+;   subw a0, a1, a2
+;   ret
 
 function %f26(i32) -> i32 {
 block0(v0: i32):
@@ -329,9 +593,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   addiw a0,a0,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addiw a0, a0, -1
+;   ret
 
 function %f27(i32) -> i32 {
 block0(v0: i32):
@@ -340,10 +610,17 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,-1
 ;   subw a0,a0,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, -1
+;   subw a0, a0, t2
+;   ret
 
 function %f28(i64) -> i64 {
 block0(v0: i64):
@@ -352,10 +629,17 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,-1
 ;   sub a0,a0,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, -1
+;   sub a0, a0, t2
+;   ret
 
 function %f29(i64) -> i64 {
 block0(v0: i64):
@@ -364,10 +648,17 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,1
 ;   sub a0,zero,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 1
+;   neg a0, t2
+;   ret
 
 function %add_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -375,12 +666,21 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   add a0,a0,a2
 ;   sltu a4,a0,a2
 ;   add a6,a1,a3
 ;   add a1,a6,a4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add a0, a0, a2
+;   sltu a4, a0, a2
+;   add a6, a1, a3
+;   add a1, a6, a4
+;   ret
 
 function %sub_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -388,6 +688,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   sub a2,a0,a2
 ;   mv a7,a2
@@ -396,6 +697,16 @@ block0(v0: i128, v1: i128):
 ;   sub a6,a1,a3
 ;   sub a1,a6,a4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sub a2, a0, a2
+;   ori a7, a2, 0
+;   sltu a4, a0, a7
+;   ori a0, a7, 0
+;   sub a6, a1, a3
+;   sub a1, a6, a4
+;   ret
 
 function %add_mul_2(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -404,10 +715,17 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   mulw a2,a1,a2
 ;   addw a0,a2,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mulw a2, a1, a2
+;   addw a0, a2, a0
+;   ret
 
 function %msub_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -416,10 +734,17 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   mulw a2,a1,a2
 ;   subw a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mulw a2, a1, a2
+;   subw a0, a0, a2
+;   ret
 
 function %msub_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -428,10 +753,17 @@ block0(v0: i64, v1: i64, v2: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   mul a2,a1,a2
 ;   sub a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul a2, a1, a2
+;   sub a0, a0, a2
+;   ret
 
 function %imul_sub_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -440,10 +772,17 @@ block0(v0: i32, v1: i32, v2: i32):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   mulw a2,a1,a2
 ;   subw a0,a2,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mulw a2, a1, a2
+;   subw a0, a2, a0
+;   ret
 
 function %imul_sub_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -452,10 +791,17 @@ block0(v0: i64, v1: i64, v2: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   mul a2,a1,a2
 ;   sub a0,a2,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mul a2, a1, a2
+;   sub a0, a2, a0
+;   ret
 
 function %srem_const (i64) -> i64 {
 block0(v0: i64):
@@ -464,12 +810,22 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,2
 ;   trap_ifc int_divz##(zero eq t2)
 ;   li a2,2
 ;   rem a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 2
+;   bne zero, t2, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   addi a2, zero, 2
+;   rem a0, a0, a2
+;   ret
 
 function %urem_const (i64) -> i64 {
 block0(v0: i64):
@@ -478,12 +834,22 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,2
 ;   trap_ifc int_divz##(zero eq t2)
 ;   li a2,2
 ;   remu a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 2
+;   bne zero, t2, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   addi a2, zero, 2
+;   remu a0, a0, a2
+;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
 block0(v0: i64):
@@ -492,6 +858,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,-1
 ;   li a1,-1
@@ -506,4 +873,28 @@ block0(v0: i64):
 ;   li a4,-1
 ;   div a0,a0,a4
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, -1
+;   addi a1, zero, -1
+;   addi a3, zero, 1
+;   slli a5, a3, 0x3f
+;   bne a1, t2, 0xc
+;   addi a7, zero, 1
+;   j 8
+;   mv a7, zero
+;   bne a5, a0, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   and t1, a7, t4
+;   beqz t1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   addi a1, zero, -1
+;   bne zero, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
+;   addi a4, zero, -1
+;   div a0, a0, a4
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif b/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif
index 8d68abfbc4..271f99902e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif
@@ -8,9 +8,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoadd.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoadd.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_add_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -18,9 +24,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoadd.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoadd.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_sub_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -28,10 +40,17 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub a1,zero,a1
 ;   amoadd.d.aqrl a2,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg a1, a1
+;   amoadd.d.aqrl a2, a1, (a0)
+;   ret
 
 function %atomic_rmw_sub_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -39,10 +58,17 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   sub a1,zero,a1
 ;   amoadd.w.aqrl a2,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg a1, a1
+;   amoadd.w.aqrl a2, a1, (a0)
+;   ret
 
 function %atomic_rmw_and_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -50,9 +76,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoand.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoand.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_and_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -60,9 +92,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoand.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoand.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_nand_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -70,11 +108,23 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   mv a3,a0
 ;   mv a2,a1
 ;   atomic_rmw.i64 nand a0,a2,(a3)##t0=a1 offset=zero
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a3, a0, 0
+;   ori a2, a1, 0
+;   lr.d.aqrl a0, (a3)
+;   and a1, a2, a0
+;   not a1, a1
+;   sc.d.aqrl a1, a1, (a3)
+;   bnez a1, -0x10
+;   ret
 
 function %atomic_rmw_nand_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -82,11 +132,23 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   mv a3,a0
 ;   mv a2,a1
 ;   atomic_rmw.i32 nand a0,a2,(a3)##t0=a1 offset=zero
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a3, a0, 0
+;   ori a2, a1, 0
+;   lr.w.aqrl a0, (a3)
+;   and a1, a2, a0
+;   not a1, a1
+;   sc.w.aqrl a1, a1, (a3)
+;   bnez a1, -0x10
+;   ret
 
 function %atomic_rmw_or_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -94,9 +156,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoor.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoor.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_or_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -104,9 +172,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoor.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoor.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_xor_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -114,9 +188,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoxor.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoxor.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_xor_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -124,9 +204,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amoxor.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amoxor.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_smax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -134,9 +220,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomax.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomax.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_smax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -144,9 +236,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomax.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomax.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_umax_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -154,9 +252,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomaxu.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomaxu.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_umax_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -164,9 +268,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomaxu.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomaxu.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_smin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -174,9 +284,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomin.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomin.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_smin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -184,9 +300,15 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amomin.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amomin.w.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_umin_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -194,9 +316,15 @@ block0(v0: i64, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   amominu.d.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amominu.d.aqrl a0, a1, (a0)
+;   ret
 
 function %atomic_rmw_umin_i32(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -204,7 +332,13 @@ block0(v0: i64, v1: i32):
     return
 }
 
+; VCode:
 ; block0:
 ;   amominu.w.aqrl a0,a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   amominu.w.aqrl a0, a1, (a0)
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif b/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif
index d242816c1c..d0aa087d6b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif
@@ -8,9 +8,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   atomic_load.i64 a0,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fence rw, rw
+;   ld a0, 0(a0)
+;   fence r, rw
+;   ret
 
 function %atomic_load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -18,9 +26,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   atomic_load.i32 a0,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fence rw, rw
+;   lw a0, 0(a0)
+;   fence r, rw
+;   ret
 
 function %atomic_load_i32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -29,8 +45,18 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   atomic_load.i32 a0,(a0)
 ;   uext.w a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fence rw, rw
+;   lw a0, 0(a0)
+;   fence r, rw
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/atomic_store.clif b/cranelift/filetests/filetests/isa/riscv64/atomic_store.clif
index 1b92fc288b..bcc9fe39e0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/atomic_store.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/atomic_store.clif
@@ -8,9 +8,16 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   atomic_store.i64 a0,(a1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fence rw, w
+;   sd a0, 0(a1)
+;   ret
 
 function %atomic_store_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -20,10 +27,22 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   load_sym t2,%sym+0
 ;   atomic_store.i64 a0,(t2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t2, 0
+;   ld t2, 0xc(t2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %sym 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   fence rw, w
+;   sd a0, 0(t2)
+;   ret
 
 function %atomic_store_imm_i64(i64) {
 block0(v0: i64):
@@ -32,11 +51,20 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lui a1,3
 ;   addi a1,a1,57
 ;   atomic_store.i64 a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 3
+;   addi a1, a1, 0x39
+;   fence rw, w
+;   sd a1, 0(a0)
+;   ret
 
 function %atomic_store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -44,9 +72,16 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   atomic_store.i32 a0,(a1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fence rw, w
+;   sw a0, 0(a1)
+;   ret
 
 function %atomic_store_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -56,10 +91,22 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   load_sym t2,%sym+0
 ;   atomic_store.i32 a0,(t2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t2, 0
+;   ld t2, 0xc(t2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %sym 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   fence rw, w
+;   sw a0, 0(t2)
+;   ret
 
 function %atomic_store_imm_i32(i64) {
 block0(v0: i64):
@@ -68,9 +115,18 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lui a1,3
 ;   addi a1,a1,57
 ;   atomic_store.i32 a1,(a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 3
+;   addi a1, a1, 0x39
+;   fence rw, w
+;   sw a1, 0(a0)
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/bitops-optimized.clif b/cranelift/filetests/filetests/isa/riscv64/bitops-optimized.clif
index 1f249ff3ed..75c3863fe7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/bitops-optimized.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/bitops-optimized.clif
@@ -8,9 +8,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   andn a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x33, 0x75, 0xb5, 0x40
+;   ret
 
 function %band_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -19,9 +25,15 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   andn a0,a1,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x33, 0xf5, 0xa5, 0x40
+;   ret
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -29,9 +41,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   orn a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x33, 0x65, 0xb5, 0x40
+;   ret
 
 function %bor_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -40,6 +58,13 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   orn a0,a1,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x33, 0xe5, 0xa5, 0x40
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/riscv64/bitops.clif b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
index 2857ad8a12..b6cc57a2ba 100644
--- a/cranelift/filetests/filetests/isa/riscv64/bitops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
@@ -8,10 +8,35 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a3,a0
 ;   brev8 a0,a3##tmp=t2 tmp2=a2 step=a1 ty=i8
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a3, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 8
+;   addi t2, zero, 1
+;   slli t2, t2, 7
+;   addi a2, zero, 1
+;   slli a2, a2, 0
+;   blez a1, 0x34
+;   and t5, t2, a3
+;   beq zero, t5, 8
+;   or a0, a0, a2
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   addi t5, zero, 8
+;   rem t5, a1, t5
+;   bnez t5, 0xc
+;   srli a2, a2, 0xf
+;   j -0x28
+;   slli a2, a2, 1
+;   j -0x30
+;   ret
 
 function %a(i16) -> i16 {
 block0(v0: i16):
@@ -19,12 +44,48 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a7,a0
 ;   brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i16
 ;   rev8 a4,a2##step=a6 tmp=a5
 ;   srli a0,a4,48
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a0, 0
+;   ori a2, zero, 0
+;   addi a1, zero, 0x10
+;   addi t2, zero, 1
+;   slli t2, t2, 0xf
+;   addi a0, zero, 1
+;   slli a0, a0, 8
+;   blez a1, 0x34
+;   and t5, t2, a7
+;   beq zero, t5, 8
+;   or a2, a2, a0
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   addi t5, zero, 8
+;   rem t5, a1, t5
+;   bnez t5, 0xc
+;   srli a0, a0, 0xf
+;   j -0x28
+;   slli a0, a0, 1
+;   j -0x30
+;   ori a4, zero, 0
+;   ori a5, a2, 0
+;   addi a6, zero, 0x38
+;   bltz a6, 0x1c
+;   andi t6, a5, 0xff
+;   sll t6, t6, a6
+;   or a4, a4, t6
+;   addi a6, a6, -8
+;   srli a5, a5, 8
+;   j -0x18
+;   srli a0, a4, 0x30
+;   ret
 
 function %a(i32) -> i32 {
 block0(v0: i32):
@@ -32,12 +93,48 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a7,a0
 ;   brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i32
 ;   rev8 a4,a2##step=a6 tmp=a5
 ;   srli a0,a4,32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a0, 0
+;   ori a2, zero, 0
+;   addi a1, zero, 0x20
+;   addi t2, zero, 1
+;   slli t2, t2, 0x1f
+;   addi a0, zero, 1
+;   slli a0, a0, 0x18
+;   blez a1, 0x34
+;   and t5, t2, a7
+;   beq zero, t5, 8
+;   or a2, a2, a0
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   addi t5, zero, 8
+;   rem t5, a1, t5
+;   bnez t5, 0xc
+;   srli a0, a0, 0xf
+;   j -0x28
+;   slli a0, a0, 1
+;   j -0x30
+;   ori a4, zero, 0
+;   ori a5, a2, 0
+;   addi a6, zero, 0x38
+;   bltz a6, 0x1c
+;   andi t6, a5, 0xff
+;   sll t6, t6, a6
+;   or a4, a4, t6
+;   addi a6, a6, -8
+;   srli a5, a5, 8
+;   j -0x18
+;   srli a0, a4, 0x20
+;   ret
 
 function %a(i64) -> i64 {
 block0(v0: i64):
@@ -45,11 +142,46 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a6,a0
 ;   rev8 t2,a6##step=a1 tmp=a0
 ;   brev8 a0,t2##tmp=a3 tmp2=a4 step=a5 ty=i64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a6, a0, 0
+;   ori t2, zero, 0
+;   ori a0, a6, 0
+;   addi a1, zero, 0x38
+;   bltz a1, 0x1c
+;   andi t6, a0, 0xff
+;   sll t6, t6, a1
+;   or t2, t2, t6
+;   addi a1, a1, -8
+;   srli a0, a0, 8
+;   j -0x18
+;   ori a0, zero, 0
+;   addi a5, zero, 0x40
+;   addi a3, zero, 1
+;   slli a3, a3, 0x3f
+;   addi a4, zero, 1
+;   slli a4, a4, 0x38
+;   blez a5, 0x34
+;   and t5, a3, t2
+;   beq zero, t5, 8
+;   or a0, a0, a4
+;   addi a5, a5, -1
+;   srli a3, a3, 1
+;   addi t5, zero, 8
+;   rem t5, a5, t5
+;   bnez t5, 0xc
+;   srli a4, a4, 0xf
+;   j -0x28
+;   slli a4, a4, 1
+;   j -0x30
+;   ret
 
 function %a(i128) -> i128 {
 block0(v0: i128):
@@ -57,6 +189,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a3,a0
 ;   mv a7,a1
@@ -66,6 +199,71 @@ block0(v0: i128):
 ;   rev8 t4,a3##step=t1 tmp=t0
 ;   brev8 a0,t4##tmp=a4 tmp2=a3 step=a2 ty=i64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a3, a0, 0
+;   ori a7, a1, 0
+;   ori a0, zero, 0
+;   ori a1, a3, 0
+;   addi a2, zero, 0x38
+;   bltz a2, 0x1c
+;   andi t6, a1, 0xff
+;   sll t6, t6, a2
+;   or a0, a0, t6
+;   addi a2, a2, -8
+;   srli a1, a1, 8
+;   j -0x18
+;   ori a1, zero, 0
+;   addi a6, zero, 0x40
+;   addi a4, zero, 1
+;   slli a4, a4, 0x3f
+;   addi a5, zero, 1
+;   slli a5, a5, 0x38
+;   blez a6, 0x34
+;   and t5, a4, a0
+;   beq zero, t5, 8
+;   or a1, a1, a5
+;   addi a6, a6, -1
+;   srli a4, a4, 1
+;   addi t5, zero, 8
+;   rem t5, a6, t5
+;   bnez t5, 0xc
+;   srli a5, a5, 0xf
+;   j -0x28
+;   slli a5, a5, 1
+;   j -0x30
+;   ori a3, a7, 0
+;   ori t4, zero, 0
+;   ori t0, a3, 0
+;   addi t1, zero, 0x38
+;   bltz t1, 0x1c
+;   andi t6, t0, 0xff
+;   sll t6, t6, t1
+;   or t4, t4, t6
+;   addi t1, t1, -8
+;   srli t0, t0, 8
+;   j -0x18
+;   ori a0, zero, 0
+;   addi a2, zero, 0x40
+;   addi a4, zero, 1
+;   slli a4, a4, 0x3f
+;   addi a3, zero, 1
+;   slli a3, a3, 0x38
+;   blez a2, 0x34
+;   and t5, a4, t4
+;   beq zero, t5, 8
+;   or a0, a0, a3
+;   addi a2, a2, -1
+;   srli a4, a4, 1
+;   addi t5, zero, 8
+;   rem t5, a2, t5
+;   bnez t5, 0xc
+;   srli a3, a3, 0xf
+;   j -0x28
+;   slli a3, a3, 1
+;   j -0x30
+;   ret
 
 function %b(i8) -> i8 {
 block0(v0: i8):
@@ -73,10 +271,27 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   clz a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 8
+;   addi t2, zero, 1
+;   slli t2, t2, 7
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %b(i16) -> i16 {
 block0(v0: i16):
@@ -84,10 +299,27 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   clz a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x10
+;   addi t2, zero, 1
+;   slli t2, t2, 0xf
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %b(i32) -> i32 {
 block0(v0: i32):
@@ -95,10 +327,27 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   clz a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x20
+;   addi t2, zero, 1
+;   slli t2, t2, 0x1f
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %b(i64) -> i64 {
 block0(v0: i64):
@@ -106,10 +355,27 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   clz a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x40
+;   addi t2, zero, 1
+;   slli t2, t2, 0x3f
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %b(i128) -> i128 {
 block0(v0: i128):
@@ -117,6 +383,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv t0,a1
 ;   clz a2,t0##ty=i64 tmp=a3 step=a1
@@ -126,6 +393,40 @@ block0(v0: i128):
 ;   add a0,a2,t0
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori t0, a1, 0
+;   ori a2, zero, 0
+;   addi a1, zero, 0x40
+;   addi a3, zero, 1
+;   slli a3, a3, 0x3f
+;   blez a1, 0x1c
+;   and t5, a3, t0
+;   bne zero, t5, 0x14
+;   addi a2, a2, 1
+;   addi a1, a1, -1
+;   srli a3, a3, 1
+;   j -0x18
+;   ori a6, zero, 0
+;   addi a5, zero, 0x40
+;   addi a4, zero, 1
+;   slli a4, a4, 0x3f
+;   blez a5, 0x1c
+;   and t5, a4, a0
+;   bne zero, t5, 0x14
+;   addi a6, a6, 1
+;   addi a5, a5, -1
+;   srli a4, a4, 1
+;   j -0x18
+;   addi t3, zero, 0x40
+;   beq t3, a2, 0xc
+;   ori t0, zero, 0
+;   j 8
+;   ori t0, a6, 0
+;   add a0, a2, t0
+;   mv a1, zero
+;   ret
 
 function %c(i8) -> i8 {
 block0(v0: i8):
@@ -133,6 +434,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b t2,a0
 ;   not a1,a0
@@ -140,6 +442,29 @@ block0(v0: i8):
 ;   clz a7,a3##ty=i8 tmp=a5 step=a6
 ;   addi a0,a7,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai t2, t2, 0x38
+;   not a1, a0
+;   bltz t2, 0xc
+;   ori a3, a0, 0
+;   j 8
+;   ori a3, a1, 0
+;   ori a7, zero, 0
+;   addi a6, zero, 8
+;   addi a5, zero, 1
+;   slli a5, a5, 7
+;   blez a6, 0x1c
+;   and t5, a5, a3
+;   bne zero, t5, 0x14
+;   addi a7, a7, 1
+;   addi a6, a6, -1
+;   srli a5, a5, 1
+;   j -0x18
+;   addi a0, a7, -1
+;   ret
 
 function %c(i16) -> i16 {
 block0(v0: i16):
@@ -147,6 +472,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h t2,a0
 ;   not a1,a0
@@ -154,6 +480,29 @@ block0(v0: i16):
 ;   clz a7,a3##ty=i16 tmp=a5 step=a6
 ;   addi a0,a7,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai t2, t2, 0x30
+;   not a1, a0
+;   bltz t2, 0xc
+;   ori a3, a0, 0
+;   j 8
+;   ori a3, a1, 0
+;   ori a7, zero, 0
+;   addi a6, zero, 0x10
+;   addi a5, zero, 1
+;   slli a5, a5, 0xf
+;   blez a6, 0x1c
+;   and t5, a5, a3
+;   bne zero, t5, 0x14
+;   addi a7, a7, 1
+;   addi a6, a6, -1
+;   srli a5, a5, 1
+;   j -0x18
+;   addi a0, a7, -1
+;   ret
 
 function %c(i32) -> i32 {
 block0(v0: i32):
@@ -161,6 +510,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.w t2,a0
 ;   not a1,a0
@@ -168,6 +518,29 @@ block0(v0: i32):
 ;   clz a7,a3##ty=i32 tmp=a5 step=a6
 ;   addi a0,a7,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srai t2, t2, 0x20
+;   not a1, a0
+;   bltz t2, 0xc
+;   ori a3, a0, 0
+;   j 8
+;   ori a3, a1, 0
+;   ori a7, zero, 0
+;   addi a6, zero, 0x20
+;   addi a5, zero, 1
+;   slli a5, a5, 0x1f
+;   blez a6, 0x1c
+;   and t5, a5, a3
+;   bne zero, t5, 0x14
+;   addi a7, a7, 1
+;   addi a6, a6, -1
+;   srli a5, a5, 1
+;   j -0x18
+;   addi a0, a7, -1
+;   ret
 
 function %c(i64) -> i64 {
 block0(v0: i64):
@@ -175,12 +548,34 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   not t2,a0
 ;   select_reg a1,t2,a0##condition=(a0 slt zero)
 ;   clz a5,a1##ty=i64 tmp=a3 step=a4
 ;   addi a0,a5,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not t2, a0
+;   bltz a0, 0xc
+;   ori a1, a0, 0
+;   j 8
+;   ori a1, t2, 0
+;   ori a5, zero, 0
+;   addi a4, zero, 0x40
+;   addi a3, zero, 1
+;   slli a3, a3, 0x3f
+;   blez a4, 0x1c
+;   and t5, a3, a1
+;   bne zero, t5, 0x14
+;   addi a5, a5, 1
+;   addi a4, a4, -1
+;   srli a3, a3, 1
+;   j -0x18
+;   addi a0, a5, -1
+;   ret
 
 function %c(i128) -> i128 {
 block0(v0: i128):
@@ -188,6 +583,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   not a2,a0
 ;   select_reg a2,a2,a0##condition=(a1 slt zero)
@@ -202,6 +598,49 @@ block0(v0: i128):
 ;   addi a0,a7,-1
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a2, a0
+;   bltz a1, 8
+;   ori a2, a0, 0
+;   not a4, a1
+;   bltz a1, 0xc
+;   ori a6, a1, 0
+;   j 8
+;   ori a6, a4, 0
+;   ori t0, zero, 0
+;   addi t4, zero, 0x40
+;   addi t3, zero, 1
+;   slli t3, t3, 0x3f
+;   blez t4, 0x1c
+;   and t5, t3, a6
+;   bne zero, t5, 0x14
+;   addi t0, t0, 1
+;   addi t4, t4, -1
+;   srli t3, t3, 1
+;   j -0x18
+;   ori a1, zero, 0
+;   addi a0, zero, 0x40
+;   addi t2, zero, 1
+;   slli t2, t2, 0x3f
+;   blez a0, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a1, a1, 1
+;   addi a0, a0, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   addi a3, zero, 0x40
+;   beq a3, t0, 0xc
+;   ori a5, zero, 0
+;   j 8
+;   ori a5, a1, 0
+;   add a7, t0, a5
+;   mv t4, zero
+;   addi a0, a7, -1
+;   mv a1, zero
+;   ret
 
 function %d(i8) -> i8 {
 block0(v0: i8):
@@ -209,10 +648,26 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   ctz a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 8
+;   addi t2, zero, 1
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   slli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i16) -> i16 {
 block0(v0: i16):
@@ -220,10 +675,26 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   ctz a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x10
+;   addi t2, zero, 1
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   slli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i32) -> i32 {
 block0(v0: i32):
@@ -231,10 +702,26 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   ctz a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x20
+;   addi t2, zero, 1
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   slli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i64) -> i64 {
 block0(v0: i64):
@@ -242,10 +729,26 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   ctz a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x40
+;   addi t2, zero, 1
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   bne zero, t5, 0x14
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   slli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i128) -> i128 {
 block0(v0: i128):
@@ -253,6 +756,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv t0,a0
 ;   ctz a2,t0##ty=i64 tmp=a0 step=a3
@@ -262,6 +766,38 @@ block0(v0: i128):
 ;   add a0,a2,t0
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori t0, a0, 0
+;   ori a2, zero, 0
+;   addi a3, zero, 0x40
+;   addi a0, zero, 1
+;   blez a3, 0x1c
+;   and t5, a0, t0
+;   bne zero, t5, 0x14
+;   addi a2, a2, 1
+;   addi a3, a3, -1
+;   slli a0, a0, 1
+;   j -0x18
+;   ori a6, zero, 0
+;   addi a5, zero, 0x40
+;   addi a4, zero, 1
+;   blez a5, 0x1c
+;   and t5, a4, a1
+;   bne zero, t5, 0x14
+;   addi a6, a6, 1
+;   addi a5, a5, -1
+;   slli a4, a4, 1
+;   j -0x18
+;   addi t3, zero, 0x40
+;   beq t3, a2, 0xc
+;   ori t0, zero, 0
+;   j 8
+;   ori t0, a6, 0
+;   add a0, a2, t0
+;   mv a1, zero
+;   ret
 
 function %d(i128) -> i128 {
 block0(v0: i128):
@@ -269,6 +805,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv t3,a0
 ;   popcnt a2,t3##ty=i64 tmp=a0 step=a3
@@ -276,6 +813,35 @@ block0(v0: i128):
 ;   add a0,a2,a6
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori t3, a0, 0
+;   ori a2, zero, 0
+;   addi a3, zero, 0x40
+;   addi a0, zero, 1
+;   slli a0, a0, 0x3f
+;   blez a3, 0x1c
+;   and t5, a0, t3
+;   beq zero, t5, 8
+;   addi a2, a2, 1
+;   addi a3, a3, -1
+;   srli a0, a0, 1
+;   j -0x18
+;   ori a6, zero, 0
+;   addi a5, zero, 0x40
+;   addi a4, zero, 1
+;   slli a4, a4, 0x3f
+;   blez a5, 0x1c
+;   and t5, a4, a1
+;   beq zero, t5, 8
+;   addi a6, a6, 1
+;   addi a5, a5, -1
+;   srli a4, a4, 1
+;   j -0x18
+;   add a0, a2, a6
+;   mv a1, zero
+;   ret
 
 function %d(i64) -> i64 {
 block0(v0: i64):
@@ -283,10 +849,27 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   popcnt a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x40
+;   addi t2, zero, 1
+;   slli t2, t2, 0x3f
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   beq zero, t5, 8
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i32) -> i32 {
 block0(v0: i32):
@@ -294,10 +877,27 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   popcnt a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x20
+;   addi t2, zero, 1
+;   slli t2, t2, 0x1f
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   beq zero, t5, 8
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i16) -> i16 {
 block0(v0: i16):
@@ -305,10 +905,27 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   popcnt a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 0x10
+;   addi t2, zero, 1
+;   slli t2, t2, 0xf
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   beq zero, t5, 8
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %d(i8) -> i8 {
 block0(v0: i8):
@@ -316,10 +933,27 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   mv a2,a0
 ;   popcnt a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a2, a0, 0
+;   ori a0, zero, 0
+;   addi a1, zero, 8
+;   addi t2, zero, 1
+;   slli t2, t2, 7
+;   blez a1, 0x1c
+;   and t5, t2, a2
+;   beq zero, t5, 8
+;   addi a0, a0, 1
+;   addi a1, a1, -1
+;   srli t2, t2, 1
+;   j -0x18
+;   ret
 
 function %bnot_i32(i32) -> i32 {
 block0(v0: i32):
@@ -327,9 +961,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   not a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a0, a0
+;   ret
 
 function %bnot_i64(i64) -> i64 {
 block0(v0: i64):
@@ -337,9 +977,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   not a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a0, a0
+;   ret
 
 function %bnot_i64_with_shift(i64) -> i64 {
 block0(v0: i64):
@@ -349,10 +995,17 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   slli a0,a0,3
 ;   not a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 3
+;   not a0, a0
+;   ret
 
 function %bnot_i128(i128) -> i128 {
 block0(v0: i128):
@@ -360,10 +1013,17 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   not a0,a0
 ;   not a1,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a0, a0
+;   not a1, a1
+;   ret
 
 function %band_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -371,9 +1031,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and a0, a0, a1
+;   ret
 
 function %band_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -381,9 +1047,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and a0, a0, a1
+;   ret
 
 function %band_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -391,10 +1063,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   and a0,a0,a2
 ;   and a1,a1,a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and a0, a0, a2
+;   and a1, a1, a3
+;   ret
 
 function %band_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -403,9 +1082,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 3
+;   ret
 
 function %band_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -414,9 +1099,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 3
+;   ret
 
 function %band_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -426,10 +1117,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   and a0, a0, a1
+;   ret
 
 function %band_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -439,10 +1137,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   and a0,a1,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   and a0, a1, a0
+;   ret
 
 function %bor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -450,9 +1155,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   ret
 
 function %bor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -460,9 +1171,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   ret
 
 function %bor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -470,10 +1187,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a2
 ;   or a1,a1,a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a2
+;   or a1, a1, a3
+;   ret
 
 function %bor_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -482,9 +1206,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ori a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a0, a0, 3
+;   ret
 
 function %bor_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -493,9 +1223,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   ori a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a0, a0, 3
+;   ret
 
 function %bor_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -505,10 +1241,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   or a0, a0, a1
+;   ret
 
 function %bor_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -518,10 +1261,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   or a0,a1,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   or a0, a1, a0
+;   ret
 
 function %bxor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -529,9 +1279,15 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a1
+;   ret
 
 function %bxor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -539,9 +1295,15 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a1
+;   ret
 
 function %bxor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -549,10 +1311,17 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   xor a0,a0,a2
 ;   xor a1,a1,a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a2
+;   xor a1, a1, a3
+;   ret
 
 function %bxor_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -561,9 +1330,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   xori a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a0, a0, 3
+;   ret
 
 function %bxor_i64_constant2(i64) -> i64 {
 block0(v0: i64):
@@ -572,9 +1347,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   xori a0,a0,3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xori a0, a0, 3
+;   ret
 
 function %bxor_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -584,10 +1365,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   xor a0, a0, a1
+;   ret
 
 function %bxor_i64_constant_shift2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -597,10 +1385,17 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a1,3
 ;   xor a0,a1,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 3
+;   xor a0, a1, a0
+;   ret
 
 function %band_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -608,10 +1403,17 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   and a0, a0, a1
+;   ret
 
 function %band_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -619,10 +1421,17 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   and a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   and a0, a0, a1
+;   ret
 
 function %band_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -630,12 +1439,21 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a4,a2
 ;   not a6,a3
 ;   and a0,a0,a4
 ;   and a1,a1,a6
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a4, a2
+;   not a6, a3
+;   and a0, a0, a4
+;   and a1, a1, a6
+;   ret
 
 function %band_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -644,11 +1462,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li a1,4
 ;   not a2,a1
 ;   and a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a1, zero, 4
+;   not a2, a1
+;   and a0, a0, a2
+;   ret
 
 function %band_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -658,11 +1484,19 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a2,a1,4
 ;   not a2,a2
 ;   and a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a1, 4
+;   not a2, a2
+;   and a0, a0, a2
+;   ret
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -670,10 +1504,17 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   or a0, a0, a1
+;   ret
 
 function %bor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -681,10 +1522,17 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   or a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   or a0, a0, a1
+;   ret
 
 function %bor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -692,12 +1540,21 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a4,a2
 ;   not a6,a3
 ;   or a0,a0,a4
 ;   or a1,a1,a6
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a4, a2
+;   not a6, a3
+;   or a0, a0, a4
+;   or a1, a1, a6
+;   ret
 
 function %bor_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -706,11 +1563,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li a1,4
 ;   not a2,a1
 ;   or a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a1, zero, 4
+;   not a2, a1
+;   or a0, a0, a2
+;   ret
 
 function %bor_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -720,11 +1585,19 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a2,a1,4
 ;   not a2,a2
 ;   or a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a1, 4
+;   not a2, a2
+;   or a0, a0, a2
+;   ret
 
 function %bxor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -732,10 +1605,17 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   xor a0, a0, a1
+;   ret
 
 function %bxor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -743,10 +1623,17 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a1,a1
 ;   xor a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a1, a1
+;   xor a0, a0, a1
+;   ret
 
 function %bxor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -754,12 +1641,21 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   not a4,a2
 ;   not a6,a3
 ;   xor a0,a0,a4
 ;   xor a1,a1,a6
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   not a4, a2
+;   not a6, a3
+;   xor a0, a0, a4
+;   xor a1, a1, a6
+;   ret
 
 function %bxor_not_i64_constant(i64) -> i64 {
 block0(v0: i64):
@@ -768,11 +1664,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li a1,4
 ;   not a2,a1
 ;   xor a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a1, zero, 4
+;   not a2, a1
+;   xor a0, a0, a2
+;   ret
 
 function %bxor_not_i64_constant_shift(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -782,11 +1686,19 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   slli a2,a1,4
 ;   not a2,a2
 ;   xor a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a1, 4
+;   not a2, a2
+;   xor a0, a0, a2
+;   ret
 
 function %ishl_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -794,6 +1706,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -808,6 +1721,31 @@ block0(v0: i128, v1: i8):
 ;   select_reg a0,zero,a7##condition=(a6 uge a4)
 ;   select_reg a1,a7,a3##condition=(a6 uge a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a5, a4, a3
+;   sll a7, a0, a3
+;   srl t4, a0, a5
+;   beqz a3, 0xc
+;   ori t1, t4, 0
+;   j 8
+;   ori t1, zero, 0
+;   sll a0, a1, a3
+;   or a3, t1, a0
+;   addi a4, zero, 0x40
+;   andi a6, a2, 0x7f
+;   bgeu a6, a4, 0xc
+;   ori a0, a7, 0
+;   j 8
+;   ori a0, zero, 0
+;   bgeu a6, a4, 0xc
+;   ori a1, a3, 0
+;   j 8
+;   ori a1, a7, 0
+;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -815,6 +1753,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -829,6 +1768,31 @@ block0(v0: i128, v1: i128):
 ;   select_reg a0,zero,t3##condition=(a7 uge a5)
 ;   select_reg a1,t3,a3##condition=(a7 uge a5)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a6, a4, a3
+;   sll t3, a0, a3
+;   srl t0, a0, a6
+;   beqz a3, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   sll a1, a1, a3
+;   or a3, t2, a1
+;   addi a5, zero, 0x40
+;   andi a7, a2, 0x7f
+;   bgeu a7, a5, 0xc
+;   ori a0, t3, 0
+;   j 8
+;   ori a0, zero, 0
+;   bgeu a7, a5, 0xc
+;   ori a1, a3, 0
+;   j 8
+;   ori a1, t3, 0
+;   ret
 
 function %ushr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -836,6 +1800,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -850,6 +1815,30 @@ block0(v0: i128, v1: i8):
 ;   select_reg a0,a5,a0##condition=(a6 uge a4)
 ;   select_reg a1,zero,a5##condition=(a6 uge a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a5, a4, a3
+;   sll a7, a1, a5
+;   beqz a3, 0xc
+;   ori t4, a7, 0
+;   j 8
+;   ori t4, zero, 0
+;   srl t1, a0, a3
+;   or a0, t4, t1
+;   addi a4, zero, 0x40
+;   srl a5, a1, a3
+;   andi a6, a2, 0x7f
+;   bgeu a6, a4, 8
+;   j 8
+;   ori a0, a5, 0
+;   bgeu a6, a4, 0xc
+;   ori a1, a5, 0
+;   j 8
+;   ori a1, zero, 0
+;   ret
 
 function %ushr_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -857,6 +1846,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -871,6 +1861,31 @@ block0(v0: i128, v1: i128):
 ;   select_reg a0,a6,a5##condition=(a7 uge a4)
 ;   select_reg a1,zero,a6##condition=(a7 uge a4)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a6, a4, a3
+;   sll t3, a1, a6
+;   beqz a3, 0xc
+;   ori t0, t3, 0
+;   j 8
+;   ori t0, zero, 0
+;   srl t2, a0, a3
+;   or a5, t0, t2
+;   addi a4, zero, 0x40
+;   srl a6, a1, a3
+;   andi a7, a2, 0x7f
+;   bgeu a7, a4, 0xc
+;   ori a0, a5, 0
+;   j 8
+;   ori a0, a6, 0
+;   bgeu a7, a4, 0xc
+;   ori a1, a6, 0
+;   j 8
+;   ori a1, zero, 0
+;   ret
 
 function %sshr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -878,6 +1893,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -895,6 +1911,36 @@ block0(v0: i128, v1: i8):
 ;   select_reg a0,a4,a0##condition=(t2 uge t0)
 ;   select_reg a1,t3,a4##condition=(t2 uge t0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a5, a4, a3
+;   sll a7, a1, a5
+;   beqz a3, 0xc
+;   ori t4, a7, 0
+;   j 8
+;   ori t4, zero, 0
+;   srl t1, a0, a3
+;   or a0, t4, t1
+;   addi a4, zero, 0x40
+;   sra a4, a1, a3
+;   addi a6, zero, -1
+;   bltz a1, 0xc
+;   ori t3, zero, 0
+;   j 8
+;   ori t3, a6, 0
+;   addi t0, zero, 0x40
+;   andi t2, a2, 0x7f
+;   bgeu t2, t0, 8
+;   j 8
+;   ori a0, a4, 0
+;   bgeu t2, t0, 0xc
+;   ori a1, a4, 0
+;   j 8
+;   ori a1, t3, 0
+;   ret
 
 function %sshr_i128_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -902,6 +1948,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -919,4 +1966,35 @@ block0(v0: i128, v1: i128):
 ;   select_reg a0,a5,a4##condition=(a1 uge t1)
 ;   select_reg a1,t4,a5##condition=(a1 uge t1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a6, a4, a3
+;   sll t3, a1, a6
+;   beqz a3, 0xc
+;   ori t0, t3, 0
+;   j 8
+;   ori t0, zero, 0
+;   srl t2, a0, a3
+;   or a4, t0, t2
+;   addi a5, zero, 0x40
+;   sra a5, a1, a3
+;   addi a7, zero, -1
+;   bltz a1, 0xc
+;   ori t4, zero, 0
+;   j 8
+;   ori t4, a7, 0
+;   addi t1, zero, 0x40
+;   andi a1, a2, 0x7f
+;   bgeu a1, t1, 0xc
+;   ori a0, a4, 0
+;   j 8
+;   ori a0, a5, 0
+;   bgeu a1, t1, 0xc
+;   ori a1, a5, 0
+;   j 8
+;   ori a1, t4, 0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/call-indirect.clif b/cranelift/filetests/filetests/isa/riscv64/call-indirect.clif
index 64b2a5fc2e..0f1e6f3c8d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/call-indirect.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/call-indirect.clif
@@ -9,6 +9,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -19,4 +20,16 @@ block0(v0: i64, v1: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   jalr a1
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/call.clif b/cranelift/filetests/filetests/isa/riscv64/call.clif
index 1f1a4dac75..0e77140a51 100644
--- a/cranelift/filetests/filetests/isa/riscv64/call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/call.clif
@@ -10,6 +10,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -21,6 +22,23 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   auipc a1, 0
+;   ld a1, 0xc(a1)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a1
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f2(i32) -> i64 {
     fn0 = %g(i32 uext) -> i64 
@@ -30,6 +48,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -42,15 +61,41 @@ block0(v0: i32):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   auipc a2, 0
+;   ld a2, 0xc(a2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a2
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f3(i32) -> i32 uext  {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   ret
 
 function %f4(i32) -> i64 {
     fn0 = %g(i32 sext) -> i64 
@@ -60,6 +105,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -72,15 +118,41 @@ block0(v0: i32):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   auipc a2, 0
+;   ld a2, 0xc(a2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a2
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f5(i32) -> i32 sext  {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   sext.w a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   ret
 
 function %f6(i8) -> i64 {
     fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
@@ -91,6 +163,7 @@ block0(v0: i8):
     return v2
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -117,6 +190,37 @@ block0(v0: i8):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori t3, a0, 0
+;   addi sp, sp, -0x10
+;   addi a0, zero, 0x2a
+;   addi a1, zero, 0x2a
+;   addi a2, zero, 0x2a
+;   addi a3, zero, 0x2a
+;   addi a4, zero, 0x2a
+;   addi a5, zero, 0x2a
+;   addi a6, zero, 0x2a
+;   addi a7, zero, 0x2a
+;   slli t3, t3, 0x38
+;   srai t3, t3, 0x38
+;   sd t3, 0(sp)
+;   auipc t3, 0
+;   ld t3, 0xc(t3)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t3
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
 block0(v0: i8):
@@ -124,6 +228,7 @@ block0(v0: i8):
     return v1, v1, v1, v1, v1, v1, v1, v1, v0
 }
 
+; VCode:
 ; block0:
 ;   li a2,42
 ;   mv t1,a2
@@ -146,6 +251,31 @@ block0(v0: i8):
 ;   mv a0,t1
 ;   mv a1,a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a2, zero, 0x2a
+;   ori t1, a2, 0
+;   addi a2, zero, 0x2a
+;   ori a3, a2, 0
+;   addi a4, zero, 0x2a
+;   addi a6, zero, 0x2a
+;   addi t3, zero, 0x2a
+;   addi t0, zero, 0x2a
+;   addi t2, zero, 0x2a
+;   addi a2, zero, 0x2a
+;   sw a4, 0(a1)
+;   sw a6, 8(a1)
+;   sw t3, 0x10(a1)
+;   sw t0, 0x18(a1)
+;   sw t2, 0x20(a1)
+;   sw a2, 0x28(a1)
+;   slli t4, a0, 0x38
+;   srai t4, t4, 0x38
+;   sd a0, 0x30(a1)
+;   ori a0, t1, 0
+;   ori a1, a3, 0
+;   ret
 
 function %f8() {
     fn0 = %g0() -> f32
@@ -165,6 +295,7 @@ block0:
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -202,6 +333,73 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   fsd fs2, -8(sp)
+;   fsd fs3, -0x10(sp)
+;   fsd fs11, -0x18(sp)
+;   addi sp, sp, -0x20
+; block0: ; offset 0x20
+;   auipc a6, 0
+;   ld a6, 0xc(a6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g0 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a6
+;   fmv.d fs11, fa0
+;   auipc a6, 0
+;   ld a6, 0xc(a6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a6
+;   fmv.d fs2, fa0
+;   auipc a6, 0
+;   ld a6, 0xc(a6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g1 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a6
+;   fmv.d fs3, fa0
+;   auipc a6, 0
+;   ld a6, 0xc(a6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g2 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a6
+;   auipc a7, 0
+;   ld a7, 0xc(a7)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g3 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   fmv.d fa0, fs11
+;   jalr a7
+;   auipc t3, 0
+;   ld t3, 0xc(t3)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g4 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   fmv.d fa0, fs2
+;   jalr t3
+;   auipc t4, 0
+;   ld t4, 0xc(t4)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g4 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   fmv.d fa0, fs3
+;   jalr t4
+;   addi sp, sp, 0x20
+;   fld fs2, -8(sp)
+;   fld fs3, -0x10(sp)
+;   fld fs11, -0x18(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f11(i128, i64) -> i64 {
 block0(v0: i128, v1: i64):
@@ -209,9 +407,15 @@ block0(v0: i128, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a0, a1, 0
+;   ret
 
 function %f11_call(i64) -> i64 {
     fn0 = %f11(i128, i64) -> i64
@@ -223,6 +427,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -238,6 +443,27 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a5, a0, 0
+;   addi a0, zero, 0x2a
+;   ori a1, a5, 0
+;   addi a2, zero, 0x2a
+;   auipc a5, 0
+;   ld a5, 0xc(a5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f11 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a5
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f12(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -245,10 +471,17 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a0,a1
 ;   mv a1,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a0, a1, 0
+;   ori a1, a2, 0
+;   ret
 
 function %f12_call(i64) -> i64 {
     fn0 = %f12(i64, i128) -> i64
@@ -260,6 +493,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -274,6 +508,26 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a1, a0, 0
+;   addi a2, zero, 0x2a
+;   addi a0, zero, 0x2a
+;   auipc a5, 0
+;   ld a5, 0xc(a5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f12 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a5
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f13(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -281,10 +535,17 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a0,a1
 ;   mv a1,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a0, a1, 0
+;   ori a1, a2, 0
+;   ret
 
 function %f13_call(i64) -> i64 {
     fn0 = %f13(i64, i128) -> i64
@@ -296,6 +557,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -310,12 +572,33 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a1, a0, 0
+;   addi a2, zero, 0x2a
+;   addi a0, zero, 0x2a
+;   auipc a5, 0
+;   ld a5, 0xc(a5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f13 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a5
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f14(i128, i128, i128, i64, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
     return v4
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -327,6 +610,19 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a0, a7, 0
+;   ld a1, 0x10(s0)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f14_call(i128, i64) -> i128 {
     fn0 = %f14(i128, i128, i128, i64, i128) -> i128
@@ -336,6 +632,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -360,12 +657,41 @@ block0(v0: i128, v1: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a7, a0, 0
+;   ori a6, a2, 0
+;   addi sp, sp, -0x10
+;   sd a1, 0(sp)
+;   ori a5, a1, 0
+;   auipc t3, 0
+;   ld t3, 0xc(t3)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f14 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ori a1, a5, 0
+;   ori a3, a5, 0
+;   ori a0, a7, 0
+;   ori a2, a7, 0
+;   ori a4, a7, 0
+;   jalr t3
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f15(i128, i128, i128, i64, i128) -> i128{
 block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
     return v4
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -377,6 +703,19 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a0, a7, 0
+;   ld a1, 0x10(s0)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f15_call(i128, i64) -> i128 {
     fn0 = %f15(i128, i128, i128, i64, i128) -> i128
@@ -386,6 +725,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -410,6 +750,34 @@ block0(v0: i128, v1: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+; block0: ; offset 0x10
+;   ori a7, a0, 0
+;   ori a6, a2, 0
+;   addi sp, sp, -0x10
+;   sd a1, 0(sp)
+;   ori a5, a1, 0
+;   auipc t3, 0
+;   ld t3, 0xc(t3)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f15 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ori a1, a5, 0
+;   ori a3, a5, 0
+;   ori a0, a7, 0
+;   ori a2, a7, 0
+;   ori a4, a7, 0
+;   jalr t3
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f16() -> i32, i32 {
 block0:
@@ -418,8 +786,15 @@ block0:
     return v0, v1
 }
 
+; VCode:
 ; block0:
 ;   li a0,0
 ;   li a1,1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a0, zero
+;   addi a1, zero, 1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condbr.clif b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
index 35b82af8f7..180b59dbe4 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condbr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
@@ -8,9 +8,18 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   eq a0,a0,a1##ty=i64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a0, a1, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_eq_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -18,9 +27,19 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   eq a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a1, a3, 0x10
+;   bne a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_ne_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -28,9 +47,19 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ne a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a1, a3, 8
+;   beq a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_slt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -38,9 +67,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   slt a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -48,9 +88,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ult a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -58,9 +109,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sle a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bltu a2, a0, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -68,9 +130,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ule a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bltu a2, a0, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -78,9 +151,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sgt a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a2, a0, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -88,9 +172,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ugt a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a2, a0, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -98,9 +193,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sge a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bltu a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -108,9 +214,20 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uge a0,[a0,a1],[a2,a3]##ty=i128
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bltu a0, a2, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -126,6 +243,7 @@ block2:
   return v5
 }
 
+; VCode:
 ; block0:
 ;   eq a2,a0,a1##ty=i64
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -135,6 +253,20 @@ block2:
 ; block2:
 ;   li a0,2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a0, a1, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+;   beqz a2, 0xc
+; block1: ; offset 0x14
+;   addi a0, zero, 1
+;   ret
+; block2: ; offset 0x1c
+;   addi a0, zero, 2
+;   ret
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -146,6 +278,7 @@ block1:
   return v4
 }
 
+; VCode:
 ; block0:
 ;   eq a1,a0,a1##ty=i64
 ;   bne a1,zero,taken(label1),not_taken(label2)
@@ -156,6 +289,16 @@ block1:
 ; block3:
 ;   li a0,1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a0, a1, 0xc
+;   addi a1, zero, 1
+;   j 8
+;   mv a1, zero
+; block1: ; offset 0x10
+;   addi a0, zero, 1
+;   ret
 
 function %i128_brif(i128){
 block0(v0: i128):
@@ -166,6 +309,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   ne a0,[a0,a1],[zerozero]##ty=i128
 ;   bne a0,zero,taken(label1),not_taken(label2)
@@ -175,6 +319,16 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bnez a1, 8
+;   beqz a0, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+; block1: ; offset 0x14
+;   ret
 
 function %i128_bricmp_eq(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -185,6 +339,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   eq a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -194,6 +349,16 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a1, a3, 0x10
+;   bne a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x14
+;   ret
 
 function %i128_bricmp_ne(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -204,6 +369,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   ne a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -213,6 +379,16 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bne a1, a3, 8
+;   beq a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x14
+;   ret
 
 function %i128_bricmp_slt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -223,6 +399,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   slt a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -232,6 +409,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_ult(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -242,6 +430,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   ult a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -251,6 +440,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_sle(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -261,6 +461,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   sle a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -270,6 +471,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bltu a2, a0, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_ule(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -280,6 +492,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   ule a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -289,6 +502,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a1, a3, 0xc
+;   bne a1, a3, 0x10
+;   bltu a2, a0, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_sgt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -299,6 +523,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   sgt a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -308,6 +533,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a2, a0, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_ugt(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -318,6 +554,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   ugt a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -327,6 +564,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bgeu a2, a0, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_sge(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -337,6 +585,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   sge a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -346,6 +595,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   blt a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bltu a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i128_bricmp_uge(i128, i128) {
 block0(v0: i128, v1: i128):
@@ -356,6 +616,7 @@ block1:
   return
 }
 
+; VCode:
 ; block0:
 ;   uge a2,[a0,a1],[a2,a3]##ty=i128
 ;   bne a2,zero,taken(label1),not_taken(label2)
@@ -365,8 +626,17 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
-
-
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bltu a3, a1, 0xc
+;   bne a1, a3, 0x10
+;   bltu a0, a2, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+; block1: ; offset 0x18
+;   ret
 
 function %i8_brif(i8){
 block0(v0: i8):
@@ -377,6 +647,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   andi t2,a0,255
 ;   bne t2,zero,taken(label1),not_taken(label2)
@@ -386,6 +657,12 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+; block1: ; offset 0x4
+;   ret
 
 function %i16_brif(i16){
 block0(v0: i16):
@@ -396,6 +673,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   lui a1,16
 ;   addi a1,a1,4095
@@ -407,6 +685,14 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 0x10
+;   addi a1, a1, -1
+;   and a3, a0, a1
+; block1: ; offset 0xc
+;   ret
 
 function %i32_brif(i32){
 block0(v0: i32):
@@ -417,6 +703,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   addiw t2,a0,0
 ;   bne t2,zero,taken(label1),not_taken(label2)
@@ -426,6 +713,12 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+; block1: ; offset 0x4
+;   ret
 
 function %i64_brif(i64){
 block0(v0: i64):
@@ -436,6 +729,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   bne a0,zero,taken(label1),not_taken(label2)
 ; block1:
@@ -444,4 +738,8 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif
index 951b808d61..873229d089 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif
@@ -10,12 +10,24 @@ block0(v0: i8, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a0,255
 ;   li a4,42
 ;   andi a5,a4,255
 ;   select_reg a0,a1,a2##condition=(a3 eq a5)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a0, 0xff
+;   addi a4, zero, 0x2a
+;   andi a5, a4, 0xff
+;   beq a3, a5, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a1, 0
+;   ret
 
 function %g(i8) -> i8 {
 block0(v0: i8):
@@ -24,12 +36,24 @@ block0(v0: i8):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   li t2,42
 ;   uext.b a1,a0
 ;   uext.b a3,t2
 ;   eq a0,a1,a3##ty=i8
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x2a
+;   andi a1, a0, 0xff
+;   andi a3, t2, 0xff
+;   bne a1, a3, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %h(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -37,12 +61,21 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   and a1,a0,a1
 ;   not a3,a0
 ;   and a5,a3,a2
 ;   or a0,a1,a5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   and a1, a0, a1
+;   not a3, a0
+;   and a5, a3, a2
+;   or a0, a1, a5
+;   ret
 
 function %i(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -50,10 +83,20 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a0,255
 ;   select_i8 a0,a1,a2##condition=a3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a0, 0xff
+;   beqz a3, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, a2, 0
+;   ret
 
 function %i(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -63,12 +106,24 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   addiw a3,a0,0
 ;   li a4,42
 ;   addiw a5,a4,0
 ;   select_reg a0,a1,a2##condition=(a3 eq a5)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a3, a0
+;   addi a4, zero, 0x2a
+;   sext.w a5, a4
+;   beq a3, a5, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a1, 0
+;   ret
 
 function %i128_select(i8, i128, i128) -> i128 {
 block0(v0: i8, v1: i128, v2: i128):
@@ -76,9 +131,22 @@ block0(v0: i8, v1: i128, v2: i128):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mv a7,a1
 ;   andi a5,a0,255
 ;   select_i128 [a0,a1],[a7,a2],[a3,a4]##condition=a5
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a1, 0
+;   andi a5, a0, 0xff
+;   beqz a5, 0x10
+;   ori a0, a7, 0
+;   ori a1, a2, 0
+;   j 0xc
+;   ori a0, a3, 0
+;   ori a1, a4, 0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/constants.clif b/cranelift/filetests/filetests/isa/riscv64/constants.clif
index 43190c6c7e..77d73889e0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/constants.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif
@@ -8,9 +8,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, zero, -1
+;   ret
 
 function %f() -> i16 {
 block0:
@@ -18,9 +24,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a0, zero
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -28,9 +40,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a0, zero
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -38,10 +56,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lui t1,16
 ;   addi a0,t1,4095
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui t1, 0x10
+;   addi a0, t1, -1
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -49,9 +74,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x00, 0x00, 0xff, 0xff
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -59,9 +94,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff00000000
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0xff, 0xff, 0x00, 0x00
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -69,9 +114,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff000000000000
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xff, 0xff
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -79,9 +134,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, zero, -1
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -89,9 +150,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lui a0,1048560
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a0, 0xffff0
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -99,9 +166,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffff0000ffff
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xff, 0xff, 0x00, 0x00
+;   .byte 0xff, 0xff, 0xff, 0xff
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -109,9 +186,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000ffffffff
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xff, 0xff, 0xff, 0xff
+;   .byte 0x00, 0x00, 0xff, 0xff
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -119,9 +206,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffffffff
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xff, 0xff, 0xff, 0xff
+;   .byte 0xff, 0xff, 0x00, 0x00
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -129,9 +226,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xf34bf0a31212003a
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x3a, 0x00, 0x12, 0x12
+;   .byte 0xa3, 0xf0, 0x4b, 0xf3
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -139,9 +246,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e900001ef40000
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x00, 0x00, 0xf4, 0x1e
+;   .byte 0x00, 0x00, 0xe9, 0x12
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -149,9 +266,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e9ffff1ef4ffff
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xff, 0xff, 0xf4, 0x1e
+;   .byte 0xff, 0xff, 0xe9, 0x12
+;   ret
 
 function %f() -> i32 {
 block0:
@@ -159,9 +286,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,-1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, zero, -1
+;   ret
 
 function %f() -> i32 {
 block0:
@@ -169,9 +302,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xfffffff7
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xf7, 0xff, 0xff, 0xff
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -179,9 +322,19 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xfffffff7
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0xf7, 0xff, 0xff, 0xff
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ret
 
 function %f() -> i64 {
 block0:
@@ -189,9 +342,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,-9
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, zero, -9
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -199,10 +358,21 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0x3ff0000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t1, 0
+;   ld t1, 0xc(t1)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0x3f
+;   fmv.d.x fa0, t1
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -210,10 +380,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lui t1,264704
 ;   fmv.w.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui t1, 0x40a00
+;   fmv.w.x fa0, t1
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -221,10 +398,21 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0x4049000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t1, 0
+;   ld t1, 0xc(t1)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x49, 0x40
+;   fmv.d.x fa0, t1
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -232,10 +420,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lui t1,271488
 ;   fmv.w.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui t1, 0x42480
+;   fmv.w.x fa0, t1
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -243,10 +438,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li t1,0
 ;   fmv.d.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv t1, zero
+;   fmv.d.x fa0, t1
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -254,10 +456,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li t1,0
 ;   fmv.w.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv t1, zero
+;   fmv.w.x fa0, t1
+;   ret
 
 function %f() -> f64 {
 block0:
@@ -265,10 +474,21 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xc030000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t1, 0
+;   ld t1, 0xc(t1)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x30, 0xc0
+;   fmv.d.x fa0, t1
+;   ret
 
 function %f() -> f32 {
 block0:
@@ -276,8 +496,18 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   auipc t1,0; ld t1,12(t1); j 8; .4byte 0xc1800000
 ;   fmv.w.x fa0,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc t1, 0
+;   lwu t1, 0xc(t1)
+;   j 8
+;   .byte 0x00, 0x00, 0x80, 0xc1
+;   fmv.w.x fa0, t1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
index 9dfc4f2c4b..0605bdd829 100644
--- a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
@@ -10,10 +10,18 @@ block0(v0: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   addi a0,a0,42
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   addi a0, a0, 0x2a
+;   ret
 
 function %f2(i8, i64) -> i64 {
 block0(v0: i8, v1: i64):
@@ -22,10 +30,18 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sext.b a2,a0
 ;   add a0,a2,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a0, 0x38
+;   srai a2, a2, 0x38
+;   add a0, a2, a1
+;   ret
 
 function %i128_uextend_i64(i64) -> i128 {
 block0(v0: i64):
@@ -33,9 +49,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a1, zero
+;   ret
 
 function %i128_sextend_i64(i64) -> i128 {
 block0(v0: i64):
@@ -43,10 +65,18 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   slt t2,a0,zero
 ;   sext.b1 a1,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltz t2, a0
+;   slli a1, t2, 0x3f
+;   srai a1, a1, 0x3f
+;   ret
 
 function %i128_uextend_i32(i32) -> i128 {
 block0(v0: i32):
@@ -54,10 +84,18 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   mv a1, zero
+;   ret
 
 function %i128_sextend_i32(i32) -> i128 {
 block0(v0: i32):
@@ -65,11 +103,21 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.w a0,a0
 ;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   sltz a1, a0
+;   slli a1, a1, 0x3f
+;   srai a1, a1, 0x3f
+;   ret
 
 function %i128_uextend_i16(i16) -> i128 {
 block0(v0: i16):
@@ -77,10 +125,18 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   mv a1, zero
+;   ret
 
 function %i128_sextend_i16(i16) -> i128 {
 block0(v0: i16):
@@ -88,11 +144,21 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h a0,a0
 ;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a0, a0, 0x30
+;   sltz a1, a0
+;   slli a1, a1, 0x3f
+;   srai a1, a1, 0x3f
+;   ret
 
 function %i128_uextend_i8(i8) -> i128 {
 block0(v0: i8):
@@ -100,10 +166,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   li a1,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   mv a1, zero
+;   ret
 
 function %i128_sextend_i8(i8) -> i128 {
 block0(v0: i8):
@@ -111,9 +184,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   sltz a1, a0
+;   slli a1, a1, 0x3f
+;   srai a1, a1, 0x3f
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/fcmp.clif b/cranelift/filetests/filetests/isa/riscv64/fcmp.clif
index 98f47dfa0b..769f54591d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fcmp.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fcmp.clif
@@ -12,6 +12,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   li t1,0
 ;   fmv.d.x ft1,t1
@@ -25,6 +26,16 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv t1, zero
+;   fmv.d.x ft1, t1
+;   mv a2, zero
+;   fmv.d.x ft5, a2
+;   fle.d a5, ft5, ft1
+; block1: ; offset 0x14
+;   ret
 
 function %f1() {
 block0:
@@ -36,6 +47,7 @@ block1:
     return
 }
 
+; VCode:
 ; block0:
 ;   li t1,0
 ;   fmv.d.x ft1,t1
@@ -49,4 +61,14 @@ block1:
 ;   j label3
 ; block3:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv t1, zero
+;   fmv.d.x ft1, t1
+;   mv a2, zero
+;   fmv.d.x ft5, a2
+;   fle.d a5, ft5, ft1
+; block1: ; offset 0x14
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
index 61df690bb7..eb1be56123 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
@@ -8,9 +8,15 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.lu fa0, a0
+;   ret
 
 function u0:0(i8) -> f64 {
 block0(v0: i8):
@@ -18,9 +24,15 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.d.lu fa0, a0
+;   ret
 
 function u0:0(i16) -> f32 {
 block0(v0: i16):
@@ -28,9 +40,15 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.lu fa0, a0
+;   ret
 
 function u0:0(i16) -> f64 {
 block0(v0: i16):
@@ -38,9 +56,15 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.d.lu fa0, a0
+;   ret
 
 function u0:0(f32) -> i8 {
 block0(v0: f32):
@@ -48,9 +72,32 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i8 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x00, 0x00, 0x80, 0xbf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x43800
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function u0:0(f64) -> i8 {
 block0(v0: f64):
@@ -58,9 +105,37 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i8 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0xbf
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x70, 0x40
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function u0:0(f32) -> i16 {
 block0(v0: f32):
@@ -68,9 +143,32 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i16 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x00, 0x00, 0x80, 0xbf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x47800
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function u0:0(f64) -> i16 {
 block0(v0: f64):
@@ -78,7 +176,35 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i16 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0xbf
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0x40
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif
index 2b5f6cea89..aa11b4b296 100644
--- a/cranelift/filetests/filetests/isa/riscv64/float.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/float.clif
@@ -8,9 +8,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fadd.s fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fadd.s fa0, fa0, fa1
+;   ret
 
 function %f2(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -18,9 +24,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fadd.d fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fadd.d fa0, fa0, fa1
+;   ret
 
 function %f3(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -28,9 +40,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsub.s fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsub.s fa0, fa0, fa1
+;   ret
 
 function %f4(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -38,9 +56,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsub.d fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsub.d fa0, fa0, fa1
+;   ret
 
 function %f5(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -48,9 +72,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmul.s fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmul.s fa0, fa0, fa1
+;   ret
 
 function %f6(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -58,9 +88,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmul.d fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmul.d fa0, fa0, fa1
+;   ret
 
 function %f7(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -68,9 +104,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fdiv.s fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fdiv.s fa0, fa0, fa1
+;   ret
 
 function %f8(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -78,9 +120,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fdiv.d fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fdiv.d fa0, fa0, fa1
+;   ret
 
 function %f9(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -88,10 +136,36 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   fmin.s fa0,ft5,fa1##tmp=a1 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a1, ft5, ft5
+;   beqz a1, 0x3c
+;   feq.s a1, fa1, fa1
+;   beqz a1, 0x34
+;   fmin.s fa0, ft5, fa1
+;   fclass.s a1, ft5
+;   andi a1, a1, 0x18
+;   beqz a1, 0x34
+;   fclass.s a1, fa1
+;   andi a1, a1, 0x18
+;   beqz a1, 0x28
+;   fmv.x.w a1, ft5
+;   fmv.x.w t6, fa1
+;   or a1, a1, t6
+;   fmv.w.x fa0, a1
+;   j 0x14
+;   addi a1, zero, -1
+;   srli a1, a1, 0x16
+;   slli a1, a1, 0x16
+;   fmv.w.x fa0, a1
+;   ret
 
 function %f10(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -99,10 +173,36 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   fmin.d fa0,ft5,fa1##tmp=a1 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a1, ft5, ft5
+;   beqz a1, 0x3c
+;   feq.d a1, fa1, fa1
+;   beqz a1, 0x34
+;   fmin.d fa0, ft5, fa1
+;   fclass.d a1, ft5
+;   andi a1, a1, 0x18
+;   beqz a1, 0x34
+;   fclass.d a1, fa1
+;   andi a1, a1, 0x18
+;   beqz a1, 0x28
+;   fmv.x.d a1, ft5
+;   fmv.x.d t6, fa1
+;   or a1, a1, t6
+;   fmv.d.x fa0, a1
+;   j 0x14
+;   addi a1, zero, -1
+;   srli a1, a1, 0x33
+;   slli a1, a1, 0x33
+;   fmv.d.x fa0, a1
+;   ret
 
 function %f11(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -110,10 +210,36 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   fmax.s fa0,ft5,fa1##tmp=a1 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a1, ft5, ft5
+;   beqz a1, 0x3c
+;   feq.s a1, fa1, fa1
+;   beqz a1, 0x34
+;   fmax.s fa0, ft5, fa1
+;   fclass.s a1, ft5
+;   andi a1, a1, 0x18
+;   beqz a1, 0x34
+;   fclass.s a1, fa1
+;   andi a1, a1, 0x18
+;   beqz a1, 0x28
+;   fmv.x.w a1, ft5
+;   fmv.x.w t6, fa1
+;   and a1, a1, t6
+;   fmv.w.x fa0, a1
+;   j 0x14
+;   addi a1, zero, -1
+;   srli a1, a1, 0x16
+;   slli a1, a1, 0x16
+;   fmv.w.x fa0, a1
+;   ret
 
 function %f12(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -121,10 +247,36 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   fmax.d fa0,ft5,fa1##tmp=a1 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a1, ft5, ft5
+;   beqz a1, 0x3c
+;   feq.d a1, fa1, fa1
+;   beqz a1, 0x34
+;   fmax.d fa0, ft5, fa1
+;   fclass.d a1, ft5
+;   andi a1, a1, 0x18
+;   beqz a1, 0x34
+;   fclass.d a1, fa1
+;   andi a1, a1, 0x18
+;   beqz a1, 0x28
+;   fmv.x.d a1, ft5
+;   fmv.x.d t6, fa1
+;   and a1, a1, t6
+;   fmv.d.x fa0, a1
+;   j 0x14
+;   addi a1, zero, -1
+;   srli a1, a1, 0x33
+;   slli a1, a1, 0x33
+;   fmv.d.x fa0, a1
+;   ret
 
 function %f13(f32) -> f32 {
 block0(v0: f32):
@@ -132,9 +284,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt.s fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt.s fa0, fa0
+;   ret
 
 function %f15(f64) -> f64 {
 block0(v0: f64):
@@ -142,9 +300,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fsqrt.d fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsqrt.d fa0, fa0
+;   ret
 
 function %f16(f32) -> f32 {
 block0(v0: f32):
@@ -152,9 +316,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs.s fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs.s fa0, fa0
+;   ret
 
 function %f17(f64) -> f64 {
 block0(v0: f64):
@@ -162,9 +332,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fabs.d fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fabs.d fa0, fa0
+;   ret
 
 function %f18(f32) -> f32 {
 block0(v0: f32):
@@ -172,9 +348,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg.s fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg.s fa0, fa0
+;   ret
 
 function %f19(f64) -> f64 {
 block0(v0: f64):
@@ -182,9 +364,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fneg.d fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fneg.d fa0, fa0
+;   ret
 
 function %f20(f32) -> f64 {
 block0(v0: f32):
@@ -192,9 +380,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.s fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x53, 0x75, 0x05, 0x42
+;   ret
 
 function %f21(f64) -> f32 {
 block0(v0: f64):
@@ -202,9 +396,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.d fa0,fa0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.d fa0, fa0
+;   ret
 
 function %f22(f32) -> f32 {
 block0(v0: f32):
@@ -212,10 +412,30 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a0, ft5, ft5
+;   beqz a0, 0x28
+;   lui t6, 0x4b800
+;   fmv.w.x ft4, t6
+;   fabs.s fa0, ft5
+;   flt.s a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.s a0, ft5, rup
+;   fcvt.s.l fa0, a0, rup
+;   fsgnj.s fa0, fa0, ft5
+;   j 0x10
+;   fadd.s fa0, ft5, ft5
+;   j 8
+;   fmv.s fa0, ft5
+;   ret
 
 function %f22(f64) -> f64 {
 block0(v0: f64):
@@ -223,10 +443,34 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a0, ft5, ft5
+;   beqz a0, 0x38
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x40, 0x43
+;   fmv.d.x ft4, t6
+;   fabs.d fa0, ft5
+;   flt.d a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.d a0, ft5, rup
+;   fcvt.d.l fa0, a0, rup
+;   fsgnj.d fa0, fa0, ft5
+;   j 0x10
+;   fadd.d fa0, ft5, ft5
+;   j 8
+;   fmv.d fa0, ft5
+;   ret
 
 function %f23(f32) -> f32 {
 block0(v0: f32):
@@ -234,10 +478,30 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a0, ft5, ft5
+;   beqz a0, 0x28
+;   lui t6, 0x4b800
+;   fmv.w.x ft4, t6
+;   fabs.s fa0, ft5
+;   flt.s a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.s a0, ft5, rdn
+;   fcvt.s.l fa0, a0, rdn
+;   fsgnj.s fa0, fa0, ft5
+;   j 0x10
+;   fadd.s fa0, ft5, ft5
+;   j 8
+;   fmv.s fa0, ft5
+;   ret
 
 function %f24(f64) -> f64 {
 block0(v0: f64):
@@ -245,10 +509,34 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a0, ft5, ft5
+;   beqz a0, 0x38
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x40, 0x43
+;   fmv.d.x ft4, t6
+;   fabs.d fa0, ft5
+;   flt.d a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.d a0, ft5, rdn
+;   fcvt.d.l fa0, a0, rdn
+;   fsgnj.d fa0, fa0, ft5
+;   j 0x10
+;   fadd.d fa0, ft5, ft5
+;   j 8
+;   fmv.d fa0, ft5
+;   ret
 
 function %f25(f32) -> f32 {
 block0(v0: f32):
@@ -256,10 +544,30 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a0, ft5, ft5
+;   beqz a0, 0x28
+;   lui t6, 0x4b800
+;   fmv.w.x ft4, t6
+;   fabs.s fa0, ft5
+;   flt.s a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.s a0, ft5, rtz
+;   fcvt.s.l fa0, a0, rtz
+;   fsgnj.s fa0, fa0, ft5
+;   j 0x10
+;   fadd.s fa0, ft5, ft5
+;   j 8
+;   fmv.s fa0, ft5
+;   ret
 
 function %f26(f64) -> f64 {
 block0(v0: f64):
@@ -267,10 +575,34 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a0, ft5, ft5
+;   beqz a0, 0x38
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x40, 0x43
+;   fmv.d.x ft4, t6
+;   fabs.d fa0, ft5
+;   flt.d a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.d a0, ft5, rtz
+;   fcvt.d.l fa0, a0, rtz
+;   fsgnj.d fa0, fa0, ft5
+;   j 0x10
+;   fadd.d fa0, ft5, ft5
+;   j 8
+;   fmv.d fa0, ft5
+;   ret
 
 function %f27(f32) -> f32 {
 block0(v0: f32):
@@ -278,10 +610,30 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.s a0, ft5, ft5
+;   beqz a0, 0x28
+;   lui t6, 0x4b800
+;   fmv.w.x ft4, t6
+;   fabs.s fa0, ft5
+;   flt.s a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.s a0, ft5, rne
+;   fcvt.s.l fa0, a0, rne
+;   fsgnj.s fa0, fa0, ft5
+;   j 0x10
+;   fadd.s fa0, ft5, ft5
+;   j 8
+;   fmv.s fa0, ft5
+;   ret
 
 function %f28(f64) -> f64 {
 block0(v0: f64):
@@ -289,10 +641,34 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fmv.d ft5,fa0
 ;   nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmv.d ft5, fa0
+;   feq.d a0, ft5, ft5
+;   beqz a0, 0x38
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x40, 0x43
+;   fmv.d.x ft4, t6
+;   fabs.d fa0, ft5
+;   flt.d a0, ft4, fa0
+;   bnez a0, 0x1c
+;   fcvt.l.d a0, ft5, rne
+;   fcvt.d.l fa0, a0, rne
+;   fsgnj.d fa0, fa0, ft5
+;   j 0x10
+;   fadd.d fa0, ft5, ft5
+;   j 8
+;   fmv.d fa0, ft5
+;   ret
 
 function %f29(f32, f32, f32) -> f32 {
 block0(v0: f32, v1: f32, v2: f32):
@@ -300,9 +676,15 @@ block0(v0: f32, v1: f32, v2: f32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fmadd.s fa0,fa0,fa1,fa2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmadd.s fa0, fa0, fa1, fa2
+;   ret
 
 function %f30(f64, f64, f64) -> f64 {
 block0(v0: f64, v1: f64, v2: f64):
@@ -310,9 +692,15 @@ block0(v0: f64, v1: f64, v2: f64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   fmadd.d fa0,fa0,fa1,fa2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fmadd.d fa0, fa0, fa1, fa2
+;   ret
 
 function %f31(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -320,9 +708,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsgnj.s fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsgnj.s fa0, fa0, fa1
+;   ret
 
 function %f32(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -330,9 +724,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   fsgnj.d fa0,fa0,fa1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fsgnj.d fa0, fa0, fa1
+;   ret
 
 function %f33(f32) -> i32 {
 block0(v0: f32):
@@ -340,9 +740,32 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x00, 0x00, 0x80, 0xbf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x4f800
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f34(f32) -> i32 {
 block0(v0: f32):
@@ -350,9 +773,32 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x01, 0x00, 0x00, 0xcf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x4f000
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.w.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f35(f32) -> i64 {
 block0(v0: f32):
@@ -360,9 +806,32 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x00, 0x00, 0x80, 0xbf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x5f800
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.lu.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f36(f32) -> i64 {
 block0(v0: f32):
@@ -370,9 +839,32 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0x40
+;   auipc t6, 0
+;   lwu t6, 0xc(t6)
+;   j 8
+;   .byte 0x01, 0x00, 0x00, 0xdf
+;   fmv.w.x ft3, t6
+;   fle.s a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   lui t6, 0x5f000
+;   fmv.w.x ft3, t6
+;   fle.s a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.l.s a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f37(f64) -> i32 {
 block0(v0: f64):
@@ -380,9 +872,37 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0xbf
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0x41
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.wu.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f38(f64) -> i32 {
 block0(v0: f64):
@@ -390,9 +910,37 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x20, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0xc1
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0x41
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.w.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f39(f64) -> i64 {
 block0(v0: f64):
@@ -400,9 +948,37 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0xbf
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xf0, 0x43
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.lu.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f40(f64) -> i64 {
 block0(v0: f64):
@@ -410,9 +986,37 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0x54
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x01, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0xc3
+;   fmv.d.x ft3, t6
+;   fle.d a0, fa0, ft3
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0xe0, 0x43
+;   fmv.d.x ft3, t6
+;   fle.d a0, ft3, fa0
+;   beqz a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
+;   fcvt.l.d a0, fa0, rtz
+;   j 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: bad_toint
+;   ret
 
 function %f41(i32) -> f32 {
 block0(v0: i32):
@@ -420,9 +1024,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.wu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.wu fa0, a0
+;   ret
 
 function %f42(i32) -> f32 {
 block0(v0: i32):
@@ -430,9 +1040,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.w fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.w fa0, a0
+;   ret
 
 function %f43(i64) -> f32 {
 block0(v0: i64):
@@ -440,9 +1056,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.lu fa0, a0
+;   ret
 
 function %f44(i64) -> f32 {
 block0(v0: i64):
@@ -450,9 +1072,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.s.l fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.s.l fa0, a0
+;   ret
 
 function %f45(i32) -> f64 {
 block0(v0: i32):
@@ -460,9 +1088,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.wu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.d.wu fa0, a0
+;   ret
 
 function %f46(i32) -> f64 {
 block0(v0: i32):
@@ -470,9 +1104,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.w fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x53, 0x75, 0x05, 0xd2
+;   ret
 
 function %f47(i64) -> f64 {
 block0(v0: i64):
@@ -480,9 +1120,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.lu fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.d.lu fa0, a0
+;   ret
 
 function %f48(i64) -> f64 {
 block0(v0: i64):
@@ -490,9 +1136,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt.d.l fa0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fcvt.d.l fa0, a0
+;   ret
 
 function %f49(f32) -> i32 {
 block0(v0: f32):
@@ -500,9 +1152,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.wu.s a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f50(f32) -> i32 {
 block0(v0: f32):
@@ -510,9 +1172,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.w.s a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f51(f32) -> i64 {
 block0(v0: f32):
@@ -520,9 +1192,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.lu.s a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f52(f32) -> i64 {
 block0(v0: f32):
@@ -530,9 +1212,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.s a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.l.s a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f53(f64) -> i32 {
 block0(v0: f64):
@@ -540,9 +1232,19 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.wu.d a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f54(f64) -> i32 {
 block0(v0: f64):
@@ -550,9 +1252,19 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.w.d a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f55(f64) -> i64 {
 block0(v0: f64):
@@ -560,9 +1272,19 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.lu.d a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
 function %f56(f64) -> i64 {
 block0(v0: f64):
@@ -570,7 +1292,17 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   feq.d a0, fa0, fa0
+;   beqz a0, 0xc
+;   fcvt.l.d a0, fa0, rtz
+;   j 8
+;   mv a0, zero
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
index 56061f6c3f..ac99995e49 100644
--- a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
@@ -8,12 +8,24 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   li a2,-1
 ;   select_reg a1,zero,a2##condition=(zero eq a0)
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   addi a2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a1, a2, 0
+;   j 8
+;   ori a1, zero, 0
+;   ori a0, a1, 0
+;   ret
 
 function %bmask_i128_i64(i128) -> i64 {
 block0(v0: i128):
@@ -21,11 +33,22 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   li a2,-1
 ;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   addi a2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, zero, 0
+;   ret
 
 function %bmask_i128_i32(i128) -> i32 {
 block0(v0: i128):
@@ -33,11 +56,22 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   li a2,-1
 ;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   addi a2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, zero, 0
+;   ret
 
 function %bmask_i128_i16(i128) -> i16 {
 block0(v0: i128):
@@ -45,11 +79,22 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   li a2,-1
 ;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   addi a2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, zero, 0
+;   ret
 
 function %bmask_i128_i8(i128) -> i8 {
 block0(v0: i128):
@@ -57,11 +102,22 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   or a0,a0,a1
 ;   li a2,-1
 ;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or a0, a0, a1
+;   addi a2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, zero, 0
+;   ret
 
 function %bmask_i64_i128(i64) -> i128 {
 block0(v0: i64):
@@ -69,11 +125,22 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   li t2,-1
 ;   select_reg a1,zero,t2##condition=(zero eq a0)
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, -1
+;   beq zero, a0, 0xc
+;   ori a1, t2, 0
+;   j 8
+;   ori a1, zero, 0
+;   ori a0, a1, 0
+;   ret
 
 function %bmask_i32_i128(i32) -> i128 {
 block0(v0: i32):
@@ -81,12 +148,23 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   addiw t2,a0,0
 ;   li a1,-1
 ;   select_reg a1,zero,a1##condition=(zero eq t2)
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   addi a1, zero, -1
+;   beq zero, t2, 8
+;   j 8
+;   ori a1, zero, 0
+;   ori a0, a1, 0
+;   ret
 
 function %bmask_i16_i128(i16) -> i128 {
 block0(v0: i16):
@@ -94,6 +172,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lui a1,16
 ;   addi a1,a1,4095
@@ -102,6 +181,19 @@ block0(v0: i16):
 ;   select_reg a1,zero,a5##condition=(zero eq a3)
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui a1, 0x10
+;   addi a1, a1, -1
+;   and a3, a0, a1
+;   addi a5, zero, -1
+;   beq zero, a3, 0xc
+;   ori a1, a5, 0
+;   j 8
+;   ori a1, zero, 0
+;   ori a0, a1, 0
+;   ret
 
 function %bmask_i8_i128(i8) -> i128 {
 block0(v0: i8):
@@ -109,10 +201,21 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   andi t2,a0,255
 ;   li a1,-1
 ;   select_reg a1,zero,a1##condition=(zero eq t2)
 ;   mv a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   addi a1, zero, -1
+;   beq zero, t2, 8
+;   j 8
+;   ori a1, zero, 0
+;   ori a0, a1, 0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/iabs-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/iabs-zbb.clif
index 6ca55dd82c..eff3769068 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iabs-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iabs-zbb.clif
@@ -7,11 +7,20 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b t2,a0
 ;   sub a1,zero,t2
 ;   max a0,t2,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai t2, t2, 0x38
+;   neg a1, t2
+;   .byte 0x33, 0xe5, 0xb3, 0x0a
+;   ret
 
 function %iabs_i16(i16) -> i16 {
 block0(v0: i16):
@@ -19,11 +28,20 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h t2,a0
 ;   sub a1,zero,t2
 ;   max a0,t2,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai t2, t2, 0x30
+;   neg a1, t2
+;   .byte 0x33, 0xe5, 0xb3, 0x0a
+;   ret
 
 function %iabs_i32(i32) -> i32 {
 block0(v0: i32):
@@ -31,11 +49,20 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.w t2,a0
 ;   sub a1,zero,t2
 ;   max a0,t2,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srai t2, t2, 0x20
+;   neg a1, t2
+;   .byte 0x33, 0xe5, 0xb3, 0x0a
+;   ret
 
 function %iabs_i64(i64) -> i64 {
 block0(v0: i64):
@@ -43,8 +70,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sub t2,zero,a0
 ;   max a0,a0,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg t2, a0
+;   .byte 0x33, 0x65, 0x75, 0x0a
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/iabs.clif b/cranelift/filetests/filetests/isa/riscv64/iabs.clif
index 92dd1fe9b4..f22f7796c5 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iabs.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iabs.clif
@@ -7,11 +7,23 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b t2,a0
 ;   sub a1,zero,t2
 ;   select_reg a0,t2,a1##condition=(t2 sgt a1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai t2, t2, 0x38
+;   neg a1, t2
+;   blt a1, t2, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, t2, 0
+;   ret
 
 function %iabs_i16(i16) -> i16 {
 block0(v0: i16):
@@ -19,11 +31,23 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h t2,a0
 ;   sub a1,zero,t2
 ;   select_reg a0,t2,a1##condition=(t2 sgt a1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai t2, t2, 0x30
+;   neg a1, t2
+;   blt a1, t2, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, t2, 0
+;   ret
 
 function %iabs_i32(i32) -> i32 {
 block0(v0: i32):
@@ -31,11 +55,23 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.w t2,a0
 ;   sub a1,zero,t2
 ;   select_reg a0,t2,a1##condition=(t2 sgt a1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srai t2, t2, 0x20
+;   neg a1, t2
+;   blt a1, t2, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, t2, 0
+;   ret
 
 function %iabs_i64(i64) -> i64 {
 block0(v0: i64):
@@ -43,8 +79,16 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   sub t2,zero,a0
 ;   select_reg a0,a0,t2##condition=(a0 sgt t2)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   neg t2, a0
+;   blt t2, a0, 8
+;   ori a0, t2, 0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
index 72845dcea0..0aa8b9674d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
@@ -10,6 +10,7 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lui t1,14
 ;   addi t1,t1,3532
@@ -19,4 +20,20 @@ block0:
 ;   uext.h a7,a2
 ;   ne a0,a5,a7##ty=i16
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lui t1, 0xe
+;   addi t1, t1, -0x234
+;   lui a2, 0xe
+;   addi a2, a2, -0x234
+;   slli a5, t1, 0x30
+;   srli a5, a5, 0x30
+;   slli a7, a2, 0x30
+;   srli a7, a7, 0x30
+;   beq a5, a7, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/multivalue-ret.clif b/cranelift/filetests/filetests/isa/riscv64/multivalue-ret.clif
index d19960db92..0af146bd88 100644
--- a/cranelift/filetests/filetests/isa/riscv64/multivalue-ret.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/multivalue-ret.clif
@@ -10,8 +10,15 @@ block1:
   return v0, v1
 }
 
+; VCode:
 ; block0:
 ;   li a0,1
 ;   li a1,2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a0, zero, 1
+;   addi a1, zero, 2
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif
index 3081ff2361..2fe4905439 100644
--- a/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif
@@ -8,9 +8,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   addw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addw a0, a0, a1
+;   ret
 
 function %add16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -18,9 +24,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   addw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addw a0, a0, a1
+;   ret
 
 function %add32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -28,9 +40,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   addw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addw a0, a0, a1
+;   ret
 
 function %add32_8(i32, i8) -> i32 {
 block0(v0: i32, v1: i8):
@@ -39,10 +57,18 @@ block0(v0: i32, v1: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sext.b a1,a1
 ;   addw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 0x38
+;   srai a1, a1, 0x38
+;   addw a0, a0, a1
+;   ret
 
 function %add64_32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -51,8 +77,16 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sext.w a1,a1
 ;   add a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a1, 0x20
+;   srai a1, a1, 0x20
+;   add a0, a0, a1
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/prologue.clif b/cranelift/filetests/filetests/isa/riscv64/prologue.clif
index c546973bb6..08c7db5583 100644
--- a/cranelift/filetests/filetests/isa/riscv64/prologue.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/prologue.clif
@@ -75,6 +75,7 @@ block0(v0: f64):
     return v62
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -170,6 +171,103 @@ block0(v0: f64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   fsd fs0, -8(sp)
+;   fsd fs2, -0x10(sp)
+;   fsd fs3, -0x18(sp)
+;   fsd fs4, -0x20(sp)
+;   fsd fs5, -0x28(sp)
+;   fsd fs6, -0x30(sp)
+;   fsd fs7, -0x38(sp)
+;   fsd fs8, -0x40(sp)
+;   fsd fs9, -0x48(sp)
+;   fsd fs10, -0x50(sp)
+;   fsd fs11, -0x58(sp)
+;   addi sp, sp, -0x60
+; block0: ; offset 0x40
+;   fadd.d ft3, fa0, fa0
+;   fadd.d ft4, fa0, fa0
+;   fadd.d ft5, fa0, fa0
+;   fadd.d ft6, fa0, fa0
+;   fadd.d ft7, fa0, fa0
+;   fadd.d fa1, fa0, fa0
+;   fadd.d fa2, fa0, fa0
+;   fadd.d fa3, fa0, fa0
+;   fadd.d fa4, fa0, fa0
+;   fadd.d fa5, fa0, fa0
+;   fadd.d fa6, fa0, fa0
+;   fadd.d fa7, fa0, fa0
+;   fadd.d ft8, fa0, fa0
+;   fadd.d ft9, fa0, fa0
+;   fadd.d ft10, fa0, fa0
+;   fadd.d ft11, fa0, fa0
+;   fadd.d ft0, fa0, fa0
+;   fadd.d ft1, fa0, fa0
+;   fadd.d ft2, fa0, fa0
+;   fadd.d fs3, fa0, fa0
+;   fadd.d fs4, fa0, fa0
+;   fadd.d fs5, fa0, fa0
+;   fadd.d fs6, fa0, fa0
+;   fadd.d fs7, fa0, fa0
+;   fadd.d fs8, fa0, fa0
+;   fadd.d fs9, fa0, fa0
+;   fadd.d fs10, fa0, fa0
+;   fadd.d fs11, fa0, fa0
+;   fadd.d fs0, fa0, fa0
+;   fadd.d fs1, fa0, fa0
+;   fadd.d fs2, fa0, fa0
+;   fadd.d ft3, fa0, ft3
+;   fadd.d ft4, ft4, ft5
+;   fadd.d ft5, ft6, ft7
+;   fadd.d ft6, fa1, fa2
+;   fadd.d ft7, fa3, fa4
+;   fadd.d fa0, fa5, fa6
+;   fadd.d fa1, fa7, ft8
+;   fadd.d fa2, ft9, ft10
+;   fadd.d fa3, ft11, ft0
+;   fadd.d fa4, ft1, ft2
+;   fadd.d fa5, fs3, fs4
+;   fadd.d fa6, fs5, fs6
+;   fadd.d fa7, fs7, fs8
+;   fadd.d ft8, fs9, fs10
+;   fadd.d ft9, fs11, fs0
+;   fadd.d ft10, fs1, fs2
+;   fadd.d ft3, ft3, ft4
+;   fadd.d ft4, ft5, ft6
+;   fadd.d ft5, ft7, fa0
+;   fadd.d ft6, fa1, fa2
+;   fadd.d ft7, fa3, fa4
+;   fadd.d fa0, fa5, fa6
+;   fadd.d fa1, fa7, ft8
+;   fadd.d fa2, ft9, ft10
+;   fadd.d ft3, ft3, ft4
+;   fadd.d ft4, ft5, ft6
+;   fadd.d ft5, ft7, fa0
+;   fadd.d ft6, fa1, fa2
+;   fadd.d ft3, ft3, ft4
+;   fadd.d ft4, ft5, ft6
+;   fadd.d fa0, ft3, ft4
+;   addi sp, sp, 0x60
+;   fld fs0, -8(sp)
+;   fld fs2, -0x10(sp)
+;   fld fs3, -0x18(sp)
+;   fld fs4, -0x20(sp)
+;   fld fs5, -0x28(sp)
+;   fld fs6, -0x30(sp)
+;   fld fs7, -0x38(sp)
+;   fld fs8, -0x40(sp)
+;   fld fs9, -0x48(sp)
+;   fld fs10, -0x50(sp)
+;   fld fs11, -0x58(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %f2(i64) -> i64 {
 block0(v0: i64):
@@ -217,6 +315,7 @@ block0(v0: i64):
     return v36
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -276,4 +375,65 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   sd s5, -8(sp)
+;   sd s6, -0x10(sp)
+;   sd s7, -0x18(sp)
+;   sd s8, -0x20(sp)
+;   sd s9, -0x28(sp)
+;   sd s10, -0x30(sp)
+;   addi sp, sp, -0x30
+; block0: ; offset 0x2c
+;   add t3, a0, a0
+;   add t4, a0, t3
+;   add t0, a0, t4
+;   add t1, a0, t0
+;   add t2, a0, t1
+;   add a1, a0, t2
+;   add a2, a0, a1
+;   add a3, a0, a2
+;   add a4, a0, a3
+;   add a5, a0, a4
+;   add a6, a0, a5
+;   add a7, a0, a6
+;   add s5, a0, a7
+;   add s6, a0, s5
+;   add s7, a0, s6
+;   add s8, a0, s7
+;   add s9, a0, s8
+;   add s10, a0, s9
+;   add t3, a0, t3
+;   add t4, t4, t0
+;   add t0, t1, t2
+;   add t1, a1, a2
+;   add t2, a3, a4
+;   add a0, a5, a6
+;   add a1, a7, s5
+;   add a2, s6, s7
+;   add a3, s8, s9
+;   add t3, s10, t3
+;   add t4, t4, t0
+;   add t0, t1, t2
+;   add t1, a0, a1
+;   add t2, a2, a3
+;   add t3, t3, t4
+;   add t4, t0, t1
+;   add t3, t2, t3
+;   add a0, t4, t3
+;   addi sp, sp, 0x30
+;   ld s5, -8(sp)
+;   ld s6, -0x10(sp)
+;   ld s7, -0x18(sp)
+;   ld s8, -0x20(sp)
+;   ld s9, -0x28(sp)
+;   ld s10, -0x30(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/reduce.clif b/cranelift/filetests/filetests/isa/riscv64/reduce.clif
index 22d00e355f..72127917ca 100644
--- a/cranelift/filetests/filetests/isa/riscv64/reduce.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/reduce.clif
@@ -8,8 +8,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_32(i128) -> i32 {
 block0(v0: i128):
@@ -17,8 +22,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_16(i128) -> i16 {
 block0(v0: i128):
@@ -26,8 +36,13 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %ireduce_128_8(i128) -> i8 {
 block0(v0: i128):
@@ -35,6 +50,11 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
index 50751ca5be..b9db2ff6c8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
@@ -7,8 +7,13 @@ block0(v0: r64):
   return v0
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %f1(r64) -> i8 {
 block0(v0: r64):
@@ -16,9 +21,18 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   is_null a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   beq zero, a0, 0xc
+;   mv a0, zero
+;   j 8
+;   addi a0, zero, 1
+;   ret
 
 function %f2(r64) -> i8 {
 block0(v0: r64):
@@ -26,9 +40,18 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   is_invalid a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   beq zero, a0, 0xc
+;   mv a0, zero
+;   j 8
+;   addi a0, zero, 1
+;   ret
 
 function %f3() -> r64 {
 block0:
@@ -36,9 +59,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   li a0,0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a0, zero
+;   ret
 
 function %f4(r64, r64) -> r64, r64, r64 {
     fn0 = %f(r64) -> i8
@@ -60,6 +89,7 @@ block3(v7: r64, v8: r64):
     return v7, v8, v9
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -100,4 +130,45 @@ block3(v7: r64, v8: r64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   sd s7, -8(sp)
+;   addi sp, sp, -0x30
+; block0: ; offset 0x18
+;   sd a0, 8(sp)
+;   sd a1, 0x10(sp)
+;   ori s7, a2, 0
+;   auipc a1, 0
+;   ld a1, 0xc(a1)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr a1
+;   mv a1, sp
+;   ld t4, 8(sp)
+;   sd t4, 0(a1)
+;   andi a1, a0, 0xff
+;   beqz a1, 0x10
+; block1: ; offset 0x50
+;   ori a0, t4, 0
+;   ld a1, 0x10(sp)
+;   j 0xc
+; block2: ; offset 0x5c
+;   ori a1, t4, 0
+;   ld a0, 0x10(sp)
+; block3: ; offset 0x64
+;   mv a2, sp
+;   ld a2, 0(a2)
+;   ori a3, s7, 0
+;   sd a2, 0(a3)
+;   addi sp, sp, 0x30
+;   ld s7, -8(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/shift-op.clif b/cranelift/filetests/filetests/isa/riscv64/shift-op.clif
index 103aac23cb..4b4cbd8e11 100644
--- a/cranelift/filetests/filetests/isa/riscv64/shift-op.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/shift-op.clif
@@ -10,10 +10,17 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   slli a1,a0,3
 ;   add a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a1, a0, 3
+;   add a0, a0, a1
+;   ret
 
 function %f(i32) -> i32 {
 block0(v0: i32):
@@ -22,7 +29,13 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   slliw a0,a0,53
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slliw a0, a0, 0x15
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif b/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif
index d54feeea36..ea2544e773 100644
--- a/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif
@@ -12,6 +12,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -30,6 +31,36 @@ block0(v0: i128, v1: i128):
 ;   select_reg a0,t4,a1##condition=(a2 uge t1)
 ;   select_reg a1,a1,t4##condition=(a2 uge t1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a6, a4, a3
+;   srl t3, a0, a3
+;   sll t0, a1, a6
+;   ori t1, a1, 0
+;   beqz a3, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a1, t3, t2
+;   srl a4, t1, a3
+;   sll a5, a0, a6
+;   beqz a3, 0xc
+;   ori a7, a5, 0
+;   j 8
+;   ori a7, zero, 0
+;   or t4, a4, a7
+;   addi t1, zero, 0x40
+;   andi a2, a2, 0x7f
+;   bgeu a2, t1, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, t4, 0
+;   bgeu a2, t1, 8
+;   ori a1, t4, 0
+;   ret
 
 function %f0(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -37,6 +68,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a7,a0
 ;   andi a0,a1,63
@@ -48,6 +80,22 @@ block0(v0: i64, v1: i64):
 ;   select_reg t0,zero,t3##condition=(a0 eq zero)
 ;   or a0,a6,t0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a0, 0
+;   andi a0, a1, 0x3f
+;   addi a2, zero, 0x40
+;   sub a4, a2, a0
+;   ori t0, a7, 0
+;   srl a6, t0, a0
+;   sll t3, t0, a4
+;   beqz a0, 0xc
+;   ori t0, t3, 0
+;   j 8
+;   ori t0, zero, 0
+;   or a0, a6, t0
+;   ret
 
 function %f1(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -55,6 +103,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   andi a2,a1,31
@@ -65,6 +114,22 @@ block0(v0: i32, v1: i32):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   andi a2, a1, 0x1f
+;   addi a4, zero, 0x20
+;   sub a6, a4, a2
+;   srl t3, a0, a2
+;   sll t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -72,6 +137,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   andi a2,a1,15
@@ -82,6 +148,22 @@ block0(v0: i16, v1: i16):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   andi a2, a1, 0xf
+;   addi a4, zero, 0x10
+;   sub a6, a4, a2
+;   srl t3, a0, a2
+;   sll t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %f3(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -89,6 +171,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   andi a2,a1,7
@@ -99,6 +182,21 @@ block0(v0: i8, v1: i8):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 7
+;   addi a4, zero, 8
+;   sub a6, a4, a2
+;   srl t3, a0, a2
+;   sll t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %i128_rotl(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -106,6 +204,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a3,a2,63
 ;   li a4,64
@@ -124,6 +223,36 @@ block0(v0: i128, v1: i128):
 ;   select_reg a0,t4,a1##condition=(a2 uge t1)
 ;   select_reg a1,a1,t4##condition=(a2 uge t1)
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a3, a2, 0x3f
+;   addi a4, zero, 0x40
+;   sub a6, a4, a3
+;   sll t3, a0, a3
+;   srl t0, a1, a6
+;   ori t1, a1, 0
+;   beqz a3, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a1, t3, t2
+;   sll a4, t1, a3
+;   srl a5, a0, a6
+;   beqz a3, 0xc
+;   ori a7, a5, 0
+;   j 8
+;   ori a7, zero, 0
+;   or t4, a4, a7
+;   addi t1, zero, 0x40
+;   andi a2, a2, 0x7f
+;   bgeu a2, t1, 0xc
+;   ori a0, a1, 0
+;   j 8
+;   ori a0, t4, 0
+;   bgeu a2, t1, 8
+;   ori a1, t4, 0
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -131,6 +260,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a7,a0
 ;   andi a0,a1,63
@@ -142,6 +272,22 @@ block0(v0: i64, v1: i64):
 ;   select_reg t0,zero,t3##condition=(a0 eq zero)
 ;   or a0,a6,t0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a0, 0
+;   andi a0, a1, 0x3f
+;   addi a2, zero, 0x40
+;   sub a4, a2, a0
+;   ori t0, a7, 0
+;   sll a6, t0, a0
+;   srl t3, t0, a4
+;   beqz a0, 0xc
+;   ori t0, t3, 0
+;   j 8
+;   ori t0, zero, 0
+;   or a0, a6, t0
+;   ret
 
 function %f5(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -149,6 +295,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   andi a2,a1,31
@@ -159,6 +306,22 @@ block0(v0: i32, v1: i32):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   andi a2, a1, 0x1f
+;   addi a4, zero, 0x20
+;   sub a6, a4, a2
+;   sll t3, a0, a2
+;   srl t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %f6(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -166,6 +329,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   andi a2,a1,15
@@ -176,6 +340,22 @@ block0(v0: i16, v1: i16):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   andi a2, a1, 0xf
+;   addi a4, zero, 0x10
+;   sub a6, a4, a2
+;   sll t3, a0, a2
+;   srl t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %f7(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -183,6 +363,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   andi a2,a1,7
@@ -193,6 +374,21 @@ block0(v0: i8, v1: i8):
 ;   select_reg t2,zero,t0##condition=(a2 eq zero)
 ;   or a0,t3,t2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 7
+;   addi a4, zero, 8
+;   sub a6, a4, a2
+;   sll t3, a0, a2
+;   srl t0, a0, a6
+;   beqz a2, 0xc
+;   ori t2, t0, 0
+;   j 8
+;   ori t2, zero, 0
+;   or a0, t3, t2
+;   ret
 
 function %f8(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -200,9 +396,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srl a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srl a0, a0, a1
+;   ret
 
 function %f9(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -210,9 +412,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srlw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srlw a0, a0, a1
+;   ret
 
 function %f10(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -220,11 +428,20 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   andi a2,a1,15
 ;   srlw a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   andi a2, a1, 0xf
+;   srlw a0, a0, a2
+;   ret
 
 function %f11(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -232,11 +449,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   andi a2,a1,7
 ;   srlw a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 7
+;   srlw a0, a0, a2
+;   ret
 
 function %f12(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -244,9 +469,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sll a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sll a0, a0, a1
+;   ret
 
 function %f13(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -254,9 +485,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllw a0, a0, a1
+;   ret
 
 function %f14(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -264,10 +501,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a1,a1,15
 ;   sllw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a1, a1, 0xf
+;   sllw a0, a0, a1
+;   ret
 
 function %f15(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -275,10 +519,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   andi a1,a1,7
 ;   sllw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a1, a1, 7
+;   sllw a0, a0, a1
+;   ret
 
 function %f16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -286,9 +537,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sra a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sra a0, a0, a1
+;   ret
 
 function %f17(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -296,9 +553,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sraw a0,a0,a1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sraw a0, a0, a1
+;   ret
 
 function %f18(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -306,11 +569,20 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.h a0,a0
 ;   andi a2,a1,15
 ;   sra a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a0, a0, 0x30
+;   andi a2, a1, 0xf
+;   sra a0, a0, a2
+;   ret
 
 function %f19(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -318,11 +590,20 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   andi a2,a1,7
 ;   sra a0,a0,a2
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   andi a2, a1, 7
+;   sra a0, a0, a2
+;   ret
 
 function %f20(i64) -> i64 {
 block0(v0: i64):
@@ -331,6 +612,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,17
 ;   andi a1,t2,63
@@ -341,6 +623,21 @@ block0(v0: i64):
 ;   select_reg t1,zero,t4##condition=(a1 eq zero)
 ;   or a0,a7,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x11
+;   andi a1, t2, 0x3f
+;   addi a3, zero, 0x40
+;   sub a5, a3, a1
+;   srl a7, a0, a1
+;   sll t4, a0, a5
+;   beqz a1, 0xc
+;   ori t1, t4, 0
+;   j 8
+;   ori t1, zero, 0
+;   or a0, a7, t1
+;   ret
 
 function %f21(i64) -> i64 {
 block0(v0: i64):
@@ -349,6 +646,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,17
 ;   andi a1,t2,63
@@ -359,6 +657,21 @@ block0(v0: i64):
 ;   select_reg t1,zero,t4##condition=(a1 eq zero)
 ;   or a0,a7,t1
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x11
+;   andi a1, t2, 0x3f
+;   addi a3, zero, 0x40
+;   sub a5, a3, a1
+;   sll a7, a0, a1
+;   srl t4, a0, a5
+;   beqz a1, 0xc
+;   ori t1, t4, 0
+;   j 8
+;   ori t1, zero, 0
+;   or a0, a7, t1
+;   ret
 
 function %f22(i32) -> i32 {
 block0(v0: i32):
@@ -367,6 +680,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.w t2,a0
 ;   li a1,17
@@ -378,6 +692,23 @@ block0(v0: i32):
 ;   select_reg a0,zero,t1##condition=(a3 eq zero)
 ;   or a0,t4,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli t2, t2, 0x20
+;   addi a1, zero, 0x11
+;   andi a3, a1, 0x1f
+;   addi a5, zero, 0x20
+;   sub a7, a5, a3
+;   sll t4, t2, a3
+;   srl t1, t2, a7
+;   beqz a3, 0xc
+;   ori a0, t1, 0
+;   j 8
+;   ori a0, zero, 0
+;   or a0, t4, a0
+;   ret
 
 function %f23(i16) -> i16 {
 block0(v0: i16):
@@ -386,6 +717,7 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.h t2,a0
 ;   li a1,10
@@ -397,6 +729,23 @@ block0(v0: i16):
 ;   select_reg a0,zero,t1##condition=(a3 eq zero)
 ;   or a0,t4,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli t2, t2, 0x30
+;   addi a1, zero, 0xa
+;   andi a3, a1, 0xf
+;   addi a5, zero, 0x10
+;   sub a7, a5, a3
+;   sll t4, t2, a3
+;   srl t1, t2, a7
+;   beqz a3, 0xc
+;   ori a0, t1, 0
+;   j 8
+;   ori a0, zero, 0
+;   or a0, t4, a0
+;   ret
 
 function %f24(i8) -> i8 {
 block0(v0: i8):
@@ -405,6 +754,7 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.b t2,a0
 ;   li a1,3
@@ -416,6 +766,22 @@ block0(v0: i8):
 ;   select_reg a0,zero,t1##condition=(a3 eq zero)
 ;   or a0,t4,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   addi a1, zero, 3
+;   andi a3, a1, 7
+;   addi a5, zero, 8
+;   sub a7, a5, a3
+;   sll t4, t2, a3
+;   srl t1, t2, a7
+;   beqz a3, 0xc
+;   ori a0, t1, 0
+;   j 8
+;   ori a0, zero, 0
+;   or a0, t4, a0
+;   ret
 
 function %f25(i64) -> i64 {
 block0(v0: i64):
@@ -424,9 +790,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srli a0,a0,17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srli a0, a0, 0x11
+;   ret
 
 function %f26(i64) -> i64 {
 block0(v0: i64):
@@ -435,9 +807,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srai a0,a0,17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srai a0, a0, 0x11
+;   ret
 
 function %f27(i64) -> i64 {
 block0(v0: i64):
@@ -446,7 +824,13 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   slli a0,a0,17
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x11
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
index 7706815fa5..1edc46acbc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
@@ -8,16 +8,26 @@ block0:
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_leaf_zero(i64 stack_limit) {
 block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_gv_leaf_zero(i64 vmctx) {
     gv0 = vmctx
@@ -28,8 +38,13 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ret
 
 function %stack_limit_call_zero(i64 stack_limit) {
     fn0 = %foo()
@@ -38,6 +53,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -50,6 +66,25 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   bgeu sp, a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+; block0: ; offset 0x18
+;   auipc t2, 0
+;   ld t2, 0xc(t2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t2
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_limit_gv_call_zero(i64 vmctx) {
     gv0 = vmctx
@@ -62,6 +97,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -76,6 +112,27 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   ld t6, 0(a0)
+;   ld t6, 4(t6)
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+; block0: ; offset 0x20
+;   auipc t2, 0
+;   ld t2, 0xc(t2)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t2
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 168
@@ -83,6 +140,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -96,6 +154,22 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   andi t6, a0, 0xb0
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   addi sp, sp, -0xb0
+; block0: ; offset 0x20
+;   addi sp, sp, 0xb0
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %huge_stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 400000
@@ -103,6 +177,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -122,6 +197,38 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   bgeu sp, a0, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   lui t5, 0x62
+;   addi t5, t5, -0x580
+;   add t6, t5, a0
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   lui a0, 0x62
+;   addi a0, a0, -0x580
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfff9e
+;   addi t6, t6, 0x580
+;   add sp, t6, sp
+; block0: ; offset 0x58
+;   lui t6, 0x62
+;   addi t6, t6, -0x580
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %limit_preamble(i64 vmctx) {
     gv0 = vmctx
@@ -133,6 +240,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -148,6 +256,24 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   ld t6, 0(a0)
+;   ld t6, 4(t6)
+;   andi t6, t6, 0x20
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   addi sp, sp, -0x20
+; block0: ; offset 0x28
+;   addi sp, sp, 0x20
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %limit_preamble_huge(i64 vmctx) {
     gv0 = vmctx
@@ -159,6 +285,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -180,6 +307,40 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   ld t6, 0(a0)
+;   ld t6, 4(t6)
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   lui t5, 0x62
+;   addi t5, t5, -0x580
+;   add t6, t5, t6
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   lui a0, 0x62
+;   addi a0, a0, -0x580
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfff9e
+;   addi t6, t6, 0x580
+;   add sp, t6, sp
+; block0: ; offset 0x60
+;   lui t6, 0x62
+;   addi t6, t6, -0x580
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %limit_preamble_huge_offset(i64 vmctx) {
     gv0 = vmctx
@@ -190,6 +351,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -204,4 +366,27 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   auipc t6, 0
+;   ld t6, 0xc(t6)
+;   j 0xc
+;   .byte 0x80, 0x1a, 0x06, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   add t6, t6, a0
+;   ld t6, 0(t6)
+;   andi t6, t6, 0x20
+;   bgeu sp, t6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
+;   addi sp, sp, -0x20
+; block0: ; offset 0x3c
+;   addi sp, sp, 0x20
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/stack.clif b/cranelift/filetests/filetests/isa/riscv64/stack.clif
index d70250ceb4..4e83ecdbfd 100644
--- a/cranelift/filetests/filetests/isa/riscv64/stack.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack.clif
@@ -11,6 +11,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -23,6 +24,20 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x10
+; block0: ; offset 0x14
+;   mv a0, sp
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_addr_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -33,6 +48,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -48,6 +64,32 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   lui a0, 0x18
+;   addi a0, a0, 0x6b0
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfffe8
+;   addi t6, t6, -0x6b0
+;   add sp, t6, sp
+; block0: ; offset 0x3c
+;   mv a0, sp
+;   lui t6, 0x18
+;   addi t6, t6, 0x6b0
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_load_small() -> i64 {
 ss0 = explicit_slot 8
@@ -57,6 +99,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -70,6 +113,21 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x10
+; block0: ; offset 0x14
+;   mv t1, sp
+;   ld a0, 0(t1)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_load_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -80,6 +138,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -96,6 +155,33 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   lui a0, 0x18
+;   addi a0, a0, 0x6b0
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfffe8
+;   addi t6, t6, -0x6b0
+;   add sp, t6, sp
+; block0: ; offset 0x3c
+;   mv t1, sp
+;   ld a0, 0(t1)
+;   lui t6, 0x18
+;   addi t6, t6, 0x6b0
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_store_small(i64) {
 ss0 = explicit_slot 8
@@ -105,6 +191,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -118,6 +205,21 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x10
+; block0: ; offset 0x14
+;   mv t2, sp
+;   sd a0, 0(t2)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %stack_store_big(i64) {
 ss0 = explicit_slot 100000
@@ -128,6 +230,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -144,6 +247,33 @@ block0(v0: i64):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   lui a0, 0x18
+;   addi a0, a0, 0x6b0
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfffe8
+;   addi t6, t6, -0x6b0
+;   add sp, t6, sp
+; block0: ; offset 0x3c
+;   mv t2, sp
+;   sd a0, 0(t2)
+;   lui t6, 0x18
+;   addi t6, t6, 0x6b0
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i8_spill_slot(i8) -> i8, i64 {
     ss0 = explicit_slot 1000
@@ -296,6 +426,7 @@ block0(v0: i8):
   return v0, v137
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -477,6 +608,189 @@ block0(v0: i8):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   sd s1, -8(sp)
+;   sd s2, -0x10(sp)
+;   sd s3, -0x18(sp)
+;   sd s4, -0x20(sp)
+;   sd s5, -0x28(sp)
+;   sd s6, -0x30(sp)
+;   sd s7, -0x38(sp)
+;   sd s8, -0x40(sp)
+;   sd s9, -0x48(sp)
+;   sd s10, -0x50(sp)
+;   sd s11, -0x58(sp)
+;   addi sp, sp, -0x500
+; block0: ; offset 0x40
+;   sd a0, 0x3e8(sp)
+;   addi t3, zero, 2
+;   addi t1, t3, 1
+;   sd t1, 0x498(sp)
+;   addi t3, zero, 4
+;   addi t2, t3, 3
+;   sd t2, 0x490(sp)
+;   addi t3, zero, 6
+;   addi a1, t3, 5
+;   sd a1, 0x488(sp)
+;   addi t3, zero, 8
+;   addi a2, t3, 7
+;   sd a2, 0x480(sp)
+;   addi t3, zero, 0xa
+;   addi a3, t3, 9
+;   sd a3, 0x478(sp)
+;   addi t3, zero, 0xc
+;   addi a4, t3, 0xb
+;   sd a4, 0x470(sp)
+;   addi t3, zero, 0xe
+;   addi a5, t3, 0xd
+;   sd a5, 0x468(sp)
+;   addi t3, zero, 0x10
+;   addi a6, t3, 0xf
+;   sd a6, 0x460(sp)
+;   addi t3, zero, 0x12
+;   addi a7, t3, 0x11
+;   sd a7, 0x458(sp)
+;   addi t3, zero, 0x14
+;   addi t3, t3, 0x13
+;   sd t3, 0x450(sp)
+;   addi t3, zero, 0x16
+;   addi t4, t3, 0x15
+;   sd t4, 0x448(sp)
+;   addi t3, zero, 0x18
+;   addi s6, t3, 0x17
+;   sd s6, 0x440(sp)
+;   addi t3, zero, 0x1a
+;   addi s7, t3, 0x19
+;   sd s7, 0x438(sp)
+;   addi t3, zero, 0x1c
+;   addi s8, t3, 0x1b
+;   sd s8, 0x430(sp)
+;   addi t3, zero, 0x1e
+;   addi s9, t3, 0x1d
+;   sd s9, 0x428(sp)
+;   addi t3, zero, 0x20
+;   addi s10, t3, 0x1f
+;   sd s10, 0x420(sp)
+;   addi t3, zero, 0x22
+;   addi s11, t3, 0x21
+;   sd s11, 0x418(sp)
+;   addi t3, zero, 0x24
+;   addi s1, t3, 0x23
+;   sd s1, 0x410(sp)
+;   addi t3, zero, 0x26
+;   addi s2, t3, 0x25
+;   sd s2, 0x408(sp)
+;   addi t3, zero, 0x1e
+;   addi s3, t3, 0x27
+;   sd s3, 0x400(sp)
+;   addi t3, zero, 0x20
+;   addi s4, t3, 0x1f
+;   sd s4, 0x3f8(sp)
+;   addi t3, zero, 0x22
+;   addi s5, t3, 0x21
+;   sd s5, 0x3f0(sp)
+;   addi t3, zero, 0x24
+;   addi s5, t3, 0x23
+;   addi t3, zero, 0x26
+;   addi a0, t3, 0x25
+;   addi t3, zero, 0x1e
+;   addi t0, t3, 0x27
+;   addi t3, zero, 0x20
+;   addi t1, t3, 0x1f
+;   addi t3, zero, 0x22
+;   addi t2, t3, 0x21
+;   addi t3, zero, 0x24
+;   addi a1, t3, 0x23
+;   addi t3, zero, 0x26
+;   addi a2, t3, 0x25
+;   addi t3, zero, 0x1e
+;   addi a3, t3, 0x27
+;   addi t3, zero, 0x20
+;   addi a4, t3, 0x1f
+;   addi t3, zero, 0x22
+;   addi a5, t3, 0x21
+;   addi t3, zero, 0x24
+;   addi a6, t3, 0x23
+;   addi t3, zero, 0x26
+;   addi a7, t3, 0x25
+;   ld t3, 0x498(sp)
+;   addi t3, t3, 0x27
+;   ld t4, 0x488(sp)
+;   ld s2, 0x490(sp)
+;   add t4, s2, t4
+;   ld s9, 0x478(sp)
+;   ld s7, 0x480(sp)
+;   add s6, s7, s9
+;   ld s3, 0x468(sp)
+;   ld s1, 0x470(sp)
+;   add s7, s1, s3
+;   ld s8, 0x458(sp)
+;   ld s9, 0x460(sp)
+;   add s8, s9, s8
+;   ld s2, 0x448(sp)
+;   ld s11, 0x450(sp)
+;   add s9, s11, s2
+;   ld s10, 0x438(sp)
+;   ld s11, 0x440(sp)
+;   add s10, s11, s10
+;   ld s1, 0x428(sp)
+;   ld s11, 0x430(sp)
+;   add s11, s11, s1
+;   ld s1, 0x418(sp)
+;   ld s4, 0x420(sp)
+;   add s1, s4, s1
+;   ld s2, 0x408(sp)
+;   ld s3, 0x410(sp)
+;   add s2, s3, s2
+;   ld s4, 0x3f8(sp)
+;   ld s3, 0x400(sp)
+;   add s3, s3, s4
+;   ld s4, 0x3f0(sp)
+;   add s5, s4, s5
+;   add t0, a0, t0
+;   add t1, t1, t2
+;   add t2, a1, a2
+;   add a0, a3, a4
+;   add a1, a5, a6
+;   add a2, a7, t3
+;   add t4, t4, s6
+;   add a3, s7, s8
+;   add a4, s9, s10
+;   add a5, s11, s1
+;   add a6, s2, s3
+;   add t0, s5, t0
+;   add t1, t1, t2
+;   add t2, a0, a1
+;   add t4, a2, t4
+;   add a0, a3, a4
+;   add a1, a5, a6
+;   add t0, t0, t1
+;   add t4, t2, t4
+;   add t1, a0, a1
+;   add t4, t0, t4
+;   add a1, t1, t4
+;   ld a0, 0x3e8(sp)
+;   addi sp, sp, 0x500
+;   ld s1, -8(sp)
+;   ld s2, -0x10(sp)
+;   ld s3, -0x18(sp)
+;   ld s4, -0x20(sp)
+;   ld s5, -0x28(sp)
+;   ld s6, -0x30(sp)
+;   ld s7, -0x38(sp)
+;   ld s8, -0x40(sp)
+;   ld s9, -0x48(sp)
+;   ld s10, -0x50(sp)
+;   ld s11, -0x58(sp)
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_store(i128) {
 ss0 = explicit_slot 16
@@ -486,6 +800,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -501,6 +816,23 @@ block0(v0: i128):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x10
+; block0: ; offset 0x14
+;   ori a2, a0, 0
+;   mv a0, sp
+;   sd a2, 0(a0)
+;   sd a1, 8(a0)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_store_inst_offset(i128) {
 ss0 = explicit_slot 16
@@ -511,6 +843,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -526,6 +859,23 @@ block0(v0: i128):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x20
+; block0: ; offset 0x14
+;   ori a2, a0, 0
+;   addi a0, sp, 0x20
+;   sd a2, 0(a0)
+;   sd a1, 8(a0)
+;   addi sp, sp, 0x20
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_store_big(i128) {
 ss0 = explicit_slot 100000
@@ -536,6 +886,7 @@ block0(v0: i128):
   return
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -554,6 +905,35 @@ block0(v0: i128):
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   lui a0, 0x18
+;   addi a0, a0, 0x6b0
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfffe8
+;   addi t6, t6, -0x6b0
+;   add sp, t6, sp
+; block0: ; offset 0x3c
+;   ori a2, a0, 0
+;   mv a0, sp
+;   sd a2, 0(a0)
+;   sd a1, 8(a0)
+;   lui t6, 0x18
+;   addi t6, t6, 0x6b0
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_load() -> i128 {
 ss0 = explicit_slot 16
@@ -563,6 +943,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -577,6 +958,22 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x10
+; block0: ; offset 0x14
+;   mv t2, sp
+;   ld a0, 0(t2)
+;   ld a1, 8(t2)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_load_inst_offset() -> i128 {
 ss0 = explicit_slot 16
@@ -587,6 +984,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -601,6 +999,22 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   addi sp, sp, -0x20
+; block0: ; offset 0x14
+;   addi t2, sp, 0x20
+;   ld a0, 0(t2)
+;   ld a1, 8(t2)
+;   addi sp, sp, 0x20
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
 function %i128_stack_load_big() -> i128 {
 ss0 = explicit_slot 100000
@@ -611,6 +1025,7 @@ block0:
   return v0
 }
 
+; VCode:
 ;   add sp,-16
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
@@ -628,4 +1043,32 @@ block0:
 ;   ld fp,0(sp)
 ;   add sp,+16
 ;   ret
+; 
+; Disassembled:
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   ori s0, sp, 0
+;   lui a0, 0x18
+;   addi a0, a0, 0x6b0
+;   auipc t5, 0
+;   ld t5, 0xc(t5)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %Probestack 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   jalr t5
+;   lui t6, 0xfffe8
+;   addi t6, t6, -0x6b0
+;   add sp, t6, sp
+; block0: ; offset 0x3c
+;   mv t2, sp
+;   ld a0, 0(t2)
+;   ld a1, 8(t2)
+;   lui t6, 0x18
+;   addi t6, t6, 0x6b0
+;   add sp, t6, sp
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/symbol-value.clif b/cranelift/filetests/filetests/isa/riscv64/symbol-value.clif
index a1353158cd..fd98472db0 100644
--- a/cranelift/filetests/filetests/isa/riscv64/symbol-value.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/symbol-value.clif
@@ -10,7 +10,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   load_sym a0,%my_global+0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   auipc a0, 0
+;   ld a0, 0xc(a0)
+;   j 0xc
+;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %my_global 0
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/traps.clif b/cranelift/filetests/filetests/isa/riscv64/traps.clif
index da61762059..bf260f2d1d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/traps.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/traps.clif
@@ -7,8 +7,13 @@ block0:
   trap user0
 }
 
+; VCode:
 ; block0:
 ;   udf##trap_code=user0
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 
 function %g(i64) {
 block0(v0: i64):
@@ -18,6 +23,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   li t2,42
 ;   eq a1,a0,t2##ty=i64
@@ -26,6 +32,19 @@ block0(v0: i64):
 ;   ret
 ; block1:
 ;   udf##trap_code=user0
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x2a
+;   bne a0, t2, 0xc
+;   addi a1, zero, 1
+;   j 8
+;   mv a1, zero
+;   bnez a1, 8
+; block1: ; offset 0x18
+;   ret
+; block2: ; offset 0x1c
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 
 function %h() {
 block0:
@@ -33,7 +52,13 @@ block0:
   return
 }
 
+; VCode:
 ; block0:
 ;   ebreak
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ebreak
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
index e65998f284..3287a4aaed 100644
--- a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
@@ -8,6 +8,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,127
 ;   uext.w a1,a0
@@ -16,6 +17,19 @@ block0(v0: i32):
 ;   srli a7,a0,32
 ;   trap_if a7,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x7f
+;   slli a1, a0, 0x20
+;   srli a1, a1, 0x20
+;   slli a3, t2, 0x20
+;   srli a3, a3, 0x20
+;   add a0, a1, a3
+;   srli a7, a0, 0x20
+;   beqz a7, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -24,6 +38,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,127
 ;   uext.w a1,t2
@@ -32,6 +47,19 @@ block0(v0: i32):
 ;   srli a7,a0,32
 ;   trap_if a7,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x7f
+;   slli a1, t2, 0x20
+;   srli a1, a1, 0x20
+;   slli a3, a0, 0x20
+;   srli a3, a3, 0x20
+;   add a0, a1, a3
+;   srli a7, a0, 0x20
+;   beqz a7, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -39,6 +67,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   uext.w a2,a1
@@ -46,6 +75,18 @@ block0(v0: i32, v1: i32):
 ;   srli a6,a0,32
 ;   trap_if a6,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   slli a2, a1, 0x20
+;   srli a2, a2, 0x20
+;   add a0, a0, a2
+;   srli a6, a0, 0x20
+;   beqz a6, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -54,6 +95,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   mv a4,a0
 ;   li t2,127
@@ -61,6 +103,19 @@ block0(v0: i64):
 ;   ult a3,a0,a4##ty=i64
 ;   trap_if a3,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a4, a0, 0
+;   addi t2, zero, 0x7f
+;   add a0, a4, t2
+;   bgeu a0, a4, 0xc
+;   addi a3, zero, 1
+;   j 8
+;   mv a3, zero
+;   beqz a3, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -69,12 +124,25 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   li t2,127
 ;   add a0,t2,a0
 ;   ult a3,a0,t2##ty=i64
 ;   trap_if a3,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x7f
+;   add a0, t2, a0
+;   bgeu a0, t2, 0xc
+;   addi a3, zero, 1
+;   j 8
+;   mv a3, zero
+;   beqz a3, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -82,6 +150,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   add a1,a0,a1
 ;   mv a3,a1
@@ -89,4 +158,17 @@ block0(v0: i64, v1: i64):
 ;   mv a0,a3
 ;   trap_if a2,user0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   add a1, a0, a1
+;   ori a3, a1, 0
+;   bgeu a3, a0, 0xc
+;   addi a2, zero, 1
+;   j 8
+;   mv a2, zero
+;   ori a0, a3, 0
+;   beqz a2, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/uextend-sextend.clif b/cranelift/filetests/filetests/isa/riscv64/uextend-sextend.clif
index 151bf45a64..8f48e813ed 100644
--- a/cranelift/filetests/filetests/isa/riscv64/uextend-sextend.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/uextend-sextend.clif
@@ -8,9 +8,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
 
 function %f_u_8_32(i8) -> i32 {
 block0(v0: i8):
@@ -18,9 +24,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
 
 function %f_u_8_16(i8) -> i16 {
 block0(v0: i8):
@@ -28,9 +40,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
 
 function %f_s_8_64(i8) -> i64 {
 block0(v0: i8):
@@ -38,9 +56,16 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   ret
 
 function %f_s_8_32(i8) -> i32 {
 block0(v0: i8):
@@ -48,9 +73,16 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   ret
 
 function %f_s_8_16(i8) -> i16 {
 block0(v0: i8):
@@ -58,9 +90,16 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.b a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a0, a0, 0x38
+;   ret
 
 function %f_u_16_64(i16) -> i64 {
 block0(v0: i16):
@@ -68,9 +107,16 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   ret
 
 function %f_u_16_32(i16) -> i32 {
 block0(v0: i16):
@@ -78,9 +124,16 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.h a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a0, a0, 0x30
+;   ret
 
 function %f_s_16_64(i16) -> i64 {
 block0(v0: i16):
@@ -88,9 +141,16 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a0, a0, 0x30
+;   ret
 
 function %f_s_16_32(i16) -> i32 {
 block0(v0: i16):
@@ -98,9 +158,16 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.h a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a0, a0, 0x30
+;   ret
 
 function %f_u_32_64(i32) -> i64 {
 block0(v0: i32):
@@ -108,9 +175,16 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   uext.w a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   ret
 
 function %f_s_32_64(i32) -> i64 {
 block0(v0: i32):
@@ -118,7 +192,14 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sext.w a0,a0
 ;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srai a0, a0, 0x20
+;   ret
 
diff --git a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
index ff65baa7e6..c87f584377 100644
--- a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
@@ -7,12 +7,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vaq %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vaq %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %iadd_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -20,9 +29,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   agr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agr %r2, %r3
+;   br %r14
 
 function %iadd_i64_ext32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -31,9 +46,15 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   agfr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agfr %r2, %r3
+;   br %r14
 
 function %iadd_i64_imm16(i64) -> i64 {
 block0(v0: i64):
@@ -42,9 +63,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   aghi %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   aghi %r2, 1
+;   br %r14
 
 function %iadd_i64_imm32(i64) -> i64 {
 block0(v0: i64):
@@ -53,9 +80,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   agfi %r2, 32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agfi %r2, 0x8000
+;   br %r14
 
 function %iadd_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -64,9 +97,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ag %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ag %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -75,9 +114,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   agh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agh %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -86,9 +131,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   agf %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agf %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -96,9 +147,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ar %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ar %r2, %r3
+;   br %r14
 
 function %iadd_i32_imm16(i32) -> i32 {
 block0(v0: i32):
@@ -107,9 +164,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, 1
+;   br %r14
 
 function %iadd_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -118,9 +181,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   afi %r2, 32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   afi %r2, 0x8000
+;   br %r14
 
 function %iadd_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -129,9 +198,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   a %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   a %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -140,9 +215,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ay %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ay %r2, 0x1000(%r3)
+;   br %r14
 
 function %iadd_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -151,9 +232,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ah %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ah %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -162,9 +249,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ahy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahy %r2, 0x1000(%r3)
+;   br %r14
 
 function %iadd_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -172,9 +265,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ar %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ar %r2, %r3
+;   br %r14
 
 function %iadd_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -183,9 +282,15 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, 1
+;   br %r14
 
 function %iadd_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -194,9 +299,15 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ah %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ah %r2, 0(%r3)
+;   br %r14
 
 function %iadd_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -204,9 +315,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ar %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ar %r2, %r3
+;   br %r14
 
 function %iadd_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -215,9 +332,15 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, 1
+;   br %r14
 
 function %iadd_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -226,10 +349,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   ar %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   ar %r2, %r3
+;   br %r14
 
 function %isub_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -237,12 +367,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vsq %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vsq %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %isub_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -250,9 +389,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sgr %r2, %r3
+;   br %r14
 
 function %isub_i64_ext32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -261,9 +406,15 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sgfr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sgfr %r2, %r3
+;   br %r14
 
 function %isub_i64_imm16(i64) -> i64 {
 block0(v0: i64):
@@ -272,9 +423,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   aghi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   aghi %r2, -1
+;   br %r14
 
 function %isub_i64_imm32(i64) -> i64 {
 block0(v0: i64):
@@ -283,9 +440,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   agfi %r2, -32769
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   agfi %r2, -0x8001
+;   br %r14
 
 function %isub_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -294,9 +457,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sg %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sg %r2, 0(%r3)
+;   br %r14
 
 function %isub_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -305,9 +474,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sgh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sgh %r2, 0(%r3)
+;   br %r14
 
 function %isub_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -316,9 +491,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sgf %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sgf %r2, 0(%r3)
+;   br %r14
 
 function %isub_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -326,9 +507,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sr %r2, %r3
+;   br %r14
 
 function %isub_i32_imm16(i32) -> i32 {
 block0(v0: i32):
@@ -337,9 +524,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, -1
+;   br %r14
 
 function %isub_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -348,9 +541,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   afi %r2, -32769
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   afi %r2, -0x8001
+;   br %r14
 
 function %isub_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -359,9 +558,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   s %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   s %r2, 0(%r3)
+;   br %r14
 
 function %isub_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -370,9 +575,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sy %r2, 0x1000(%r3)
+;   br %r14
 
 function %isub_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -381,9 +592,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sh %r2, 0(%r3)
+;   br %r14
 
 function %isub_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -392,9 +609,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   shy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   shy %r2, 0x1000(%r3)
+;   br %r14
 
 function %isub_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -402,9 +625,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sr %r2, %r3
+;   br %r14
 
 function %isub_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -413,9 +642,15 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, -1
+;   br %r14
 
 function %isub_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -424,9 +659,15 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sh %r2, 0(%r3)
+;   br %r14
 
 function %isub_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -434,9 +675,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sr %r2, %r3
+;   br %r14
 
 function %isub_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -445,9 +692,15 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ahi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ahi %r2, -1
+;   br %r14
 
 function %isub_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -456,10 +709,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   sr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   sr %r2, %r3
+;   br %r14
 
 function %iabs_i128(i128) -> i128 {
 block0(v0: i128):
@@ -467,6 +727,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vgbm %v4, 0
@@ -476,6 +737,17 @@ block0(v0: i128):
 ;   vsel %v20, %v6, %v1, %v18
 ;   vst %v20, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vzero %v4
+;   vsq %v6, %v4, %v1
+;   vrepg %v16, %v1, 0
+;   vchg %v18, %v4, %v16
+;   vsel %v20, %v6, %v1, %v18
+;   vst %v20, 0(%r2)
+;   br %r14
 
 function %iabs_i64(i64) -> i64 {
 block0(v0: i64):
@@ -483,9 +755,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lpgr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lpgr %r2, %r2
+;   br %r14
 
 function %iabs_i64_ext32(i32) -> i64 {
 block0(v0: i32):
@@ -494,9 +772,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lpgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lpgfr %r2, %r2
+;   br %r14
 
 function %iabs_i32(i32) -> i32 {
 block0(v0: i32):
@@ -504,9 +788,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lpr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lpr %r2, %r2
+;   br %r14
 
 function %iabs_i16(i16) -> i16 {
 block0(v0: i16):
@@ -514,10 +804,17 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lhr %r4, %r2
 ;   lpr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r4, %r2
+;   lpr %r2, %r4
+;   br %r14
 
 function %iabs_i8(i8) -> i8 {
 block0(v0: i8):
@@ -525,10 +822,17 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lbr %r4, %r2
 ;   lpr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r4, %r2
+;   lpr %r2, %r4
+;   br %r14
 
 function %ineg_i128(i128) -> i128 {
 block0(v0: i128):
@@ -536,12 +840,21 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vgbm %v4, 0
 ;   vsq %v6, %v4, %v1
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vzero %v4
+;   vsq %v6, %v4, %v1
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %ineg_i64(i64) -> i64 {
 block0(v0: i64):
@@ -549,9 +862,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcgr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcgr %r2, %r2
+;   br %r14
 
 function %ineg_i64_ext32(i32) -> i64 {
 block0(v0: i32):
@@ -560,9 +879,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcgfr %r2, %r2
+;   br %r14
 
 function %ineg_i32(i32) -> i32 {
 block0(v0: i32):
@@ -570,9 +895,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r2, %r2
+;   br %r14
 
 function %ineg_i16(i16) -> i16 {
 block0(v0: i16):
@@ -580,9 +911,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r2, %r2
+;   br %r14
 
 function %ineg_i8(i8) -> i8 {
 block0(v0: i8):
@@ -590,9 +927,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r2, %r2
+;   br %r14
 
 function %imul_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -600,6 +943,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ;   stmg %r7, %r15, 56(%r15)
 ; block0:
 ;   lgr %r10, %r2
@@ -621,6 +965,29 @@ block0(v0: i128, v1: i128):
 ;   vst %v5, 0(%r2)
 ;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r7, %r15, 0x38(%r15)
+; block0: ; offset 0x6
+;   lgr %r10, %r2
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   lgdr %r4, %f1
+;   vlgvg %r5, %v1, 1
+;   lgdr %r7, %f3
+;   vlgvg %r9, %v3, 1
+;   lgr %r3, %r5
+;   mlgr %r2, %r9
+;   lgr %r8, %r2
+;   msgrkc %r2, %r5, %r7
+;   msgrkc %r5, %r4, %r9
+;   agrk %r4, %r2, %r8
+;   agr %r5, %r4
+;   vlvgp %v5, %r5, %r3
+;   lgr %r2, %r10
+;   vst %v5, 0(%r2)
+;   lmg %r7, %r15, 0x38(%r15)
+;   br %r14
 
 function %imul_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -628,9 +995,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msgr %r2, %r3
+;   br %r14
 
 function %imul_i64_imm16(i64) -> i64 {
 block0(v0: i64):
@@ -639,9 +1012,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mghi %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mghi %r2, 3
+;   br %r14
 
 function %imul_i64_imm32(i64) -> i64 {
 block0(v0: i64):
@@ -650,9 +1029,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msgfi %r2, 32769
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msgfi %r2, 0x8001
+;   br %r14
 
 function %imul_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -661,9 +1046,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   msg %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msg %r2, 0(%r3)
+;   br %r14
 
 function %imul_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -672,9 +1063,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mgh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mgh %r2, 0(%r3)
+;   br %r14
 
 function %imul_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -683,9 +1080,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   msgf %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msgf %r2, 0(%r3)
+;   br %r14
 
 function %imul_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -693,9 +1096,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msr %r2, %r3
+;   br %r14
 
 function %imul_i32_imm16(i32) -> i32 {
 block0(v0: i32):
@@ -704,9 +1113,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mhi %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mhi %r2, 3
+;   br %r14
 
 function %imul_i32_imm32(i32) -> i32 {
 block0(v0: i32):
@@ -715,9 +1130,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msfi %r2, 32769
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msfi %r2, 0x8001
+;   br %r14
 
 function %imul_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -726,9 +1147,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ms %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ms %r2, 0(%r3)
+;   br %r14
 
 function %imul_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -737,9 +1164,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   msy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msy %r2, 0x1000(%r3)
+;   br %r14
 
 function %imul_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -748,9 +1181,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mh %r2, 0(%r3)
+;   br %r14
 
 function %imul_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -759,9 +1198,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mhy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mhy %r2, 0x1000(%r3)
+;   br %r14
 
 function %imul_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -769,9 +1214,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msr %r2, %r3
+;   br %r14
 
 function %imul_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -780,9 +1231,15 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mhi %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mhi %r2, 3
+;   br %r14
 
 function %imul_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -791,9 +1248,15 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   mh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mh %r2, 0(%r3)
+;   br %r14
 
 function %imul_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -801,9 +1264,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   msr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   msr %r2, %r3
+;   br %r14
 
 function %imul_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -812,9 +1281,15 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mhi %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mhi %r2, 3
+;   br %r14
 
 function %imul_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -823,10 +1298,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   msr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   msr %r2, %r3
+;   br %r14
 
 function %umulhi_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -834,11 +1316,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   lgr %r3, %r2
 ;   mlgr %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   lgr %r3, %r2
+;   mlgr %r2, %r5
+;   br %r14
 
 function %umulhi_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -846,12 +1336,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r5, %r2
 ;   llgfr %r3, %r3
 ;   msgr %r5, %r3
 ;   srlg %r2, %r5, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r5, %r2
+;   llgfr %r3, %r3
+;   msgr %r5, %r3
+;   srlg %r2, %r5, 0x20
+;   br %r14
 
 function %umulhi_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -859,12 +1358,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   llhr %r3, %r3
 ;   msr %r5, %r3
 ;   srlk %r2, %r5, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   llhr %r3, %r3
+;   msr %r5, %r3
+;   srlk %r2, %r5, 0x10
+;   br %r14
 
 function %umulhi_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -872,12 +1380,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   llcr %r3, %r3
 ;   msr %r5, %r3
 ;   srlk %r2, %r5, 8
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   llcr %r3, %r3
+;   msr %r5, %r3
+;   srlk %r2, %r5, 8
+;   br %r14
 
 function %smulhi_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -885,9 +1402,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mgrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mgrk %r2, %r2, %r3
+;   br %r14
 
 function %smulhi_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -895,12 +1418,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r5, %r2
 ;   lgfr %r3, %r3
 ;   msgr %r5, %r3
 ;   srag %r2, %r5, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r5, %r2
+;   lgfr %r3, %r3
+;   msgr %r5, %r3
+;   srag %r2, %r5, 0x20
+;   br %r14
 
 function %smulhi_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -908,12 +1440,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   lhr %r3, %r3
 ;   msr %r5, %r3
 ;   srak %r2, %r5, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   lhr %r3, %r3
+;   msr %r5, %r3
+;   srak %r2, %r5, 0x10
+;   br %r14
 
 function %smulhi_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -921,12 +1462,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   lbr %r3, %r3
 ;   msr %r5, %r3
 ;   srak %r2, %r5, 8
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   lbr %r3, %r3
+;   msr %r5, %r3
+;   srak %r2, %r5, 8
+;   br %r14
 
 function %sdiv_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -934,6 +1484,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llihf %r4, 2147483647
 ;   iilf %r4, 4294967295
@@ -945,6 +1496,19 @@ block0(v0: i64, v1: i64):
 ;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llihf %r4, 0x7fffffff
+;   iilf %r4, 0xffffffff
+;   xgrk %r5, %r4, %r2
+;   ngrk %r4, %r5, %r3
+;   cgite %r4, -1 ; trap: int_ovf
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   dsgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -953,12 +1517,21 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lghi %r4, 2
 ;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lghi %r4, 2
+;   dsgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -966,6 +1539,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   stmg %r7, %r15, 56(%r15)
 ; block0:
 ;   lgr %r7, %r3
@@ -979,6 +1553,21 @@ block0(v0: i32, v1: i32):
 ;   lgr %r2, %r3
 ;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r7, %r15, 0x38(%r15)
+; block0: ; offset 0x6
+;   lgr %r7, %r3
+;   lgfr %r3, %r2
+;   iilf %r4, 0x7fffffff
+;   xrk %r5, %r4, %r3
+;   lgr %r4, %r7
+;   nr %r5, %r4
+;   cite %r5, -1 ; trap: int_ovf
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r7, %r15, 0x38(%r15)
+;   br %r14
 
 function %sdiv_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -987,12 +1576,21 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -1000,6 +1598,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghr %r5, %r2
 ;   lgr %r2, %r5
@@ -1012,6 +1611,20 @@ block0(v0: i16, v1: i16):
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r5, %r2
+;   lgr %r2, %r5
+;   lhr %r4, %r3
+;   lhi %r5, 0x7fff
+;   lgr %r3, %r2
+;   xr %r5, %r3
+;   nr %r5, %r4
+;   cite %r5, -1 ; trap: int_ovf
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -1020,12 +1633,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -1033,6 +1655,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r5, %r2
 ;   lgr %r2, %r5
@@ -1045,6 +1668,20 @@ block0(v0: i8, v1: i8):
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r5, %r2
+;   lgr %r2, %r5
+;   lbr %r4, %r3
+;   lhi %r5, 0x7f
+;   lgr %r3, %r2
+;   xr %r5, %r3
+;   nr %r5, %r4
+;   cite %r5, -1 ; trap: int_ovf
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -1053,12 +1690,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -1066,6 +1712,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lgr %r3, %r2
@@ -1073,6 +1720,15 @@ block0(v0: i64, v1: i64):
 ;   dlgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   lghi %r2, 0
+;   dlgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -1081,6 +1737,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lghi %r2, 0
@@ -1088,6 +1745,15 @@ block0(v0: i64):
 ;   dlgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lghi %r2, 0
+;   lghi %r4, 2
+;   dlgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -1095,6 +1761,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lgr %r3, %r2
@@ -1102,6 +1769,15 @@ block0(v0: i32, v1: i32):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   lhi %r2, 0
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -1110,6 +1786,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lhi %r2, 0
@@ -1117,6 +1794,15 @@ block0(v0: i32):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lhi %r2, 0
+;   lhi %r4, 2
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -1124,6 +1810,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -1137,6 +1824,21 @@ block0(v0: i16, v1: i16):
 ;   lgr %r2, %r3
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llhr %r3, %r2
+;   lgr %r5, %r4
+;   llhr %r5, %r5
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %udiv_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -1145,6 +1847,7 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 0
 ;   lgr %r5, %r4
@@ -1154,6 +1857,17 @@ block0(v0: i16):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0
+;   lgr %r5, %r4
+;   llhr %r3, %r2
+;   lhi %r4, 2
+;   lgr %r2, %r5
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -1161,6 +1875,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -1174,6 +1889,21 @@ block0(v0: i8, v1: i8):
 ;   lgr %r2, %r3
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llcr %r3, %r2
+;   lgr %r5, %r4
+;   llcr %r5, %r5
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %udiv_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -1182,6 +1912,7 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 0
 ;   lgr %r5, %r4
@@ -1191,6 +1922,17 @@ block0(v0: i8):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0
+;   lgr %r5, %r4
+;   llcr %r3, %r2
+;   lhi %r4, 2
+;   lgr %r2, %r5
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %srem_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -1198,6 +1940,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r3, -1
 ;   lgr %r4, %r3
@@ -1205,6 +1948,15 @@ block0(v0: i64, v1: i64):
 ;   locghie %r3, 0
 ;   dsgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r3, -1
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   locghie %r3, 0
+;   dsgr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %srem_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -1212,12 +1964,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   lgfr %r3, %r2
 ;   lgr %r2, %r5
 ;   dsgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   lgfr %r3, %r2
+;   lgr %r2, %r5
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   br %r14
 
 function %srem_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -1225,12 +1986,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lghr %r3, %r2
 ;   lhr %r4, %r4
 ;   dsgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lghr %r3, %r2
+;   lhr %r4, %r4
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %srem_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -1238,12 +2008,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lgbr %r3, %r2
 ;   lbr %r4, %r4
 ;   dsgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lgbr %r3, %r2
+;   lbr %r4, %r4
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %urem_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -1251,12 +2030,21 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lghi %r2, 0
 ;   dlgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   lghi %r2, 0
+;   dlgr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %urem_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -1264,12 +2052,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lhi %r2, 0
 ;   dlr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   lhi %r2, 0
+;   dlr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %urem_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -1277,6 +2074,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -1289,6 +2087,20 @@ block0(v0: i16, v1: i16):
 ;   dlr %r2, %r5
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llhr %r3, %r2
+;   lgr %r5, %r4
+;   llhr %r5, %r5
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %urem_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -1296,6 +2108,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -1308,4 +2121,18 @@ block0(v0: i8, v1: i8):
 ;   dlr %r2, %r5
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llcr %r3, %r2
+;   lgr %r5, %r4
+;   llcr %r5, %r5
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif
index 88d609fe52..fc1fc1686a 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif
@@ -11,12 +11,21 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r5, %r2
 ;   lrvgr %r2, %r3
 ;   csg %r5, %r2, 0(%r4)
 ;   lrvgr %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r5, %r2
+;   lrvgr %r2, %r3
+;   csg %r5, %r2, 0(%r4)
+;   lrvgr %r2, %r5
+;   br %r14
 
 function %atomic_cas_i32(i32, i32, i64) -> i32 {
 block0(v0: i32, v1: i32, v2: i64):
@@ -24,12 +33,21 @@ block0(v0: i32, v1: i32, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r5, %r2
 ;   lrvr %r2, %r3
 ;   cs %r5, %r2, 0(%r4)
 ;   lrvr %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r5, %r2
+;   lrvr %r2, %r3
+;   cs %r5, %r2, 0(%r4)
+;   lrvr %r2, %r5
+;   br %r14
 
 function %atomic_cas_i16(i64, i16, i16, i64) -> i16 {
 block0(v0: i64, v1: i16, v2: i16, v3: i64):
@@ -37,6 +55,7 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
   return v4
 }
 
+; VCode:
 ;   stmg %r11, %r15, 88(%r15)
 ; block0:
 ;   sllk %r11, %r5, 3
@@ -49,6 +68,26 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
 ;   lrvr %r2, %r5
 ;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r11, %r15, 0x58(%r15)
+; block0: ; offset 0x6
+;   sllk %r11, %r5, 3
+;   nill %r5, 0xfffc
+;   lrvr %r2, %r3
+;   lrvr %r3, %r4
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0x10(%r11)
+;   rxsbg %r1, %r2, 0xb0, 0x40, 0x30
+;   jglh 0x44
+;   risbgn %r1, %r3, 0x30, 0x40, 0x30
+;   rll %r1, %r1, 0x10(%r11)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1c
+;   rll %r5, %r0, 0(%r11)
+;   lrvr %r2, %r5
+;   lmg %r11, %r15, 0x58(%r15)
+;   br %r14
 
 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 {
 block0(v0: i64, v1: i8, v2: i8, v3: i64):
@@ -56,6 +95,7 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
   return v4
 }
 
+; VCode:
 ;   stmg %r10, %r15, 80(%r15)
 ; block0:
 ;   lgr %r10, %r3
@@ -67,4 +107,23 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
 ;   rll %r2, %r0, 8(%r3)
 ;   lmg %r10, %r15, 80(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r10, %r15, 0x50(%r15)
+; block0: ; offset 0x6
+;   lgr %r10, %r3
+;   sllk %r3, %r5, 3
+;   nill %r5, 0xfffc
+;   lcr %r2, %r3
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r3)
+;   rxsbg %r1, %r10, 0xa0, 0x28, 0x18
+;   jglh 0x42
+;   risbgn %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r3)
+;   lmg %r10, %r15, 0x50(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif
index 32f2e4b765..78b80aaa41 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif
@@ -11,9 +11,15 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   csg %r2, %r3, 0(%r4)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   csg %r2, %r3, 0(%r4)
+;   br %r14
 
 function %atomic_cas_i32(i32, i32, i64) -> i32 {
 block0(v0: i32, v1: i32, v2: i64):
@@ -21,9 +27,15 @@ block0(v0: i32, v1: i32, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cs %r2, %r3, 0(%r4)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cs %r2, %r3, 0(%r4)
+;   br %r14
 
 function %atomic_cas_i16(i64, i16, i16, i64) -> i16 {
 block0(v0: i64, v1: i16, v2: i16, v3: i64):
@@ -31,6 +43,7 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
   return v4
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   sllk %r3, %r5, 3
@@ -39,6 +52,22 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
 ;   0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r2, 160, 48, 16 ; jglh 1f ; risbgn %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   sllk %r3, %r5, 3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r3)
+;   rxsbg %r1, %r2, 0xa0, 0x30, 0x10
+;   jglh 0x3a
+;   risbgn %r1, %r4, 0x20, 0x30, 0x10
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r3)
+;   br %r14
 
 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 {
 block0(v0: i64, v1: i8, v2: i8, v3: i64):
@@ -46,6 +75,7 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
   return v4
 }
 
+; VCode:
 ;   stmg %r10, %r15, 80(%r15)
 ; block0:
 ;   lgr %r10, %r3
@@ -57,4 +87,23 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
 ;   rll %r2, %r0, 8(%r3)
 ;   lmg %r10, %r15, 80(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r10, %r15, 0x50(%r15)
+; block0: ; offset 0x6
+;   lgr %r10, %r3
+;   sllk %r3, %r5, 3
+;   nill %r5, 0xfffc
+;   lcr %r2, %r3
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r3)
+;   rxsbg %r1, %r10, 0xa0, 0x28, 0x18
+;   jglh 0x42
+;   risbgn %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r3)
+;   lmg %r10, %r15, 0x50(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_load-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_load-little.clif
index 539fee2c53..b5e5760239 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_load-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_load-little.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -19,9 +25,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvg %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvg %r2, 0(%r1)
+;   br %r14
 
 function %atomic_load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -29,9 +42,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrv %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -41,9 +60,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrv %r2, 0(%r1)
+;   br %r14
 
 function %atomic_load_i16(i64) -> i16 {
 block0(v0: i64):
@@ -51,9 +77,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i16_sym() -> i16 {
   gv0 = symbol colocated %sym
@@ -63,9 +95,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   br %r14
 
 function %atomic_load_i8(i64) -> i8 {
 block0(v0: i64):
@@ -73,7 +112,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_load.clif b/cranelift/filetests/filetests/isa/s390x/atomic_load.clif
index dfec456e98..484c2d7724 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_load.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_load.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lg %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -19,9 +25,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %atomic_load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -29,9 +41,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   l %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -41,9 +59,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %atomic_load_i16(i64) -> i16 {
 block0(v0: i64):
@@ -51,9 +75,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r2, 0(%r2)
+;   br %r14
 
 function %atomic_load_i16_sym() -> i16 {
   gv0 = symbol colocated %sym
@@ -63,9 +93,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llhrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %atomic_load_i8(i64) -> i8 {
 block0(v0: i64):
@@ -73,7 +109,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif
index 730d0c1824..919d69a831 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif
@@ -7,11 +7,23 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: nngrk %r1, %r0, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   .byte 0xb9, 0x64
+;   sth %r1, 0xb01(%r14)
+;   lper %f0, %f0
+;   .byte 0x00, 0x30
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -19,11 +31,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: nnrk %r1, %r0, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   .byte 0xb9, 0x74
+;   sth %r1, 0xa01(%r11)
+;   lper %f0, %f0
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -31,6 +54,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -39,6 +63,21 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x30, 0x10
+;   xilf %r1, 0xffff0000
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -46,6 +85,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -55,6 +95,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   xilf %r1, 0xff000000
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -62,12 +118,24 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
 ;   0: nngrk %r1, %r0, %r2 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   lg %r0, 0(%r3)
+;   .byte 0xb9, 0x64
+;   lpdr %f1, %f0
+;   csg %r0, %r1, 0(%r3)
+;   jglh 0xa
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -75,12 +143,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
 ;   0: nnrk %r1, %r0, %r2 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   l %r0, 0(%r3)
+;   .byte 0xb9, 0x74
+;   lpdr %f1, %f0
+;   cs %r0, %r1, 0(%r3)
+;   jglh 8
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -88,6 +168,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -99,6 +180,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   rnsbg %r1, %r3, 0x30, 0x40, 0x30
+;   xilf %r1, 0xffff
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -106,6 +205,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -115,4 +215,20 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   xilf %r1, 0xff000000
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif
index 14135aeb0c..2d2c92246e 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif
@@ -11,12 +11,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
 ;   0: csg %r0, %r2, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   lg %r0, 0(%r3)
+;   csg %r0, %r2, 0(%r3)
+;   jglh 0xa
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_xchg_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -24,12 +34,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
 ;   0: cs %r0, %r2, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   l %r0, 0(%r3)
+;   cs %r0, %r2, 0(%r3)
+;   jglh 8
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_xchg_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -37,6 +57,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -48,6 +69,23 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   risbgn %r1, %r3, 0x30, 0x40, 0x30
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -55,6 +93,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -64,6 +103,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   risbgn %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_add_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -71,11 +125,23 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; agr %r1, %r4 ; lrvgr %r1, %r1 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   agr %r1, %r4
+;   lrvgr %r1, %r1
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_add_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -83,11 +149,23 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; ar %r1, %r4 ; lrvr %r1, %r1 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   ar %r1, %r4
+;   lrvr %r1, %r1
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_add_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -95,6 +173,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -106,6 +185,25 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   ar %r1, %r3
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_add_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -113,6 +211,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -123,6 +222,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   ar %r1, %r3
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_sub_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -130,11 +245,23 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; sgr %r1, %r4 ; lrvgr %r1, %r1 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   sgr %r1, %r4
+;   lrvgr %r1, %r1
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_sub_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -142,11 +269,23 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; sr %r1, %r4 ; lrvr %r1, %r1 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   sr %r1, %r4
+;   lrvr %r1, %r1
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_sub_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -154,6 +293,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -165,6 +305,25 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   sr %r1, %r3
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_sub_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -172,6 +331,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -182,6 +342,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   sr %r1, %r3
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_and_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -189,11 +365,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   lang %r4, %r2, 0(%r3)
 ;   lrvgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   lang %r4, %r2, 0(%r3)
+;   lrvgr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_and_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -201,11 +385,19 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   lan %r4, %r2, 0(%r3)
 ;   lrvr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   lan %r4, %r2, 0(%r3)
+;   lrvr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_and_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -213,6 +405,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -224,6 +417,23 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   rnsbg %r1, %r3, 0x30, 0x40, 0x30
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -231,6 +441,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -240,6 +451,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_or_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -247,11 +473,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   laog %r4, %r2, 0(%r3)
 ;   lrvgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   laog %r4, %r2, 0(%r3)
+;   lrvgr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_or_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -259,11 +493,19 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   lao %r4, %r2, 0(%r3)
 ;   lrvr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   lao %r4, %r2, 0(%r3)
+;   lrvr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_or_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -271,6 +513,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -282,6 +525,23 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   rosbg %r1, %r3, 0x30, 0x40, 0x30
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -289,6 +549,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -298,6 +559,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rosbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_xor_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -305,11 +581,19 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   laxg %r4, %r2, 0(%r3)
 ;   lrvgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   laxg %r4, %r2, 0(%r3)
+;   lrvgr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_xor_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -317,11 +601,19 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   lax %r4, %r2, 0(%r3)
 ;   lrvr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   lax %r4, %r2, 0(%r3)
+;   lrvr %r2, %r4
+;   br %r14
 
 function %atomic_rmw_xor_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -329,6 +621,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -340,6 +633,23 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   rxsbg %r1, %r3, 0x30, 0x40, 0x30
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -347,6 +657,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -356,6 +667,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rxsbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -363,12 +689,25 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
 ;   0: ngrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r4
+;   lg %r0, 0(%r3)
+;   ngrk %r1, %r0, %r2
+;   xilf %r1, 0xffffffff
+;   xihf %r1, 0xffffffff
+;   csg %r0, %r1, 0(%r3)
+;   jglh 0xa
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -376,12 +715,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
 ;   0: nrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r4
+;   l %r0, 0(%r3)
+;   nrk %r1, %r0, %r2
+;   xilf %r1, 0xffffffff
+;   cs %r0, %r1, 0(%r3)
+;   jglh 8
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -389,6 +740,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -400,6 +752,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   lrvr %r3, %r5
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   rnsbg %r1, %r3, 0x30, 0x40, 0x30
+;   xilf %r1, 0xffff
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1a
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -407,6 +777,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -416,6 +787,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   xilf %r1, 0xff000000
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -423,11 +810,24 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; cgr %r4, %r1 ; jgnl 1f ; lrvgr %r1, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   cgr %r4, %r1
+;   jgnl 0x24
+;   lrvgr %r1, %r4
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smin_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -435,11 +835,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; cr %r4, %r1 ; jgnl 1f ; lrvr %r1, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   cr %r4, %r1
+;   jgnl 0x1e
+;   lrvr %r1, %r4
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smin_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -447,6 +860,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -458,6 +872,27 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   cr %r3, %r1
+;   jgnl 0x48
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_smin_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -465,6 +900,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -475,6 +911,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnl 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -482,11 +936,24 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; cgr %r4, %r1 ; jgnh 1f ; lrvgr %r1, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   cgr %r4, %r1
+;   jgnh 0x24
+;   lrvgr %r1, %r4
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smax_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -494,11 +961,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; cr %r4, %r1 ; jgnh 1f ; lrvr %r1, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   cr %r4, %r1
+;   jgnh 0x1e
+;   lrvr %r1, %r4
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smax_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -506,6 +986,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -517,6 +998,27 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   cr %r3, %r1
+;   jgnh 0x48
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_smax_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -524,6 +1026,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -534,6 +1037,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnh 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -541,11 +1062,24 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; clgr %r4, %r1 ; jgnl 1f ; lrvgr %r1, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   clgr %r4, %r1
+;   jgnl 0x24
+;   lrvgr %r1, %r4
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umin_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -553,11 +1087,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; clr %r4, %r1 ; jgnl 1f ; lrvr %r1, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   clr %r4, %r1
+;   jgnl 0x1e
+;   lrvr %r1, %r4
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umin_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -565,6 +1112,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -576,6 +1124,27 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   clr %r3, %r1
+;   jgnl 0x48
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_umin_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -583,6 +1152,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -593,6 +1163,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnl 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -600,11 +1188,24 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: lrvgr %r1, %r0 ; clgr %r4, %r1 ; jgnh 1f ; lrvgr %r1, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   lrvgr %r1, %r0
+;   clgr %r4, %r1
+;   jgnh 0x24
+;   lrvgr %r1, %r4
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lrvgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umax_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -612,11 +1213,24 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: lrvr %r1, %r0 ; clr %r4, %r1 ; jgnh 1f ; lrvr %r1, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   lrvr %r1, %r0
+;   clr %r4, %r1
+;   jgnh 0x1e
+;   lrvr %r1, %r4
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lrvr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umax_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -624,6 +1238,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -635,6 +1250,27 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   rll %r2, %r0, 0(%r2)
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0x10(%r2)
+;   lrvr %r1, %r1
+;   clr %r3, %r1
+;   jgnh 0x48
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   lrvr %r1, %r1
+;   rll %r1, %r1, 0x10(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0(%r2)
+;   lrvr %r2, %r2
+;   br %r14
 
 function %atomic_rmw_umax_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -642,6 +1278,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -652,4 +1289,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnh 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif
index 4837175f09..b517c6661a 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif
@@ -11,11 +11,20 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   csg %r0, %r4, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_xchg_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -23,11 +32,20 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   cs %r0, %r4, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_xchg_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -35,6 +53,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -43,6 +62,20 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   risbgn %r1, %r4, 0x20, 0x30, 0x10
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -50,6 +83,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -59,6 +93,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   risbgn %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_add_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -66,9 +115,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   laag %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   laag %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_add_i32(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -76,9 +131,15 @@ block0(v0: i64, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   laa %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   laa %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_add_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -86,6 +147,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -96,6 +158,22 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   ar %r1, %r3
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_add_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -103,6 +181,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -113,6 +192,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   ar %r1, %r3
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_sub_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -120,10 +215,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcgr %r5, %r3
 ;   laag %r2, %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcgr %r5, %r3
+;   laag %r2, %r5, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_sub_i32(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -131,10 +233,17 @@ block0(v0: i64, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r3
 ;   laa %r2, %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r3
+;   laa %r2, %r5, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_sub_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -142,6 +251,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -152,6 +262,22 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   sr %r1, %r3
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_sub_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -159,6 +285,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -169,6 +296,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   sr %r1, %r3
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_and_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -176,9 +319,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lang %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lang %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_and_i32(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -186,9 +335,15 @@ block0(v0: i64, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lan %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lan %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_and_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -196,6 +351,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -204,6 +360,20 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x30, 0x10
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -211,6 +381,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -220,6 +391,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_or_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -227,9 +413,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   laog %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   laog %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_or_i32(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -237,9 +429,15 @@ block0(v0: i64, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lao %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lao %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_or_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -247,6 +445,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -255,6 +454,20 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rosbg %r1, %r4, 0x20, 0x30, 0x10
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -262,6 +475,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -271,6 +485,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rosbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_xor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -278,9 +507,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   laxg %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   laxg %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_xor_i32(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -288,9 +523,15 @@ block0(v0: i64, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lax %r2, %r3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lax %r2, %r3, 0(%r2)
+;   br %r14
 
 function %atomic_rmw_xor_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -298,6 +539,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -306,6 +548,20 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rxsbg %r1, %r4, 0x20, 0x30, 0x10
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -313,6 +569,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -322,6 +579,21 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rxsbg %r1, %r4, 0x20, 0x28, 0x18
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -329,11 +601,23 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: ngrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   ngrk %r1, %r0, %r4
+;   xilf %r1, 0xffffffff
+;   xihf %r1, 0xffffffff
+;   csg %r0, %r1, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -341,11 +625,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: nrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   nrk %r1, %r0, %r4
+;   xilf %r1, 0xffffffff
+;   cs %r0, %r1, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_nand_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -353,6 +648,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -361,6 +657,21 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x30, 0x10
+;   xilf %r1, 0xffff0000
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x12
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -368,6 +679,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -377,6 +689,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   lcr %r3, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   rnsbg %r1, %r4, 0x20, 0x28, 0x18
+;   xilf %r1, 0xff000000
+;   rll %r1, %r1, 0(%r3)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x14
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -384,11 +712,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: cgr %r4, %r0 ; jgnl 1f ; csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   cgr %r4, %r0
+;   jgnl 0x1c
+;   csg %r0, %r4, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smin_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -396,11 +735,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: cr %r4, %r0 ; jgnl 1f ; cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   cr %r4, %r0
+;   jgnl 0x16
+;   cs %r0, %r4, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smin_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -408,6 +758,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -418,6 +769,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnl 0x40
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_smin_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -425,6 +794,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -435,6 +805,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnl 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -442,11 +830,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: cgr %r4, %r0 ; jgnh 1f ; csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   cgr %r4, %r0
+;   jgnh 0x1c
+;   csg %r0, %r4, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smax_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -454,11 +853,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: cr %r4, %r0 ; jgnh 1f ; cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   cr %r4, %r0
+;   jgnh 0x16
+;   cs %r0, %r4, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_smax_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -466,6 +876,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -476,6 +887,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnh 0x40
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_smax_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -483,6 +912,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -493,6 +923,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   cr %r3, %r1
+;   jgnh 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -500,11 +948,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: clgr %r4, %r0 ; jgnl 1f ; csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   clgr %r4, %r0
+;   jgnl 0x1c
+;   csg %r0, %r4, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umin_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -512,11 +971,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: clr %r4, %r0 ; jgnl 1f ; cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   clr %r4, %r0
+;   jgnl 0x16
+;   cs %r0, %r4, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umin_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -524,6 +994,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -534,6 +1005,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnl 0x40
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_umin_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -541,6 +1030,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -551,6 +1041,24 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnl 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -558,11 +1066,22 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lg %r0, 0(%r3)
 ;   0: clgr %r4, %r0 ; jgnh 1f ; csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r0, 0(%r3)
+;   clgr %r4, %r0
+;   jgnh 0x1c
+;   csg %r0, %r4, 0(%r3)
+;   jglh 6
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umax_i32(i64, i64, i32) -> i32 {
 block0(v0: i64, v1: i64, v2: i32):
@@ -570,11 +1089,22 @@ block0(v0: i64, v1: i64, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   l %r0, 0(%r3)
 ;   0: clr %r4, %r0 ; jgnh 1f ; cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
 ;   lgr %r2, %r0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r0, 0(%r3)
+;   clr %r4, %r0
+;   jgnh 0x16
+;   cs %r0, %r4, 0(%r3)
+;   jglh 4
+;   lgr %r2, %r0
+;   br %r14
 
 function %atomic_rmw_umax_i16(i64, i64, i16) -> i16 {
 block0(v0: i64, v1: i64, v2: i16):
@@ -582,6 +1112,7 @@ block0(v0: i64, v1: i64, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
@@ -592,6 +1123,24 @@ block0(v0: i64, v1: i64, v2: i16):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r4
+;   sllk %r2, %r3, 3
+;   lgr %r4, %r3
+;   nill %r4, 0xfffc
+;   sllk %r3, %r5, 0x10
+;   l %r0, 0(%r4)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnh 0x40
+;   risbgn %r1, %r3, 0x20, 0x30, 0
+;   rll %r1, %r1, 0(%r2)
+;   cs %r0, %r1, 0(%r4)
+;   jglh 0x1c
+;   rll %r2, %r0, 0x10(%r2)
+;   br %r14
 
 function %atomic_rmw_umax_i8(i64, i64, i8) -> i8 {
 block0(v0: i64, v1: i64, v2: i8):
@@ -599,6 +1148,7 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
@@ -609,4 +1159,22 @@ block0(v0: i64, v1: i64, v2: i8):
 ;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r3, 3
+;   lgr %r5, %r3
+;   nill %r5, 0xfffc
+;   sllk %r3, %r4, 0x18
+;   lcr %r4, %r2
+;   l %r0, 0(%r5)
+;   rll %r1, %r0, 0(%r2)
+;   clr %r3, %r1
+;   jgnh 0x3e
+;   risbgn %r1, %r3, 0x20, 0x28, 0
+;   rll %r1, %r1, 0(%r4)
+;   cs %r0, %r1, 0(%r5)
+;   jglh 0x1a
+;   rll %r2, %r0, 8(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_store-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_store-little.clif
index 8e9fd78c9a..dee456038e 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_store-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_store-little.clif
@@ -7,10 +7,17 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvg %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvg %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -20,10 +27,18 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvg %r2, 0(%r1)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvg %r2, 0(%r1)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i64(i64) {
 block0(v0: i64):
@@ -32,11 +47,19 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lghi %r4, 12345
 ;   strvg %r4, 0(%r2)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r4, 0x3039
+;   strvg %r4, 0(%r2)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -44,10 +67,17 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strv %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strv %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -57,10 +87,18 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strv %r2, 0(%r1)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strv %r2, 0(%r1)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i32(i64) {
 block0(v0: i64):
@@ -69,11 +107,19 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 12345
 ;   strv %r4, 0(%r2)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0x3039
+;   strv %r4, 0(%r2)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -81,10 +127,17 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvh %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvh %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i16_sym(i16) {
   gv0 = symbol colocated %sym
@@ -94,10 +147,18 @@ block0(v0: i16):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvh %r2, 0(%r1)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i16(i64) {
 block0(v0: i64):
@@ -106,10 +167,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 14640
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3930
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i8(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -117,10 +185,17 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i8(i64) {
 block0(v0: i64):
@@ -129,8 +204,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   bnor %r0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_store.clif b/cranelift/filetests/filetests/isa/s390x/atomic_store.clif
index 9c2944745c..0bc3a46a05 100644
--- a/cranelift/filetests/filetests/isa/s390x/atomic_store.clif
+++ b/cranelift/filetests/filetests/isa/s390x/atomic_store.clif
@@ -7,10 +7,17 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stg %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stg %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -20,10 +27,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stgrl %r2, %sym + 0
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i64(i64) {
 block0(v0: i64):
@@ -32,10 +46,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvghi 0(%r2), 12345
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvghi 0(%r2), 0x3039
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -43,10 +64,17 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   st %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   st %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -56,10 +84,17 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   strl %r2, %sym + 0
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i32(i64) {
 block0(v0: i64):
@@ -68,10 +103,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhi 0(%r2), 12345
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhi 0(%r2), 0x3039
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -79,10 +121,17 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sth %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sth %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i16_sym(i16) {
   gv0 = symbol colocated %sym
@@ -92,10 +141,17 @@ block0(v0: i16):
   return
 }
 
+; VCode:
 ; block0:
 ;   sthrl %r2, %sym + 0
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sthrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i16(i64) {
 block0(v0: i64):
@@ -104,10 +160,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 12345
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3039
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_i8(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -115,10 +178,17 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   bnor %r0
+;   br %r14
 
 function %atomic_store_imm_i8(i64) {
 block0(v0: i64):
@@ -127,8 +197,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   bnor %r0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bitcast.clif b/cranelift/filetests/filetests/isa/s390x/bitcast.clif
index c247be51a9..176e23a568 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitcast.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitcast.clif
@@ -9,8 +9,13 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i16_i16(i16) -> i16 {
 block0(v0: i16):
@@ -18,8 +23,13 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i32_i32(i32) -> i32 {
 block0(v0: i32):
@@ -27,8 +37,13 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64_i64(i64) -> i64 {
 block0(v0: i64):
@@ -36,8 +51,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i128_i128(i128) -> i128 {
 block0(v0: i128):
@@ -45,10 +65,17 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vst %v1, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vst %v1, 0(%r2)
+;   br %r14
 
 function %bitcast_r64_i64(r64) -> i64 {
 block0(v0: r64):
@@ -56,8 +83,13 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64_r64(i64) -> r64 {
 block0(v0: i64):
@@ -65,8 +97,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_r64_r64(r64) -> r64 {
 block0(v0: r64):
@@ -74,6 +111,11 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif b/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif
index 9090f30e4e..023362e58a 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif
@@ -11,9 +11,16 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r2, %r2, 8
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xe1
+;   .byte 0x80, 0x22
+;   br %r14
 
 function %popcnt_i32(i32) -> i32 {
 block0(v0: i32):
@@ -21,10 +28,18 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r4, %r2
 ;   popcnt %r2, %r4, 8
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r4, %r2
+;   .byte 0xb9, 0xe1
+;   .byte 0x80, 0x24
+;   br %r14
 
 function %popcnt_i16(i16) -> i16 {
 block0(v0: i16):
@@ -32,10 +47,18 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r4, %r2
 ;   popcnt %r2, %r4, 8
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r4, %r2
+;   .byte 0xb9, 0xe1
+;   .byte 0x80, 0x24
+;   br %r14
 
 function %popcnt_i8(i8) -> i8 {
 block0(v0: i8):
@@ -43,7 +66,13 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   popcnt %r2, %r2
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bitops-optimized.clif b/cranelift/filetests/filetests/isa/s390x/bitops-optimized.clif
index 2f2ad86908..7bad63642f 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitops-optimized.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitops-optimized.clif
@@ -8,9 +8,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ncrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xf5
+;   lper %f2, %f2
+;   br %r14
 
 function %band_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -19,9 +26,16 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ncrk %r2, %r3, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xf5
+;   lpdr %f2, %f3
+;   br %r14
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -29,9 +43,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ocrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x75
+;   lper %f2, %f2
+;   br %r14
 
 function %bor_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -40,9 +61,16 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ocrk %r2, %r3, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x75
+;   lpdr %f2, %f3
+;   br %r14
 
 function %bxor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -50,9 +78,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lper %f2, %f2
+;   br %r14
 
 function %bxor_not_i32_reversed(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -61,9 +96,16 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r3, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lpdr %f2, %f3
+;   br %r14
 
 function %bnot_of_bxor(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -72,6 +114,14 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lper %f2, %f2
+;   br %r14
+
diff --git a/cranelift/filetests/filetests/isa/s390x/bitops.clif b/cranelift/filetests/filetests/isa/s390x/bitops.clif
index 8dc2813f69..a64b5fa20f 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitops.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitops.clif
@@ -7,6 +7,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 170
@@ -28,6 +29,38 @@ block0(v0: i128):
 ;   vperm %v20, %v16, %v16, %v18
 ;   vst %v20, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0xaa
+;   vrepib %v6, 1
+;   vsl %v16, %v1, %v6
+;   vsrl %v18, %v1, %v6
+;   vsel %v20, %v16, %v18, %v4
+;   vrepib %v22, 0xcc
+;   vrepib %v24, 2
+;   vsl %v26, %v20, %v24
+;   vsrl %v28, %v20, %v24
+;   vsel %v30, %v26, %v28, %v22
+;   vrepib %v0, 0xf0
+;   vrepib %v2, 4
+;   vsl %v4, %v30, %v2
+;   vsrl %v6, %v30, %v2
+;   vsel %v16, %v4, %v6, %v0
+;   bras %r1, 0x74
+;   clcl %r0, %r14
+;   basr %r0, %r12
+;   bsm %r0, %r10
+;   .byte 0x09, 0x08
+;   bcr 0, %r6
+;   balr %r0, %r4
+;   .byte 0x03, 0x02
+;   .byte 0x01, 0x00
+;   vl %v18, 0(%r1)
+;   vperm %v20, %v16, %v16, %v18
+;   vst %v20, 0(%r2)
+;   br %r14
 
 function %bitrev_i64(i64) -> i64 {
 block0(v0: i64):
@@ -35,6 +68,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r2
 ;   llihf %r2, 2863311530
@@ -67,6 +101,40 @@ block0(v0: i64):
 ;   ogr %r4, %r2
 ;   lrvgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r2
+;   llihf %r2, 0xaaaaaaaa
+;   iilf %r2, 0xaaaaaaaa
+;   lgr %r3, %r4
+;   sllg %r4, %r3, 1
+;   srlg %r3, %r3, 1
+;   ngr %r4, %r2
+;   xilf %r2, 0xffffffff
+;   xihf %r2, 0xffffffff
+;   ngrk %r2, %r3, %r2
+;   ogrk %r5, %r4, %r2
+;   llihf %r4, 0xcccccccc
+;   iilf %r4, 0xcccccccc
+;   sllg %r2, %r5, 2
+;   srlg %r5, %r5, 2
+;   ngr %r2, %r4
+;   xilf %r4, 0xffffffff
+;   xihf %r4, 0xffffffff
+;   ngrk %r4, %r5, %r4
+;   ogrk %r3, %r2, %r4
+;   llihf %r2, 0xf0f0f0f0
+;   iilf %r2, 0xf0f0f0f0
+;   sllg %r4, %r3, 4
+;   srlg %r3, %r3, 4
+;   ngr %r4, %r2
+;   xilf %r2, 0xffffffff
+;   xihf %r2, 0xffffffff
+;   ngrk %r2, %r3, %r2
+;   ogr %r4, %r2
+;   lrvgr %r2, %r4
+;   br %r14
 
 function %bitrev_i32(i32) -> i32 {
 block0(v0: i32):
@@ -74,6 +142,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   iilf %r4, 2863311530
 ;   sllk %r3, %r2, 1
@@ -98,6 +167,32 @@ block0(v0: i32):
 ;   ork %r4, %r2, %r3
 ;   lrvr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   iilf %r4, 0xaaaaaaaa
+;   sllk %r3, %r2, 1
+;   srlk %r5, %r2, 1
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   ork %r4, %r2, %r3
+;   iilf %r2, 0xcccccccc
+;   sllk %r5, %r4, 2
+;   srlk %r3, %r4, 2
+;   nrk %r4, %r5, %r2
+;   xilf %r2, 0xffffffff
+;   nrk %r5, %r3, %r2
+;   ork %r2, %r4, %r5
+;   iilf %r4, 0xf0f0f0f0
+;   sllk %r3, %r2, 4
+;   srlk %r5, %r2, 4
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   ork %r4, %r2, %r3
+;   lrvr %r2, %r4
+;   br %r14
 
 function %bitrev_i16(i16) -> i16 {
 block0(v0: i16):
@@ -105,6 +200,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, -21846
 ;   sllk %r3, %r2, 1
@@ -130,6 +226,33 @@ block0(v0: i16):
 ;   lrvr %r2, %r4
 ;   srlk %r2, %r2, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, -0x5556
+;   sllk %r3, %r2, 1
+;   srlk %r5, %r2, 1
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   ork %r4, %r2, %r3
+;   lhi %r2, -0x3334
+;   sllk %r5, %r4, 2
+;   srlk %r3, %r4, 2
+;   nrk %r4, %r5, %r2
+;   xilf %r2, 0xffffffff
+;   nrk %r5, %r3, %r2
+;   ork %r2, %r4, %r5
+;   lhi %r4, -0xf10
+;   sllk %r3, %r2, 4
+;   srlk %r5, %r2, 4
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   ork %r4, %r2, %r3
+;   lrvr %r2, %r4
+;   srlk %r2, %r2, 0x10
+;   br %r14
 
 function %bitrev_i8(i8) -> i8 {
 block0(v0: i8):
@@ -137,6 +260,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, -21846
 ;   sllk %r3, %r2, 1
@@ -160,6 +284,31 @@ block0(v0: i8):
 ;   nrk %r3, %r5, %r4
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, -0x5556
+;   sllk %r3, %r2, 1
+;   srlk %r5, %r2, 1
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   ork %r4, %r2, %r3
+;   lhi %r2, -0x3334
+;   sllk %r5, %r4, 2
+;   srlk %r3, %r4, 2
+;   nrk %r4, %r5, %r2
+;   xilf %r2, 0xffffffff
+;   nrk %r5, %r3, %r2
+;   ork %r2, %r4, %r5
+;   lhi %r4, -0xf10
+;   sllk %r3, %r2, 4
+;   srlk %r5, %r2, 4
+;   nrk %r2, %r3, %r4
+;   xilf %r4, 0xffffffff
+;   nrk %r3, %r5, %r4
+;   or %r2, %r3
+;   br %r14
 
 function %clz_i128(i128) -> i128 {
 block0(v0: i128):
@@ -167,6 +316,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vclzg %v4, %v1
@@ -179,6 +329,20 @@ block0(v0: i128):
 ;   vsel %v26, %v20, %v16, %v24
 ;   vst %v26, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vclzg %v4, %v1
+;   vzero %v6
+;   vpdi %v16, %v6, %v4, 0
+;   vpdi %v18, %v6, %v4, 1
+;   vag %v20, %v16, %v18
+;   vrepig %v22, 0x40
+;   vceqg %v24, %v16, %v22
+;   vsel %v26, %v20, %v16, %v24
+;   vst %v26, 0(%r2)
+;   br %r14
 
 function %clz_i64(i64) -> i64 {
 block0(v0: i64):
@@ -186,9 +350,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   flogr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   flogr %r2, %r2
+;   br %r14
 
 function %clz_i32(i32) -> i32 {
 block0(v0: i32):
@@ -196,11 +366,19 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r4, %r2
 ;   flogr %r2, %r4
 ;   ahi %r2, -32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x20
+;   br %r14
 
 function %clz_i16(i16) -> i16 {
 block0(v0: i16):
@@ -208,11 +386,19 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r4, %r2
 ;   flogr %r2, %r4
 ;   ahi %r2, -48
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x30
+;   br %r14
 
 function %clz_i8(i8) -> i8 {
 block0(v0: i8):
@@ -220,11 +406,19 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llgcr %r4, %r2
 ;   flogr %r2, %r4
 ;   ahi %r2, -56
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgcr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x38
+;   br %r14
 
 function %cls_i128(i128) -> i128 {
 block0(v0: i128):
@@ -232,6 +426,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 255
@@ -249,6 +444,25 @@ block0(v0: i128):
 ;   vaq %v4, %v2, %v4
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0xff
+;   vsrab %v6, %v1, %v4
+;   vsra %v16, %v6, %v4
+;   vx %v18, %v1, %v16
+;   vclzg %v20, %v18
+;   vzero %v22
+;   vpdi %v24, %v22, %v20, 0
+;   vpdi %v26, %v22, %v20, 1
+;   vag %v28, %v24, %v26
+;   vrepig %v30, 0x40
+;   vceqg %v0, %v24, %v30
+;   vsel %v2, %v28, %v24, %v0
+;   vaq %v4, %v2, %v4
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %cls_i64(i64) -> i64 {
 block0(v0: i64):
@@ -256,12 +470,21 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   srag %r4, %r2, 63
 ;   xgr %r2, %r4
 ;   flogr %r2, %r2
 ;   aghi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srag %r4, %r2, 0x3f
+;   xgr %r2, %r4
+;   flogr %r2, %r2
+;   aghi %r2, -1
+;   br %r14
 
 function %cls_i32(i32) -> i32 {
 block0(v0: i32):
@@ -269,6 +492,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r4, %r2
 ;   srag %r2, %r4, 63
@@ -276,6 +500,15 @@ block0(v0: i32):
 ;   flogr %r2, %r4
 ;   ahi %r2, -33
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r4, %r2
+;   srag %r2, %r4, 0x3f
+;   xgr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x21
+;   br %r14
 
 function %cls_i16(i16) -> i16 {
 block0(v0: i16):
@@ -283,6 +516,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r4, %r2
 ;   srag %r2, %r4, 63
@@ -290,6 +524,15 @@ block0(v0: i16):
 ;   flogr %r2, %r4
 ;   ahi %r2, -49
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r4, %r2
+;   srag %r2, %r4, 0x3f
+;   xgr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x31
+;   br %r14
 
 function %cls_i8(i8) -> i8 {
 block0(v0: i8):
@@ -297,6 +540,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r4, %r2
 ;   srag %r2, %r4, 63
@@ -304,6 +548,15 @@ block0(v0: i8):
 ;   flogr %r2, %r4
 ;   ahi %r2, -57
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r4, %r2
+;   srag %r2, %r4, 0x3f
+;   xgr %r4, %r2
+;   flogr %r2, %r4
+;   ahi %r2, -0x39
+;   br %r14
 
 function %ctz_i128(i128) -> i128 {
 block0(v0: i128):
@@ -311,6 +564,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vctzg %v4, %v1
@@ -323,6 +577,20 @@ block0(v0: i128):
 ;   vsel %v26, %v20, %v18, %v24
 ;   vst %v26, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vctzg %v4, %v1
+;   vzero %v6
+;   vpdi %v16, %v6, %v4, 0
+;   vpdi %v18, %v6, %v4, 1
+;   vag %v20, %v16, %v18
+;   vrepig %v22, 0x40
+;   vceqg %v24, %v18, %v22
+;   vsel %v26, %v20, %v18, %v24
+;   vst %v26, 0(%r2)
+;   br %r14
 
 function %ctz_i64(i64) -> i64 {
 block0(v0: i64):
@@ -330,6 +598,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lcgr %r4, %r2
 ;   ngr %r2, %r4
@@ -339,6 +608,17 @@ block0(v0: i64):
 ;   lghi %r5, 63
 ;   sgrk %r2, %r5, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcgr %r4, %r2
+;   ngr %r2, %r4
+;   flogr %r2, %r2
+;   lgr %r3, %r2
+;   locghie %r3, -1
+;   lghi %r5, 0x3f
+;   sgrk %r2, %r5, %r3
+;   br %r14
 
 function %ctz_i32(i32) -> i32 {
 block0(v0: i32):
@@ -346,6 +626,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r2
 ;   oihl %r4, 1
@@ -355,6 +636,17 @@ block0(v0: i32):
 ;   lhi %r5, 63
 ;   srk %r2, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r2
+;   oihl %r4, 1
+;   lcgr %r2, %r4
+;   ngr %r4, %r2
+;   flogr %r2, %r4
+;   lhi %r5, 0x3f
+;   srk %r2, %r5, %r2
+;   br %r14
 
 function %ctz_i16(i16) -> i16 {
 block0(v0: i16):
@@ -362,6 +654,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r2
 ;   oilh %r4, 1
@@ -371,6 +664,17 @@ block0(v0: i16):
 ;   lhi %r5, 63
 ;   srk %r2, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r2
+;   oilh %r4, 1
+;   lcgr %r2, %r4
+;   ngr %r4, %r2
+;   flogr %r2, %r4
+;   lhi %r5, 0x3f
+;   srk %r2, %r5, %r2
+;   br %r14
 
 function %ctz_i8(i8) -> i8 {
 block0(v0: i8):
@@ -378,6 +682,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lgr %r4, %r2
 ;   oill %r4, 256
@@ -387,6 +692,17 @@ block0(v0: i8):
 ;   lhi %r5, 63
 ;   srk %r2, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r4, %r2
+;   oill %r4, 0x100
+;   lcgr %r2, %r4
+;   ngr %r4, %r2
+;   flogr %r2, %r4
+;   lhi %r5, 0x3f
+;   srk %r2, %r5, %r2
+;   br %r14
 
 function %popcnt_i128(i128) -> i128 {
 block0(v0: i128):
@@ -394,6 +710,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vpopctg %v4, %v1
@@ -403,6 +720,17 @@ block0(v0: i128):
 ;   vag %v20, %v16, %v18
 ;   vst %v20, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vpopctg %v4, %v1
+;   vzero %v6
+;   vpdi %v16, %v6, %v4, 0
+;   vpdi %v18, %v6, %v4, 1
+;   vag %v20, %v16, %v18
+;   vst %v20, 0(%r2)
+;   br %r14
 
 function %popcnt_i64(i64) -> i64 {
 block0(v0: i64):
@@ -410,6 +738,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r4, %r2
 ;   sllg %r2, %r4, 32
@@ -420,6 +749,18 @@ block0(v0: i64):
 ;   agr %r4, %r2
 ;   srlg %r2, %r4, 56
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   popcnt %r4, %r2
+;   sllg %r2, %r4, 0x20
+;   agr %r4, %r2
+;   sllg %r2, %r4, 0x10
+;   agr %r4, %r2
+;   sllg %r2, %r4, 8
+;   agr %r4, %r2
+;   srlg %r2, %r4, 0x38
+;   br %r14
 
 function %popcnt_i32(i32) -> i32 {
 block0(v0: i32):
@@ -427,6 +768,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r4, %r2
 ;   sllk %r2, %r4, 16
@@ -435,6 +777,16 @@ block0(v0: i32):
 ;   ar %r4, %r2
 ;   srlk %r2, %r4, 24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   popcnt %r4, %r2
+;   sllk %r2, %r4, 0x10
+;   ar %r4, %r2
+;   sllk %r2, %r4, 8
+;   ar %r4, %r2
+;   srlk %r2, %r4, 0x18
+;   br %r14
 
 function %popcnt_i16(i16) -> i16 {
 block0(v0: i16):
@@ -442,12 +794,21 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r4, %r2
 ;   srlk %r2, %r4, 8
 ;   ark %r2, %r4, %r2
 ;   nill %r2, 255
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   popcnt %r4, %r2
+;   srlk %r2, %r4, 8
+;   ark %r2, %r4, %r2
+;   nill %r2, 0xff
+;   br %r14
 
 function %popcnt_i8(i8) -> i8 {
 block0(v0: i8):
@@ -455,7 +816,13 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   popcnt %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   popcnt %r2, %r2
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif b/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif
index 1285f6788d..66afb3945e 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif
@@ -12,9 +12,16 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ncgrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xe5
+;   lper %f2, %f2
+;   br %r14
 
 function %band_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -22,9 +29,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ncrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xf5
+;   lper %f2, %f2
+;   br %r14
 
 function %band_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -32,9 +46,16 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ncrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xf5
+;   lper %f2, %f2
+;   br %r14
 
 function %band_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -42,9 +63,16 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ncrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0xf5
+;   lper %f2, %f2
+;   br %r14
 
 function %bor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -52,9 +80,16 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ocgrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x65
+;   lper %f2, %f2
+;   br %r14
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -62,9 +97,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ocrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x75
+;   lper %f2, %f2
+;   br %r14
 
 function %bor_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -72,9 +114,16 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ocrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x75
+;   lper %f2, %f2
+;   br %r14
 
 function %bor_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -82,9 +131,16 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ocrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x75
+;   lper %f2, %f2
+;   br %r14
 
 function %bxor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -92,9 +148,16 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nxgrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x67
+;   lper %f2, %f2
+;   br %r14
 
 function %bxor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -102,9 +165,16 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lper %f2, %f2
+;   br %r14
 
 function %bxor_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -112,9 +182,16 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lper %f2, %f2
+;   br %r14
 
 function %bxor_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -122,9 +199,16 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nxrk %r2, %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x77
+;   lper %f2, %f2
+;   br %r14
 
 function %bnot_i64(i64) -> i64 {
 block0(v0: i64):
@@ -132,9 +216,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   nogrk %r2, %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x66
+;   lpdr %f2, %f2
+;   br %r14
 
 function %bnot_i32(i32) -> i32 {
 block0(v0: i32):
@@ -142,9 +233,16 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   nork %r2, %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x76
+;   lpdr %f2, %f2
+;   br %r14
 
 function %bnot_i16(i16) -> i16 {
 block0(v0: i16):
@@ -152,9 +250,16 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   nork %r2, %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x76
+;   lpdr %f2, %f2
+;   br %r14
 
 function %bnot_i8(i8) -> i8 {
 block0(v0: i8):
@@ -162,9 +267,16 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   nork %r2, %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xb9, 0x76
+;   lpdr %f2, %f2
+;   br %r14
 
 function %bitselect_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -172,11 +284,20 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ngr %r3, %r2
 ;   ncgrk %r4, %r4, %r2
 ;   ogrk %r2, %r4, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ngr %r3, %r2
+;   .byte 0xb9, 0xe5
+;   lpdr %f4, %f4
+;   ogrk %r2, %r4, %r3
+;   br %r14
 
 function %bitselect_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -184,11 +305,20 @@ block0(v0: i32, v1: i32, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   ncrk %r4, %r4, %r2
 ;   ork %r2, %r4, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   .byte 0xb9, 0xf5
+;   lpdr %f4, %f4
+;   ork %r2, %r4, %r3
+;   br %r14
 
 function %bitselect_i16(i16, i16, i16) -> i16 {
 block0(v0: i16, v1: i16, v2: i16):
@@ -196,11 +326,20 @@ block0(v0: i16, v1: i16, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   ncrk %r4, %r4, %r2
 ;   ork %r2, %r4, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   .byte 0xb9, 0xf5
+;   lpdr %f4, %f4
+;   ork %r2, %r4, %r3
+;   br %r14
 
 function %bitselect_i8(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -208,9 +347,18 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   ncrk %r4, %r4, %r2
 ;   ork %r2, %r4, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   .byte 0xb9, 0xf5
+;   lpdr %f4, %f4
+;   ork %r2, %r4, %r3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bitwise.clif b/cranelift/filetests/filetests/isa/s390x/bitwise.clif
index 37f0b5488c..94a7ec1927 100644
--- a/cranelift/filetests/filetests/isa/s390x/bitwise.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bitwise.clif
@@ -10,12 +10,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vn %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vn %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %band_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -23,9 +32,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ngr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ngr %r2, %r3
+;   br %r14
 
 function %band_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -34,9 +49,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ng %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ng %r2, 0(%r3)
+;   br %r14
 
 function %band_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -44,9 +65,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r2, %r3
+;   br %r14
 
 function %band_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -55,9 +82,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   n %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   n %r2, 0(%r3)
+;   br %r14
 
 function %band_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -66,9 +99,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ny %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ny %r2, 0x1000(%r3)
+;   br %r14
 
 function %band_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -76,9 +115,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r2, %r3
+;   br %r14
 
 function %band_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -87,10 +132,17 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llh %r3, 0(%r3)
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r3, 0(%r3)
+;   nr %r2, %r3
+;   br %r14
 
 function %band_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -98,9 +150,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r2, %r3
+;   br %r14
 
 function %band_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -109,10 +167,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   nr %r2, %r3
+;   br %r14
 
 function %bor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -120,12 +185,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vo %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vo %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %bor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -133,9 +207,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ogr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ogr %r2, %r3
+;   br %r14
 
 function %bor_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -144,9 +224,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   og %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   og %r2, 0(%r3)
+;   br %r14
 
 function %bor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -154,9 +240,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or %r2, %r3
+;   br %r14
 
 function %bor_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -165,9 +257,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   o %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   o %r2, 0(%r3)
+;   br %r14
 
 function %bor_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -176,9 +274,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   oy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   oy %r2, 0x1000(%r3)
+;   br %r14
 
 function %bor_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -186,9 +290,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or %r2, %r3
+;   br %r14
 
 function %bor_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -197,10 +307,17 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llh %r3, 0(%r3)
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r3, 0(%r3)
+;   or %r2, %r3
+;   br %r14
 
 function %bor_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -208,9 +325,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   or %r2, %r3
+;   br %r14
 
 function %bor_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -219,10 +342,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   or %r2, %r3
+;   br %r14
 
 function %bxor_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -230,12 +360,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vx %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vx %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %bxor_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -243,9 +382,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xgr %r2, %r3
+;   br %r14
 
 function %bxor_i64_mem(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -254,9 +399,15 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   xg %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xg %r2, 0(%r3)
+;   br %r14
 
 function %bxor_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -264,9 +415,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_i32_mem(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -275,9 +432,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   x %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   x %r2, 0(%r3)
+;   br %r14
 
 function %bxor_i32_memoff(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -286,9 +449,15 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   xy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xy %r2, 0x1000(%r3)
+;   br %r14
 
 function %bxor_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -296,9 +465,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_i16_mem(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -307,10 +482,17 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llh %r3, 0(%r3)
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r3, 0(%r3)
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -318,9 +500,15 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -329,10 +517,17 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   xr %r2, %r3
+;   br %r14
 
 function %band_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -340,12 +535,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vnc %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vnc %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %band_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -353,11 +557,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xihf %r3, 4294967295
 ;   ngr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xihf %r3, 0xffffffff
+;   ngr %r2, %r3
+;   br %r14
 
 function %band_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -365,10 +577,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   nr %r2, %r3
+;   br %r14
 
 function %band_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -376,10 +595,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   nr %r2, %r3
+;   br %r14
 
 function %band_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -387,10 +613,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   nr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   nr %r2, %r3
+;   br %r14
 
 function %bor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -398,12 +631,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   voc %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   voc %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %bor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -411,11 +653,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xihf %r3, 4294967295
 ;   ogr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xihf %r3, 0xffffffff
+;   ogr %r2, %r3
+;   br %r14
 
 function %bor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -423,10 +673,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   or %r2, %r3
+;   br %r14
 
 function %bor_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -434,10 +691,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   or %r2, %r3
+;   br %r14
 
 function %bor_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -445,10 +709,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   or %r2, %r3
+;   br %r14
 
 function %bxor_not_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -456,12 +727,21 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vnx %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vnx %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %bxor_not_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -469,11 +749,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xihf %r3, 4294967295
 ;   xgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xihf %r3, 0xffffffff
+;   xgr %r2, %r3
+;   br %r14
 
 function %bxor_not_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -481,10 +769,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_not_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -492,10 +787,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xr %r2, %r3
+;   br %r14
 
 function %bxor_not_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -503,10 +805,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   xilf %r3, 4294967295
 ;   xr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r3, 0xffffffff
+;   xr %r2, %r3
+;   br %r14
 
 function %bnot_i128(i128) -> i128 {
 block0(v0: i128):
@@ -514,11 +823,19 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vno %v4, %v1, %v1
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vno %v4, %v1, %v1
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %bnot_i64(i64) -> i64 {
 block0(v0: i64):
@@ -526,10 +843,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   xilf %r2, 4294967295
 ;   xihf %r2, 4294967295
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r2, 0xffffffff
+;   xihf %r2, 0xffffffff
+;   br %r14
 
 function %bnot_i32(i32) -> i32 {
 block0(v0: i32):
@@ -537,9 +861,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   xilf %r2, 4294967295
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r2, 0xffffffff
+;   br %r14
 
 function %bnot_i16(i16) -> i16 {
 block0(v0: i16):
@@ -547,9 +877,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   xilf %r2, 4294967295
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r2, 0xffffffff
+;   br %r14
 
 function %bnot_i8(i8) -> i8 {
 block0(v0: i8):
@@ -557,9 +893,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   xilf %r2, 4294967295
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xilf %r2, 0xffffffff
+;   br %r14
 
 function %bitselect_i128(i128, i128, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128):
@@ -567,6 +909,7 @@ block0(v0: i128, v1: i128, v2: i128):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -574,6 +917,15 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   vsel %v16, %v3, %v5, %v1
 ;   vst %v16, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vl %v5, 0(%r5)
+;   vsel %v16, %v3, %v5, %v1
+;   vst %v16, 0(%r2)
+;   br %r14
 
 function %bitselect_i64(i64, i64, i64) -> i64 {
 block0(v0: i64, v1: i64, v2: i64):
@@ -581,6 +933,7 @@ block0(v0: i64, v1: i64, v2: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ngr %r3, %r2
 ;   lgr %r5, %r2
@@ -589,6 +942,16 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   ngr %r4, %r5
 ;   ogrk %r2, %r4, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ngr %r3, %r2
+;   lgr %r5, %r2
+;   xilf %r5, 0xffffffff
+;   xihf %r5, 0xffffffff
+;   ngr %r4, %r5
+;   ogrk %r2, %r4, %r3
+;   br %r14
 
 function %bitselect_i32(i32, i32, i32) -> i32 {
 block0(v0: i32, v1: i32, v2: i32):
@@ -596,6 +959,7 @@ block0(v0: i32, v1: i32, v2: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
@@ -603,6 +967,15 @@ block0(v0: i32, v1: i32, v2: i32):
 ;   nrk %r2, %r4, %r5
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   lgr %r5, %r2
+;   xilf %r5, 0xffffffff
+;   nrk %r2, %r4, %r5
+;   or %r2, %r3
+;   br %r14
 
 function %bitselect_i16(i16, i16, i16) -> i16 {
 block0(v0: i16, v1: i16, v2: i16):
@@ -610,6 +983,7 @@ block0(v0: i16, v1: i16, v2: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
@@ -617,6 +991,15 @@ block0(v0: i16, v1: i16, v2: i16):
 ;   nrk %r2, %r4, %r5
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   lgr %r5, %r2
+;   xilf %r5, 0xffffffff
+;   nrk %r2, %r4, %r5
+;   or %r2, %r3
+;   br %r14
 
 function %bitselect_i8(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -624,6 +1007,7 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
@@ -631,6 +1015,15 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   nrk %r2, %r4, %r5
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   nr %r3, %r2
+;   lgr %r5, %r2
+;   xilf %r5, 0xffffffff
+;   nrk %r2, %r4, %r5
+;   or %r2, %r3
+;   br %r14
 
 function %bnot_of_bxor(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -639,10 +1032,17 @@ block0(v0: i32, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   xr %r2, %r3
 ;   xilf %r2, 4294967295
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xr %r2, %r3
+;   xilf %r2, 0xffffffff
+;   br %r14
 
 function %bnot_of_bxor(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -651,12 +1051,21 @@ block0(v0: i128, v1: i128):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
 ;   vnx %v6, %v1, %v3
 ;   vst %v6, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vnx %v6, %v1, %v3
+;   vst %v6, 0(%r2)
+;   br %r14
 
 function %bnot_of_bxor(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -665,7 +1074,13 @@ block0(v0: i32x4, v1: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vnx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnx %v24, %v24, %v25
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/bswap.clif b/cranelift/filetests/filetests/isa/s390x/bswap.clif
index 6d6d87d96e..a1fcb64ed0 100644
--- a/cranelift/filetests/filetests/isa/s390x/bswap.clif
+++ b/cranelift/filetests/filetests/isa/s390x/bswap.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvgr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvgr %r2, %r2
+;   br %r14
 
 function %bswap_i32(i32) -> i32 {
 block0(v0: i32):
@@ -17,9 +23,15 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r2, %r2
+;   br %r14
 
 function %bswap_i16(i16) -> i16 {
 block0(v0: i16):
@@ -27,8 +39,15 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvr %r4, %r2
 ;   srlk %r2, %r4, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvr %r4, %r2
+;   srlk %r2, %r4, 0x10
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/call.clif b/cranelift/filetests/filetests/isa/s390x/call.clif
index 37a90760b1..9fabef2c92 100644
--- a/cranelift/filetests/filetests/isa/s390x/call.clif
+++ b/cranelift/filetests/filetests/isa/s390x/call.clif
@@ -13,6 +13,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -21,6 +22,20 @@ block0(v0: i64):
 ;   basr %r14, %r5
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   bras %r1, 0x16
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r5, 0(%r1)
+;   basr %r14, %r5
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %call_uext(i32) -> i64 {
     fn0 = %g(i32 uext) -> i64
@@ -30,6 +45,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -39,15 +55,36 @@ block0(v0: i32):
 ;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   llgfr %r2, %r2
+;   bras %r1, 0x1a
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r3, 0(%r1)
+;   basr %r14, %r3
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %ret_uext(i32) -> i32 uext {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r2, %r2
+;   br %r14
 
 function %call_uext(i32) -> i64 {
     fn0 = %g(i32 sext) -> i64
@@ -57,6 +94,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -66,15 +104,36 @@ block0(v0: i32):
 ;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   lgfr %r2, %r2
+;   bras %r1, 0x1a
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r3, 0(%r1)
+;   basr %r14, %r3
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %ret_uext(i32) -> i32 sext {
 block0(v0: i32):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r2, %r2
+;   br %r14
 
 function %call_colocated(i64) -> i64 {
     fn0 = colocated %g(i64) -> i64
@@ -84,6 +143,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -91,6 +151,14 @@ block0(v0: i64):
 ;   brasl %r14, %g
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   brasl %r14, 0xa ; reloc_external PLTRel32Dbl %g 2
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %f2(i32) -> i64 {
     fn0 = %g(i32 uext) -> i64
@@ -100,6 +168,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -109,6 +178,21 @@ block0(v0: i32):
 ;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   llgfr %r2, %r2
+;   bras %r1, 0x1a
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r3, 0(%r1)
+;   basr %r14, %r3
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %call_indirect(i64, i64) -> i64 {
     sig0 = (i64) -> i64
@@ -117,6 +201,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -124,6 +209,14 @@ block0(v0: i64, v1: i64):
 ;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   basr %r14, %r3
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %incoming_args(i64, i32, i32 uext, i32 sext, i16, i16 uext, i16 sext, i8, i8 uext, i8 sext) -> i64 {
 block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8: i8, v9: i8):
@@ -148,6 +241,7 @@ block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8
     return v27
 }
 
+; VCode:
 ;   stmg %r6, %r15, 48(%r15)
 ; block0:
 ;   lg %r12, 160(%r15)
@@ -175,6 +269,35 @@ block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8
 ;   agrk %r2, %r4, %r3
 ;   lmg %r6, %r15, 48(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r6, %r15, 0x30(%r15)
+; block0: ; offset 0x6
+;   lg %r12, 0xa0(%r15)
+;   lg %r14, 0xa8(%r15)
+;   llgc %r7, 0xb7(%r15)
+;   lg %r9, 0xb8(%r15)
+;   lg %r11, 0xc0(%r15)
+;   llgfr %r3, %r3
+;   llgfr %r4, %r4
+;   llgfr %r13, %r5
+;   llghr %r6, %r6
+;   llghr %r5, %r12
+;   llghr %r12, %r14
+;   llgcr %r14, %r7
+;   llgcr %r7, %r9
+;   llgcr %r8, %r11
+;   agrk %r3, %r2, %r3
+;   agr %r4, %r13
+;   agrk %r5, %r6, %r5
+;   agrk %r2, %r12, %r14
+;   agrk %r12, %r7, %r8
+;   agr %r3, %r4
+;   agrk %r4, %r5, %r2
+;   agrk %r3, %r12, %r3
+;   agrk %r2, %r4, %r3
+;   lmg %r6, %r15, 0x30(%r15)
+;   br %r14
 
 function %incoming_args_i128(i128, i128, i128, i128, i128, i128, i128, i128) -> i128 {
 block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7: i128):
@@ -188,6 +311,7 @@ block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7:
     return v14
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -210,6 +334,30 @@ block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7:
 ;   vaq %v16, %v16, %v17
 ;   vst %v16, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vl %v5, 0(%r5)
+;   vl %v7, 0(%r6)
+;   lg %r3, 0xa0(%r15)
+;   vl %v18, 0(%r3)
+;   lg %r3, 0xa8(%r15)
+;   vl %v21, 0(%r3)
+;   lg %r5, 0xb0(%r15)
+;   vl %v24, 0(%r5)
+;   lg %r4, 0xb8(%r15)
+;   vl %v27, 0(%r4)
+;   vaq %v16, %v1, %v3
+;   vaq %v17, %v5, %v7
+;   vaq %v18, %v18, %v21
+;   vaq %v19, %v24, %v27
+;   vaq %v16, %v16, %v17
+;   vaq %v17, %v18, %v19
+;   vaq %v16, %v16, %v17
+;   vst %v16, 0(%r2)
+;   br %r14
 
 function %call_sret() -> i64 {
     fn0 = colocated %g(i64 sret)
@@ -220,6 +368,7 @@ block0:
     trap user0
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -227,4 +376,12 @@ block0:
 ;   lghi %r2, 0
 ;   brasl %r14, %g
 ;   trap
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   lghi %r2, 0
+;   brasl %r14, 0xe ; reloc_external PLTRel32Dbl %g 2
+;   .byte 0x00, 0x00 ; trap: user0
 
diff --git a/cranelift/filetests/filetests/isa/s390x/concat-split.clif b/cranelift/filetests/filetests/isa/s390x/concat-split.clif
index 00057d4da7..a69adfdfc2 100644
--- a/cranelift/filetests/filetests/isa/s390x/concat-split.clif
+++ b/cranelift/filetests/filetests/isa/s390x/concat-split.clif
@@ -7,10 +7,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgp %v4, %r4, %r3
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgp %v4, %r4, %r3
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %isplit_i128(i128) -> i64, i64 {
 block0(v0: i128):
@@ -18,9 +25,17 @@ block0(v0: i128):
   return v1, v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   lgdr %r3, %f1
 ;   vlgvg %r2, %v1, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   lgdr %r3, %f1
+;   vlgvg %r2, %v1, 1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/condbr.clif b/cranelift/filetests/filetests/isa/s390x/condbr.clif
index 4b83a87906..13c287d943 100644
--- a/cranelift/filetests/filetests/isa/s390x/condbr.clif
+++ b/cranelift/filetests/filetests/isa/s390x/condbr.clif
@@ -7,11 +7,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -27,6 +35,7 @@ block2:
   return v5
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   jge label1 ; jg label2
@@ -36,6 +45,17 @@ block2:
 ; block2:
 ;   lghi %r2, 2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+;   jgne 0x10
+; block1: ; offset 0xa
+;   lghi %r2, 1
+;   br %r14
+; block2: ; offset 0x10
+;   lghi %r2, 2
+;   br %r14
 
 function %f(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -47,6 +67,7 @@ block1:
   return v4
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   jge label1 ; jg label2
@@ -57,4 +78,11 @@ block1:
 ; block3:
 ;   lghi %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+; block1: ; offset 0x4
+;   lghi %r2, 1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/condops.clif b/cranelift/filetests/filetests/isa/s390x/condops.clif
index 65d525e2b7..97cb275a3e 100644
--- a/cranelift/filetests/filetests/isa/s390x/condops.clif
+++ b/cranelift/filetests/filetests/isa/s390x/condops.clif
@@ -9,12 +9,21 @@ block0(v0: i8, v1: i64, v2: i64):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   llcr %r2, %r2
 ;   clfi %r2, 42
 ;   lgr %r2, %r4
 ;   locgre %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r2, %r2
+;   clfi %r2, 0x2a
+;   lgr %r2, %r4
+;   locgre %r2, %r3
+;   br %r14
 
 function %g(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -22,12 +31,21 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lbr %r2, %r2
 ;   chi %r2, 0
 ;   lgr %r2, %r4
 ;   locrlh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r2, %r2
+;   chi %r2, 0
+;   lgr %r2, %r4
+;   locrlh %r2, %r3
+;   br %r14
 
 function %i(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -37,11 +55,19 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   clfi %r2, 42
 ;   lgr %r2, %r4
 ;   locre %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clfi %r2, 0x2a
+;   lgr %r2, %r4
+;   locre %r2, %r3
+;   br %r14
 
 function %i(i32, i8x16, i8x16) -> i8x16 {
 block0(v0: i32, v1: i8x16, v2: i8x16):
@@ -51,10 +77,20 @@ block0(v0: i32, v1: i8x16, v2: i8x16):
   return v5
 }
 
+; VCode:
 ; block0:
 ;   clfi %r2, 42
 ;   vlr %v6, %v24
 ;   vlr %v24, %v25
 ;   jne 10 ; vlr %v24, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clfi %r2, 0x2a
+;   vlr %v6, %v24
+;   vlr %v24, %v25
+;   jne 0x1c
+;   vlr %v24, %v6
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/constants.clif b/cranelift/filetests/filetests/isa/s390x/constants.clif
index 2f6c0966fa..d1b05d18a3 100644
--- a/cranelift/filetests/filetests/isa/s390x/constants.clif
+++ b/cranelift/filetests/filetests/isa/s390x/constants.clif
@@ -7,9 +7,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lhi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r2, -1
+;   br %r14
 
 function %f() -> i16 {
 block0:
@@ -17,9 +23,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lhi %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r2, 0
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -27,9 +39,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lghi %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r2, 0
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -37,9 +55,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lgfi %r2, 65535
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfi %r2, 0xffff
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -47,9 +71,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   llilh %r2, 65535
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llilh %r2, 0xffff
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -57,9 +87,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   llihl %r2, 65535
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llihl %r2, 0xffff
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -67,9 +103,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   llihh %r2, 65535
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llihh %r2, 0xffff
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -77,9 +119,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lghi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r2, -1
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -87,9 +135,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lgfi %r2, -65536
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfi %r2, -0x10000
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -97,10 +151,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   llihf %r2, 4081840291
 ;   iilf %r2, 303169594
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llihf %r2, 0xf34bf0a3
+;   iilf %r2, 0x1212003a
+;   br %r14
 
 function %f() -> i64 {
 block0:
@@ -108,10 +169,17 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   llihh %r2, 4841
 ;   iilh %r2, 7924
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llihh %r2, 0x12e9
+;   iilh %r2, 0x1ef4
+;   br %r14
 
 function %f() -> i32 {
 block0:
@@ -119,7 +187,13 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lhi %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r2, -1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/conversions.clif b/cranelift/filetests/filetests/isa/s390x/conversions.clif
index 64f7ae94e3..655f0772ec 100644
--- a/cranelift/filetests/filetests/isa/s390x/conversions.clif
+++ b/cranelift/filetests/filetests/isa/s390x/conversions.clif
@@ -7,11 +7,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v4, 0
 ;   vlvgg %v4, %r3, 1
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v4
+;   vlvgg %v4, %r3, 1
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %uextend_i32_i128(i32) -> i128 {
 block0(v0: i32):
@@ -19,11 +27,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v4, 0
 ;   vlvgf %v4, %r3, 3
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v4
+;   vlvgf %v4, %r3, 3
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %uextend_i32_i64(i32) -> i64 {
 block0(v0: i32):
@@ -31,9 +47,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r2, %r2
+;   br %r14
 
 function %uextend_i16_i128(i16) -> i128 {
 block0(v0: i16):
@@ -41,11 +63,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v4, 0
 ;   vlvgh %v4, %r3, 7
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v4
+;   vlvgh %v4, %r3, 7
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %uextend_i16_i64(i16) -> i64 {
 block0(v0: i16):
@@ -53,9 +83,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r2, %r2
+;   br %r14
 
 function %uextend_i16_i32(i16) -> i32 {
 block0(v0: i16):
@@ -63,9 +99,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llhr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r2, %r2
+;   br %r14
 
 function %uextend_i8_i128(i8) -> i128 {
 block0(v0: i8):
@@ -73,11 +115,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v4, 0
 ;   vlvgb %v4, %r3, 15
 ;   vst %v4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v4
+;   vlvgb %v4, %r3, 0xf
+;   vst %v4, 0(%r2)
+;   br %r14
 
 function %uextend_i8_i64(i8) -> i64 {
 block0(v0: i8):
@@ -85,9 +135,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgcr %r2, %r2
+;   br %r14
 
 function %uextend_i8_i32(i8) -> i32 {
 block0(v0: i8):
@@ -95,9 +151,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r2, %r2
+;   br %r14
 
 function %uextend_i8_i16(i8) -> i16 {
 block0(v0: i8):
@@ -105,9 +167,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llcr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r2, %r2
+;   br %r14
 
 function %sextend_i64_i128(i64) -> i128 {
 block0(v0: i64):
@@ -115,11 +183,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   srag %r5, %r3, 63
 ;   vlvgp %v5, %r5, %r3
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srag %r5, %r3, 0x3f
+;   vlvgp %v5, %r5, %r3
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %sextend_i32_i128(i32) -> i128 {
 block0(v0: i32):
@@ -127,12 +203,21 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r5, %r3
 ;   srag %r3, %r5, 63
 ;   vlvgp %v7, %r3, %r5
 ;   vst %v7, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r5, %r3
+;   srag %r3, %r5, 0x3f
+;   vlvgp %v7, %r3, %r5
+;   vst %v7, 0(%r2)
+;   br %r14
 
 function %sextend_i32_i64(i32) -> i64 {
 block0(v0: i32):
@@ -140,9 +225,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r2, %r2
+;   br %r14
 
 function %sextend_i16_i128(i16) -> i128 {
 block0(v0: i16):
@@ -150,12 +241,21 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r5, %r3
 ;   srag %r3, %r5, 63
 ;   vlvgp %v7, %r3, %r5
 ;   vst %v7, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r5, %r3
+;   srag %r3, %r5, 0x3f
+;   vlvgp %v7, %r3, %r5
+;   vst %v7, 0(%r2)
+;   br %r14
 
 function %sextend_i16_i64(i16) -> i64 {
 block0(v0: i16):
@@ -163,9 +263,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r2, %r2
+;   br %r14
 
 function %sextend_i16_i32(i16) -> i32 {
 block0(v0: i16):
@@ -173,9 +279,15 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lhr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r2, %r2
+;   br %r14
 
 function %sextend_i8_i128(i8) -> i128 {
 block0(v0: i8):
@@ -183,12 +295,21 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r5, %r3
 ;   srag %r3, %r5, 63
 ;   vlvgp %v7, %r3, %r5
 ;   vst %v7, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r5, %r3
+;   srag %r3, %r5, 0x3f
+;   vlvgp %v7, %r3, %r5
+;   vst %v7, 0(%r2)
+;   br %r14
 
 function %sextend_i8_i64(i8) -> i64 {
 block0(v0: i8):
@@ -196,9 +317,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r2, %r2
+;   br %r14
 
 function %sextend_i8_i32(i8) -> i32 {
 block0(v0: i8):
@@ -206,9 +333,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lbr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r2, %r2
+;   br %r14
 
 function %sextend_i8_i16(i8) -> i16 {
 block0(v0: i8):
@@ -216,9 +349,15 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lbr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r2, %r2
+;   br %r14
 
 function %ireduce_i128_i64(i128) -> i64 {
 block0(v0: i128):
@@ -226,10 +365,17 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vlgvg %r2, %v1, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vlgvg %r2, %v1, 1
+;   br %r14
 
 function %ireduce_i128_i32(i128) -> i32 {
 block0(v0: i128):
@@ -237,10 +383,17 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vlgvg %r2, %v1, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vlgvg %r2, %v1, 1
+;   br %r14
 
 function %ireduce_i128_i16(i128) -> i16 {
 block0(v0: i128):
@@ -248,10 +401,17 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vlgvg %r2, %v1, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vlgvg %r2, %v1, 1
+;   br %r14
 
 function %ireduce_i128_i8(i128) -> i8 {
 block0(v0: i128):
@@ -259,10 +419,17 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vlgvg %r2, %v1, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vlgvg %r2, %v1, 1
+;   br %r14
 
 function %ireduce_i64_i32(i64, i64) -> i32 {
 block0(v0: i64, v1: i64):
@@ -270,9 +437,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %ireduce_i64_i16(i64, i64) -> i16 {
 block0(v0: i64, v1: i64):
@@ -280,9 +453,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %ireduce_i64_i8(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -290,9 +469,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %ireduce_i32_i16(i32, i32) -> i16 {
 block0(v0: i32, v1: i32):
@@ -300,9 +485,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %ireduce_i32_i8(i32, i32) -> i8 {
 block0(v0: i32, v1: i32):
@@ -310,9 +501,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %ireduce_i16_i8(i16, i16) -> i8 {
 block0(v0: i16, v1: i16):
@@ -320,9 +517,15 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %bmask_i128_i128(i128) -> i128 {
 block0(v0: i128):
@@ -330,6 +533,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vgbm %v4, 0
@@ -339,6 +543,17 @@ block0(v0: i128):
 ;   vlvgp %v20, %r3, %r3
 ;   vst %v20, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vzero %v4
+;   vceqgs %v6, %v1, %v4
+;   lghi %r3, 0
+;   locghine %r3, -1
+;   vlvgp %v20, %r3, %r3
+;   vst %v20, 0(%r2)
+;   br %r14
 
 function %bmask_i128_i64(i128) -> i64 {
 block0(v0: i128):
@@ -346,6 +561,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vgbm %v3, 0
@@ -353,6 +569,15 @@ block0(v0: i128):
 ;   lghi %r2, 0
 ;   locghine %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vzero %v3
+;   vceqgs %v5, %v1, %v3
+;   lghi %r2, 0
+;   locghine %r2, -1
+;   br %r14
 
 function %bmask_i128_i32(i128) -> i32 {
 block0(v0: i128):
@@ -360,6 +585,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vgbm %v3, 0
@@ -367,6 +593,15 @@ block0(v0: i128):
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vzero %v3
+;   vceqgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochine %r2, -1
+;   br %r14
 
 function %bmask_i128_i16(i128) -> i16 {
 block0(v0: i128):
@@ -374,6 +609,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vgbm %v3, 0
@@ -381,6 +617,15 @@ block0(v0: i128):
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vzero %v3
+;   vceqgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochine %r2, -1
+;   br %r14
 
 function %bmask_i128_i8(i128) -> i8 {
 block0(v0: i128):
@@ -388,6 +633,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vgbm %v3, 0
@@ -395,6 +641,15 @@ block0(v0: i128):
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vzero %v3
+;   vceqgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochine %r2, -1
+;   br %r14
 
 function %bmask_i64_i128(i64, i64) -> i128 {
 block0(v0: i64, v1: i64):
@@ -402,6 +657,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r4, 0
 ;   lghi %r4, 0
@@ -409,6 +665,15 @@ block0(v0: i64, v1: i64):
 ;   vlvgp %v17, %r4, %r4
 ;   vst %v17, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r4, 0
+;   lghi %r4, 0
+;   locghilh %r4, -1
+;   vlvgp %v17, %r4, %r4
+;   vst %v17, 0(%r2)
+;   br %r14
 
 function %bmask_i64_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -416,11 +681,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r3, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r3, 0
+;   lghi %r2, 0
+;   locghilh %r2, -1
+;   br %r14
 
 function %bmask_i64_i32(i64, i64) -> i32 {
 block0(v0: i64, v1: i64):
@@ -428,11 +701,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i64_i16(i64, i64) -> i16 {
 block0(v0: i64, v1: i64):
@@ -440,11 +721,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i64_i8(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -452,11 +741,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i32_i128(i32, i32) -> i128 {
 block0(v0: i32, v1: i32):
@@ -464,6 +761,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r4, 0
 ;   lghi %r4, 0
@@ -471,6 +769,15 @@ block0(v0: i32, v1: i32):
 ;   vlvgp %v17, %r4, %r4
 ;   vst %v17, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r4, 0
+;   lghi %r4, 0
+;   locghilh %r4, -1
+;   vlvgp %v17, %r4, %r4
+;   vst %v17, 0(%r2)
+;   br %r14
 
 function %bmask_i32_i64(i32, i32) -> i64 {
 block0(v0: i32, v1: i32):
@@ -478,11 +785,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r3, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r3, 0
+;   lghi %r2, 0
+;   locghilh %r2, -1
+;   br %r14
 
 function %bmask_i32_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -490,11 +805,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i32_i16(i32, i32) -> i16 {
 block0(v0: i32, v1: i32):
@@ -502,11 +825,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i32_i8(i32, i32) -> i8 {
 block0(v0: i32, v1: i32):
@@ -514,11 +845,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r3, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r3, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i16_i128(i16, i16) -> i128 {
 block0(v0: i16, v1: i16):
@@ -526,6 +865,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r3, %r4
 ;   chi %r3, 0
@@ -534,6 +874,16 @@ block0(v0: i16, v1: i16):
 ;   vlvgp %v19, %r3, %r3
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r3, %r4
+;   chi %r3, 0
+;   lghi %r3, 0
+;   locghilh %r3, -1
+;   vlvgp %v19, %r3, %r3
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %bmask_i16_i64(i16, i16) -> i64 {
 block0(v0: i16, v1: i16):
@@ -541,12 +891,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r3
 ;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r3
+;   chi %r5, 0
+;   lghi %r2, 0
+;   locghilh %r2, -1
+;   br %r14
 
 function %bmask_i16_i32(i16, i16) -> i32 {
 block0(v0: i16, v1: i16):
@@ -554,12 +913,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i16_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -567,12 +935,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i16_i8(i16, i16) -> i8 {
 block0(v0: i16, v1: i16):
@@ -580,12 +957,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i128(i8, i8) -> i128 {
 block0(v0: i8, v1: i8):
@@ -593,6 +979,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r3, %r4
 ;   chi %r3, 0
@@ -601,6 +988,16 @@ block0(v0: i8, v1: i8):
 ;   vlvgp %v19, %r3, %r3
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r3, %r4
+;   chi %r3, 0
+;   lghi %r3, 0
+;   locghilh %r3, -1
+;   vlvgp %v19, %r3, %r3
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %bmask_i8_i64(i8, i8) -> i64 {
 block0(v0: i8, v1: i8):
@@ -608,12 +1005,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lghi %r2, 0
+;   locghilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i32(i8, i8) -> i32 {
 block0(v0: i8, v1: i8):
@@ -621,12 +1027,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i16(i8, i8) -> i16 {
 block0(v0: i8, v1: i8):
@@ -634,12 +1049,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -647,12 +1071,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i128(i8, i8) -> i128 {
 block0(v0: i8, v1: i8):
@@ -660,6 +1093,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r3, %r4
 ;   chi %r3, 0
@@ -668,6 +1102,16 @@ block0(v0: i8, v1: i8):
 ;   vlvgp %v19, %r3, %r3
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r3, %r4
+;   chi %r3, 0
+;   lghi %r3, 0
+;   locghilh %r3, -1
+;   vlvgp %v19, %r3, %r3
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %bmask_i8_i64(i8, i8) -> i64 {
 block0(v0: i8, v1: i8):
@@ -675,12 +1119,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lghi %r2, 0
+;   locghilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i32(i8, i8) -> i32 {
 block0(v0: i8, v1: i8):
@@ -688,12 +1141,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i16(i8, i8) -> i16 {
 block0(v0: i8, v1: i8):
@@ -701,12 +1163,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
 function %bmask_i8_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -714,10 +1185,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r3
 ;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r3
+;   chi %r5, 0
+;   lhi %r2, 0
+;   lochilh %r2, -1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/div-traps.clif b/cranelift/filetests/filetests/isa/s390x/div-traps.clif
index ca58173104..b1d98a43d0 100644
--- a/cranelift/filetests/filetests/isa/s390x/div-traps.clif
+++ b/cranelift/filetests/filetests/isa/s390x/div-traps.clif
@@ -12,6 +12,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgite %r3, 0
 ;   llihf %r4, 2147483647
@@ -26,6 +27,22 @@ block0(v0: i64, v1: i64):
 ;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgite %r3, 0 ; trap: int_divz
+;   llihf %r4, 0x7fffffff
+;   iilf %r4, 0xffffffff
+;   xgr %r4, %r2
+;   lgr %r5, %r2
+;   ngr %r4, %r3
+;   lgr %r2, %r3
+;   cgite %r4, -1 ; trap: int_ovf
+;   lgr %r4, %r2
+;   lgr %r3, %r5
+;   dsgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -34,12 +51,21 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lghi %r4, 2
 ;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lghi %r4, 2
+;   dsgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -47,6 +73,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   stmg %r7, %r15, 56(%r15)
 ; block0:
 ;   lgfr %r5, %r2
@@ -63,6 +90,24 @@ block0(v0: i32, v1: i32):
 ;   lgr %r2, %r3
 ;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r7, %r15, 0x38(%r15)
+; block0: ; offset 0x6
+;   lgfr %r5, %r2
+;   lgr %r7, %r5
+;   cite %r3, 0 ; trap: int_divz
+;   iilf %r5, 0x7fffffff
+;   lgr %r4, %r7
+;   xrk %r2, %r5, %r4
+;   nrk %r4, %r2, %r3
+;   lgr %r5, %r3
+;   cite %r4, -1 ; trap: int_ovf
+;   lgr %r3, %r7
+;   dsgfr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r7, %r15, 0x38(%r15)
+;   br %r14
 
 function %sdiv_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -71,12 +116,21 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -84,6 +138,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghr %r5, %r2
 ;   lhr %r4, %r3
@@ -96,6 +151,20 @@ block0(v0: i16, v1: i16):
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r5, %r2
+;   lhr %r4, %r3
+;   cite %r4, 0 ; trap: int_divz
+;   lhi %r2, 0x7fff
+;   lgr %r3, %r5
+;   xrk %r5, %r2, %r3
+;   nrk %r2, %r5, %r4
+;   cite %r2, -1 ; trap: int_ovf
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -104,12 +173,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -117,6 +195,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r5, %r2
 ;   lbr %r4, %r3
@@ -129,6 +208,20 @@ block0(v0: i8, v1: i8):
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r5, %r2
+;   lbr %r4, %r3
+;   cite %r4, 0 ; trap: int_divz
+;   lhi %r2, 0x7f
+;   lgr %r3, %r5
+;   xrk %r5, %r2, %r3
+;   nrk %r2, %r5, %r4
+;   cite %r2, -1 ; trap: int_ovf
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %sdiv_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -137,12 +230,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r3, %r2
 ;   lhi %r2, 2
 ;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r3, %r2
+;   lhi %r2, 2
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -150,6 +252,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r2
 ;   lghi %r2, 0
@@ -160,6 +263,18 @@ block0(v0: i64, v1: i64):
 ;   dlgr %r2, %r5
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r2
+;   lghi %r2, 0
+;   cgite %r3, 0 ; trap: int_divz
+;   lgr %r4, %r3
+;   lgr %r3, %r5
+;   lgr %r5, %r4
+;   dlgr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -168,6 +283,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lghi %r2, 0
@@ -175,6 +291,15 @@ block0(v0: i64):
 ;   dlgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lghi %r2, 0
+;   lghi %r4, 2
+;   dlgr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -182,6 +307,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r2
 ;   lhi %r2, 0
@@ -192,6 +318,18 @@ block0(v0: i32, v1: i32):
 ;   dlr %r2, %r5
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r2
+;   lhi %r2, 0
+;   cite %r3, 0 ; trap: int_divz
+;   lgr %r4, %r3
+;   lgr %r3, %r5
+;   lgr %r5, %r4
+;   dlr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -200,6 +338,7 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r3, %r2
 ;   lhi %r2, 0
@@ -207,6 +346,15 @@ block0(v0: i32):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r3, %r2
+;   lhi %r2, 0
+;   lhi %r4, 2
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -214,6 +362,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -228,6 +377,22 @@ block0(v0: i16, v1: i16):
 ;   lgr %r2, %r3
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llhr %r3, %r2
+;   lgr %r5, %r4
+;   llhr %r5, %r5
+;   cite %r5, 0 ; trap: int_divz
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %udiv_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -236,6 +401,7 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 0
 ;   lgr %r5, %r4
@@ -245,6 +411,17 @@ block0(v0: i16):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0
+;   lgr %r5, %r4
+;   llhr %r3, %r2
+;   lhi %r4, 2
+;   lgr %r2, %r5
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %udiv_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -252,6 +429,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -266,6 +444,22 @@ block0(v0: i8, v1: i8):
 ;   lgr %r2, %r3
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llcr %r3, %r2
+;   lgr %r5, %r4
+;   llcr %r5, %r5
+;   cite %r5, 0 ; trap: int_divz
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lgr %r2, %r3
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %udiv_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -274,6 +468,7 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 0
 ;   lgr %r5, %r4
@@ -283,6 +478,17 @@ block0(v0: i8):
 ;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0
+;   lgr %r5, %r4
+;   llcr %r3, %r2
+;   lhi %r4, 2
+;   lgr %r2, %r5
+;   dlr %r2, %r4 ; trap: int_divz
+;   lgr %r2, %r3
+;   br %r14
 
 function %srem_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -290,6 +496,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgite %r3, 0
 ;   cghi %r3, -1
@@ -298,6 +505,16 @@ block0(v0: i64, v1: i64):
 ;   locghie %r3, 0
 ;   dsgr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgite %r3, 0 ; trap: int_divz
+;   cghi %r3, -1
+;   lgr %r4, %r3
+;   lgr %r3, %r2
+;   locghie %r3, 0
+;   dsgr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %srem_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -305,6 +522,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   lgfr %r3, %r2
@@ -312,6 +530,15 @@ block0(v0: i32, v1: i32):
 ;   cite %r2, 0
 ;   dsgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   lgfr %r3, %r2
+;   lgr %r2, %r5
+;   cite %r2, 0 ; trap: int_divz
+;   dsgfr %r2, %r2 ; trap: int_divz
+;   br %r14
 
 function %srem_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -319,6 +546,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghr %r5, %r2
 ;   lgr %r2, %r5
@@ -327,6 +555,16 @@ block0(v0: i16, v1: i16):
 ;   lgr %r3, %r2
 ;   dsgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r5, %r2
+;   lgr %r2, %r5
+;   lhr %r4, %r3
+;   cite %r4, 0 ; trap: int_divz
+;   lgr %r3, %r2
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %srem_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -334,6 +572,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r5, %r2
 ;   lgr %r2, %r5
@@ -342,6 +581,16 @@ block0(v0: i8, v1: i8):
 ;   lgr %r3, %r2
 ;   dsgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r5, %r2
+;   lgr %r2, %r5
+;   lbr %r4, %r3
+;   cite %r4, 0 ; trap: int_divz
+;   lgr %r3, %r2
+;   dsgfr %r2, %r4 ; trap: int_divz
+;   br %r14
 
 function %urem_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -349,6 +598,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r2
 ;   lghi %r2, 0
@@ -358,6 +608,17 @@ block0(v0: i64, v1: i64):
 ;   lgr %r5, %r4
 ;   dlgr %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r2
+;   lghi %r2, 0
+;   cgite %r3, 0 ; trap: int_divz
+;   lgr %r4, %r3
+;   lgr %r3, %r5
+;   lgr %r5, %r4
+;   dlgr %r2, %r5 ; trap: int_divz
+;   br %r14
 
 function %urem_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -365,6 +626,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r2
 ;   lhi %r2, 0
@@ -374,6 +636,17 @@ block0(v0: i32, v1: i32):
 ;   lgr %r5, %r4
 ;   dlr %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r2
+;   lhi %r2, 0
+;   cite %r3, 0 ; trap: int_divz
+;   lgr %r4, %r3
+;   lgr %r3, %r5
+;   lgr %r5, %r4
+;   dlr %r2, %r5 ; trap: int_divz
+;   br %r14
 
 function %urem_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -381,6 +654,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -394,6 +668,21 @@ block0(v0: i16, v1: i16):
 ;   dlr %r2, %r5
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llhr %r3, %r2
+;   lgr %r5, %r4
+;   llhr %r5, %r5
+;   cite %r5, 0 ; trap: int_divz
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
 function %urem_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -401,6 +690,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
@@ -414,4 +704,19 @@ block0(v0: i8, v1: i8):
 ;   dlr %r2, %r5
 ;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r8, %r15, 0x40(%r15)
+; block0: ; offset 0x6
+;   lgr %r4, %r3
+;   lhi %r5, 0
+;   lgr %r8, %r5
+;   llcr %r3, %r2
+;   lgr %r5, %r4
+;   llcr %r5, %r5
+;   cite %r5, 0 ; trap: int_divz
+;   lgr %r2, %r8
+;   dlr %r2, %r5 ; trap: int_divz
+;   lmg %r8, %r15, 0x40(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/fence.clif b/cranelift/filetests/filetests/isa/s390x/fence.clif
index 2439ec7a2e..7aaf0dddd6 100644
--- a/cranelift/filetests/filetests/isa/s390x/fence.clif
+++ b/cranelift/filetests/filetests/isa/s390x/fence.clif
@@ -11,7 +11,13 @@ block0:
   return
 }
 
+; VCode:
 ; block0:
 ;   bcr 14, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bnor %r0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif b/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif
index 9bddd04138..b111bf0621 100644
--- a/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -19,6 +20,27 @@ block0(v0: f32):
 ;   wclfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   ic %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vclgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -26,6 +48,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -38,6 +61,28 @@ block0(v0: f32):
 ;   wcfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   ic %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   .byte 0xc3, 0x01
+;   .byte 0x00, 0x00
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vcgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -45,6 +90,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -57,6 +103,27 @@ block0(v0: f32):
 ;   wclfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   be 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vclgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -64,6 +131,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -76,6 +144,28 @@ block0(v0: f32):
 ;   wcfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   bc 0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   bpp 0, -0x31dc, 0x100
+;   lpr %r0, %r0
+;   .byte 0x08, 0x03
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vcgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -83,6 +173,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -95,6 +186,27 @@ block0(v0: f32):
 ;   wclfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   cvb %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vclgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -102,6 +214,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -114,6 +227,28 @@ block0(v0: f32):
 ;   wcfeb %v20, %f0, 0, 5
 ;   vlgvf %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   cvb %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   .byte 0xcf, 0x00
+;   .byte 0x00, 0x01
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   vcgd %v20, %v0, 2, 8, 5
+;   vlgvf %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -121,6 +256,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -134,6 +270,28 @@ block0(v0: f32):
 ;   wclgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   sl %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wclgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -141,6 +299,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -154,6 +313,29 @@ block0(v0: f32):
 ;   wcgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   sl %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   edmk 1(1), 0x700(%r14)
+;   lpr %r0, %r0
+;   .byte 0x08, 0x03
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wcgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -161,6 +343,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -173,6 +356,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r7, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -180,6 +388,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -192,6 +401,30 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r6, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   larl %r6, 0x40000028
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -199,6 +432,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -211,6 +445,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -218,6 +477,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -230,6 +490,30 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   larl %r14, 0x400028
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -237,6 +521,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -249,6 +534,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   la %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -256,6 +566,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -268,6 +579,32 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   la %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   .byte 0xc1, 0xe0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x20
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -275,6 +612,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -287,6 +625,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   ic %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -294,6 +657,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -306,6 +670,32 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   ic %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   .byte 0xc3, 0xe0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_from_uint_i8_f32(i8) -> f32 {
 block0(v0: i8):
@@ -313,11 +703,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llcr %r4, %r2
 ;   vlvgf %v4, %r4, 0
 ;   wcelfb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r4, %r2
+;   vlvgf %v4, %r4, 0
+;   vcdlg %v0, %v4, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_sint_i8_f32(i8) -> f32 {
 block0(v0: i8):
@@ -325,11 +723,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lbr %r4, %r2
 ;   vlvgf %v4, %r4, 0
 ;   wcefb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r4, %r2
+;   vlvgf %v4, %r4, 0
+;   vcdg %v0, %v4, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_uint_i16_f32(i16) -> f32 {
 block0(v0: i16):
@@ -337,11 +743,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   vlvgf %v4, %r4, 0
 ;   wcelfb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   vlvgf %v4, %r4, 0
+;   vcdlg %v0, %v4, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_sint_i16_f32(i16) -> f32 {
 block0(v0: i16):
@@ -349,11 +763,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lhr %r4, %r2
 ;   vlvgf %v4, %r4, 0
 ;   wcefb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r4, %r2
+;   vlvgf %v4, %r4, 0
+;   vcdg %v0, %v4, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_uint_i32_f32(i32) -> f32 {
 block0(v0: i32):
@@ -361,10 +783,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v2, %r2, 0
 ;   wcelfb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v2, %r2, 0
+;   vcdlg %v0, %v2, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_sint_i32_f32(i32) -> f32 {
 block0(v0: i32):
@@ -372,10 +801,17 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v2, %r2, 0
 ;   wcefb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v2, %r2, 0
+;   vcdg %v0, %v2, 2, 8, 4
+;   br %r14
 
 function %fcvt_from_uint_i64_f32(i64) -> f32 {
 block0(v0: i64):
@@ -383,11 +819,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdlgb %f4, %f2, 0, 3
 ;   ledbra %f0, 4, %f4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdlgb %f4, %f2, 0, 3
+;   ledbra %f0, 4, %f4, 0
+;   br %r14
 
 function %fcvt_from_sint_i64_f32(i64) -> f32 {
 block0(v0: i64):
@@ -395,11 +839,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdgb %f4, %f2, 0, 3
 ;   ledbra %f0, 4, %f4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdgb %f4, %f2, 0, 3
+;   ledbra %f0, 4, %f4, 0
+;   br %r14
 
 function %fcvt_from_uint_i8_f64(i8) -> f64 {
 block0(v0: i8):
@@ -407,11 +859,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgcr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgcr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i8_f64(i8) -> f64 {
 block0(v0: i8):
@@ -419,11 +879,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i16_f64(i16) -> f64 {
 block0(v0: i16):
@@ -431,11 +899,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i16_f64(i16) -> f64 {
 block0(v0: i16):
@@ -443,11 +919,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i32_f64(i32) -> f64 {
 block0(v0: i32):
@@ -455,11 +939,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i32_f64(i32) -> f64 {
 block0(v0: i32):
@@ -467,11 +959,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i64_f64(i64) -> f64 {
 block0(v0: i64):
@@ -479,10 +979,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdlgb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdlgb %f0, %f2, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i64_f64(i64) -> f64 {
 block0(v0: i64):
@@ -490,10 +997,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdgb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdgb %f0, %f2, 0, 4
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -501,12 +1015,21 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
 ;   clfi %r2, 256
 ;   lochih %r2, 255
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   clfi %r2, 0x100
+;   lochih %r2, 0xff
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -514,6 +1037,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
@@ -524,6 +1048,18 @@ block0(v0: f32):
 ;   chi %r2, -128
 ;   lochil %r2, -128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   cebr %f0, %f0
+;   lochio %r2, 0
+;   chi %r2, 0x7f
+;   lochih %r2, 0x7f
+;   chi %r2, -0x80
+;   lochil %r2, -0x80
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -531,12 +1067,21 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
 ;   clfi %r2, 65535
 ;   lochih %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   clfi %r2, 0xffff
+;   lochih %r2, -1
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -544,6 +1089,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
@@ -554,6 +1100,18 @@ block0(v0: f32):
 ;   chi %r2, -32768
 ;   lochil %r2, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   cebr %f0, %f0
+;   lochio %r2, 0
+;   chi %r2, 0x7fff
+;   lochih %r2, 0x7fff
+;   chi %r2, -0x8000
+;   lochil %r2, -0x8000
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -561,10 +1119,17 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -572,12 +1137,21 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcfeb %f2, %f0, 0, 5
 ;   vlgvf %r2, %v2, 0
 ;   cebr %f0, %f0
 ;   lochio %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgd %v2, %v0, 2, 8, 5
+;   vlgvf %r2, %v2, 0
+;   cebr %f0, %f0
+;   lochio %r2, 0
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -585,11 +1159,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wclgdb %f4, %f2, 0, 5
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wclgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -597,6 +1179,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wcgdb %f4, %f2, 0, 5
@@ -604,6 +1187,15 @@ block0(v0: f32):
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wcgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   cebr %f0, %f0
+;   locghio %r2, 0
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -611,12 +1203,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   clgfi %r2, 0x100
+;   locghih %r2, 0xff
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -624,6 +1225,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -634,6 +1236,18 @@ block0(v0: f64):
 ;   cghi %r2, -128
 ;   locghil %r2, -128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7f
+;   locghih %r2, 0x7f
+;   cghi %r2, -0x80
+;   locghil %r2, -0x80
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -641,12 +1255,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   clgfi %r2, 0xffff
+;   locghih %r2, -1
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -654,6 +1277,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -664,6 +1288,18 @@ block0(v0: f64):
 ;   cghi %r2, -32768
 ;   locghil %r2, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7fff
+;   locghih %r2, 0x7fff
+;   cghi %r2, -0x8000
+;   locghil %r2, -0x8000
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -671,6 +1307,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -678,6 +1315,15 @@ block0(v0: f64):
 ;   clgr %r2, %r4
 ;   locgrh %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   llilf %r4, 0xffffffff
+;   clgr %r2, %r4
+;   locgrh %r2, %r4
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -685,6 +1331,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -697,6 +1344,20 @@ block0(v0: f64):
 ;   cgr %r2, %r4
 ;   locgrl %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   lgfi %r3, 0x7fffffff
+;   cgr %r2, %r3
+;   locgrh %r2, %r3
+;   lgfi %r4, -0x80000000
+;   cgr %r2, %r4
+;   locgrl %r2, %r4
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -704,10 +1365,17 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -715,10 +1383,19 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/floating-point.clif b/cranelift/filetests/filetests/isa/s390x/floating-point.clif
index eee92024bd..0181ffdd35 100644
--- a/cranelift/filetests/filetests/isa/s390x/floating-point.clif
+++ b/cranelift/filetests/filetests/isa/s390x/floating-point.clif
@@ -14,9 +14,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.f32 0 ; le %f0, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   le %f0, 0(%r1)
+;   br %r14
 
 function %f64const_zero() -> f64 {
 block0:
@@ -24,9 +33,20 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f0, 0(%r1)
+;   br %r14
 
 function %f32const_one() -> f32 {
 block0:
@@ -34,9 +54,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.f32 1 ; le %f0, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   sur %f8, %f0
+;   .byte 0x00, 0x00
+;   le %f0, 0(%r1)
+;   br %r14
 
 function %f64const_one() -> f64 {
 block0:
@@ -44,9 +73,20 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.f64 1 ; ld %f0, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   sur %f15, %f0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f0, 0(%r1)
+;   br %r14
 
 function %fadd_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -54,9 +94,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   aebr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   aebr %f0, %f2
+;   br %r14
 
 function %fadd_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -64,9 +110,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   adbr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   adbr %f0, %f2
+;   br %r14
 
 function %fsub_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -74,9 +126,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sebr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sebr %f0, %f2
+;   br %r14
 
 function %fsub_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -84,9 +142,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sdbr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sdbr %f0, %f2
+;   br %r14
 
 function %fmul_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -94,9 +158,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   meebr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   meebr %f0, %f2
+;   br %r14
 
 function %fmul_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -104,9 +174,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   mdbr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mdbr %f0, %f2
+;   br %r14
 
 function %fdiv_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -114,9 +190,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   debr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   debr %f0, %f2
+;   br %r14
 
 function %fdiv_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -124,9 +206,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   ddbr %f0, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ddbr %f0, %f2
+;   br %r14
 
 function %fmin_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -134,9 +222,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfminsb %f0, %f0, %f2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfminsb %f0, %f0, %f2, 1
+;   br %r14
 
 function %fmin_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -144,9 +238,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmindb %f0, %f0, %f2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmindb %f0, %f0, %f2, 1
+;   br %r14
 
 function %fmax_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -154,9 +254,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmaxsb %f0, %f0, %f2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmaxsb %f0, %f0, %f2, 1
+;   br %r14
 
 function %fmax_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -164,9 +270,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmaxdb %f0, %f0, %f2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmaxdb %f0, %f0, %f2, 1
+;   br %r14
 
 function %fmin_pseudo_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -174,9 +286,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfminsb %f0, %f0, %f2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfminsb %f0, %f0, %f2, 3
+;   br %r14
 
 function %fmin_pseudo_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -184,9 +302,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmindb %f0, %f0, %f2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmindb %f0, %f0, %f2, 3
+;   br %r14
 
 function %fmax_pseudo_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -194,9 +318,15 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmaxsb %f0, %f0, %f2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmaxsb %f0, %f0, %f2, 3
+;   br %r14
 
 function %fmax_pseudo_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -204,9 +334,15 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   wfmaxdb %f0, %f0, %f2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmaxdb %f0, %f0, %f2, 3
+;   br %r14
 
 function %sqrt_f32(f32) -> f32 {
 block0(v0: f32):
@@ -214,9 +350,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sqebr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqebr %f0, %f0
+;   br %r14
 
 function %sqrt_f64(f64) -> f64 {
 block0(v0: f64):
@@ -224,9 +366,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   sqdbr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sqdbr %f0, %f0
+;   br %r14
 
 function %fabs_f32(f32) -> f32 {
 block0(v0: f32):
@@ -234,9 +382,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lpebr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lpebr %f0, %f0
+;   br %r14
 
 function %fabs_f64(f64) -> f64 {
 block0(v0: f64):
@@ -244,9 +398,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lpdbr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lpdbr %f0, %f0
+;   br %r14
 
 function %fneg_f32(f32) -> f32 {
 block0(v0: f32):
@@ -254,9 +414,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcebr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcebr %f0, %f0
+;   br %r14
 
 function %fneg_f64(f64) -> f64 {
 block0(v0: f64):
@@ -264,9 +430,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lcdbr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcdbr %f0, %f0
+;   br %r14
 
 function %fpromote_f32(f32) -> f64 {
 block0(v0: f32):
@@ -274,9 +446,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f0, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f0, %f0
+;   br %r14
 
 function %fdemote_f64(f64) -> f32 {
 block0(v0: f64):
@@ -284,9 +462,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ledbra %f0, 0, %f0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ledbr %f0, %f0
+;   br %r14
 
 function %ceil_f32(f32) -> f32 {
 block0(v0: f32):
@@ -294,9 +478,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fiebr %f0, 6, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fiebr %f0, 6, %f0
+;   br %r14
 
 function %ceil_f64(f64) -> f64 {
 block0(v0: f64):
@@ -304,9 +494,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fidbr %f0, 6, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fidbr %f0, 6, %f0
+;   br %r14
 
 function %floor_f32(f32) -> f32 {
 block0(v0: f32):
@@ -314,9 +510,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fiebr %f0, 7, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fiebr %f0, 7, %f0
+;   br %r14
 
 function %floor_f64(f64) -> f64 {
 block0(v0: f64):
@@ -324,9 +526,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fidbr %f0, 7, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fidbr %f0, 7, %f0
+;   br %r14
 
 function %trunc_f32(f32) -> f32 {
 block0(v0: f32):
@@ -334,9 +542,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fiebr %f0, 5, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fiebr %f0, 5, %f0
+;   br %r14
 
 function %trunc_f64(f64) -> f64 {
 block0(v0: f64):
@@ -344,9 +558,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fidbr %f0, 5, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fidbr %f0, 5, %f0
+;   br %r14
 
 function %nearest_f32(f32) -> f32 {
 block0(v0: f32):
@@ -354,9 +574,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fiebr %f0, 4, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fiebr %f0, 4, %f0
+;   br %r14
 
 function %nearest_f64(f64) -> f64 {
 block0(v0: f64):
@@ -364,9 +590,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   fidbr %f0, 4, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   fidbr %f0, 4, %f0
+;   br %r14
 
 function %fma_f32(f32, f32, f32) -> f32 {
 block0(v0: f32, v1: f32, v2: f32):
@@ -374,9 +606,15 @@ block0(v0: f32, v1: f32, v2: f32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   wfmasb %f0, %f0, %f2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmasb %f0, %f0, %f2, %f4
+;   br %r14
 
 function %fma_f64(f64, f64, f64) -> f64 {
 block0(v0: f64, v1: f64, v2: f64):
@@ -384,9 +622,15 @@ block0(v0: f64, v1: f64, v2: f64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   wfmadb %f0, %f0, %f2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wfmadb %f0, %f0, %f2, %f4
+;   br %r14
 
 function %fcopysign_f32(f32, f32) -> f32 {
 block0(v0: f32, v1: f32):
@@ -394,10 +638,19 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.f32 NaN ; le %f3, 0(%r1)
 ;   vsel %v0, %v0, %v2, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   su %f15, 0xfff(%r15, %r15)
+;   le %f3, 0(%r1)
+;   vsel %v0, %v0, %v2, %v3
+;   br %r14
 
 function %fcopysign_f64(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -405,10 +658,21 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.f64 NaN ; ld %f3, 0(%r1)
 ;   vsel %v0, %v0, %v2, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   su %f15, 0xfff(%r15, %r15)
+;   .byte 0xff, 0xff
+;   .byte 0xff, 0xff
+;   ld %f3, 0(%r1)
+;   vsel %v0, %v0, %v2, %v3
+;   br %r14
 
 function %fcvt_to_uint_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -416,6 +680,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -429,6 +694,28 @@ block0(v0: f32):
 ;   wclgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   ic %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wclgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -436,6 +723,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -449,6 +737,29 @@ block0(v0: f32):
 ;   wcgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   ic %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   .byte 0xc3, 0x01
+;   .byte 0x00, 0x00
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wcgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -456,6 +767,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -469,6 +781,28 @@ block0(v0: f32):
 ;   wclgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   be 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wclgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -476,6 +810,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -489,6 +824,29 @@ block0(v0: f32):
 ;   wcgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   bc 0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   bpp 0, -0x31dc, 0x100
+;   lpr %r0, %r0
+;   .byte 0x08, 0x03
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wcgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -496,6 +854,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -509,6 +868,28 @@ block0(v0: f32):
 ;   wclgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   cvb %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wclgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -516,6 +897,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -529,6 +911,29 @@ block0(v0: f32):
 ;   wcgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   cvb %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   .byte 0xcf, 0x00
+;   .byte 0x00, 0x01
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wcgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_uint_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -536,6 +941,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -549,6 +955,28 @@ block0(v0: f32):
 ;   wclgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   sl %r8, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   icm %r8, 0, 0
+;   vlef %v16, 0(%r1), 0
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wclgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_sint_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -556,6 +984,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
@@ -569,6 +998,29 @@ block0(v0: f32):
 ;   wcgdb %v22, %v20, 0, 5
 ;   vlgvg %r2, %v22, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cebr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x12
+;   sl %r0, 0
+;   le %f4, 0(%r1)
+;   cebr %f0, %f4
+;   jnhe 0x20
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x28
+;   edmk 1(1), 0x700(%r14)
+;   lpr %r0, %r0
+;   .byte 0x08, 0x03
+;   wfcsb %f0, %v16
+;   jnle 0x3a
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wldeb %v20, %f0
+;   wcgdb %v22, %v20, 0, 5
+;   vlgvg %r2, %v22, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -576,6 +1028,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -588,6 +1041,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r7, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -595,6 +1073,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -607,6 +1086,30 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r6, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   larl %r6, 0x40000028
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -614,6 +1117,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -626,6 +1130,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -633,6 +1162,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -645,6 +1175,30 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   sth %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   larl %r14, 0x400028
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -652,6 +1206,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -664,6 +1219,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   la %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -671,6 +1251,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -683,6 +1264,32 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   la %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   .byte 0xc1, 0xe0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x20
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_uint_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -690,6 +1297,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -702,6 +1310,31 @@ block0(v0: f64):
 ;   wclgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   ic %r15, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   icm %r15, 0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wclgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_to_sint_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -709,6 +1342,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
@@ -721,6 +1355,32 @@ block0(v0: f64):
 ;   wcgdb %v20, %f0, 0, 5
 ;   vlgvg %r2, %v20, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cdbr %f0, %f0
+;   jno 0xa
+;   .byte 0x00, 0x00 ; trap: bad_toint
+;   bras %r1, 0x16
+;   ic %r14, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   cdbr %f0, %f4
+;   jnhe 0x24
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   bras %r1, 0x30
+;   .byte 0xc3, 0xe0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   vleg %v16, 0(%r1), 0
+;   wfcdb %f0, %v16
+;   jnle 0x42
+;   .byte 0x00, 0x00 ; trap: int_ovf
+;   wcgdb %v20, %f0, 0, 5
+;   vlgvg %r2, %v20, 0
+;   br %r14
 
 function %fcvt_from_uint_i8_f32(i8) -> f32 {
 block0(v0: i8):
@@ -728,12 +1388,21 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgcr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgcr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_sint_i8_f32(i8) -> f32 {
 block0(v0: i8):
@@ -741,12 +1410,21 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_uint_i16_f32(i16) -> f32 {
 block0(v0: i16):
@@ -754,12 +1432,21 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_sint_i16_f32(i16) -> f32 {
 block0(v0: i16):
@@ -767,12 +1454,21 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_uint_i32_f32(i32) -> f32 {
 block0(v0: i32):
@@ -780,12 +1476,21 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_sint_i32_f32(i32) -> f32 {
 block0(v0: i32):
@@ -793,12 +1498,21 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f6, %f4, 0, 3
 ;   ledbra %f0, 4, %f6, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f6, %f4, 0, 3
+;   ledbra %f0, 4, %f6, 0
+;   br %r14
 
 function %fcvt_from_uint_i64_f32(i64) -> f32 {
 block0(v0: i64):
@@ -806,11 +1520,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdlgb %f4, %f2, 0, 3
 ;   ledbra %f0, 4, %f4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdlgb %f4, %f2, 0, 3
+;   ledbra %f0, 4, %f4, 0
+;   br %r14
 
 function %fcvt_from_sint_i64_f32(i64) -> f32 {
 block0(v0: i64):
@@ -818,11 +1540,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdgb %f4, %f2, 0, 3
 ;   ledbra %f0, 4, %f4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdgb %f4, %f2, 0, 3
+;   ledbra %f0, 4, %f4, 0
+;   br %r14
 
 function %fcvt_from_uint_i8_f64(i8) -> f64 {
 block0(v0: i8):
@@ -830,11 +1560,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgcr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgcr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i8_f64(i8) -> f64 {
 block0(v0: i8):
@@ -842,11 +1580,19 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgbr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgbr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i16_f64(i16) -> f64 {
 block0(v0: i16):
@@ -854,11 +1600,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i16_f64(i16) -> f64 {
 block0(v0: i16):
@@ -866,11 +1620,19 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i32_f64(i32) -> f64 {
 block0(v0: i32):
@@ -878,11 +1640,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdlgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i32_f64(i32) -> f64 {
 block0(v0: i32):
@@ -890,11 +1660,19 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfr %r4, %r2
 ;   ldgr %f4, %r4
 ;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfr %r4, %r2
+;   ldgr %f4, %r4
+;   wcdgb %f0, %f4, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i64_f64(i64) -> f64 {
 block0(v0: i64):
@@ -902,10 +1680,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdlgb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdlgb %f0, %f2, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i64_f64(i64) -> f64 {
 block0(v0: i64):
@@ -913,10 +1698,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   wcdgb %f0, %f2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   wcdgb %f0, %f2, 0, 4
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -924,6 +1716,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wclgdb %f4, %f2, 0, 5
@@ -931,6 +1724,15 @@ block0(v0: f32):
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wclgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   clgfi %r2, 0x100
+;   locghih %r2, 0xff
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i8(f32) -> i8 {
 block0(v0: f32):
@@ -938,6 +1740,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wcgdb %f4, %f2, 0, 5
@@ -949,6 +1752,19 @@ block0(v0: f32):
 ;   cghi %r2, -128
 ;   locghil %r2, -128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wcgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   cebr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7f
+;   locghih %r2, 0x7f
+;   cghi %r2, -0x80
+;   locghil %r2, -0x80
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -956,6 +1772,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wclgdb %f4, %f2, 0, 5
@@ -963,6 +1780,15 @@ block0(v0: f32):
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wclgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   clgfi %r2, 0xffff
+;   locghih %r2, -1
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i16(f32) -> i16 {
 block0(v0: f32):
@@ -970,6 +1796,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wcgdb %f4, %f2, 0, 5
@@ -981,6 +1808,19 @@ block0(v0: f32):
 ;   cghi %r2, -32768
 ;   locghil %r2, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wcgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   cebr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7fff
+;   locghih %r2, 0x7fff
+;   cghi %r2, -0x8000
+;   locghil %r2, -0x8000
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -988,6 +1828,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wclgdb %f4, %f2, 0, 5
@@ -996,6 +1837,16 @@ block0(v0: f32):
 ;   clgr %r2, %r3
 ;   locgrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wclgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   llilf %r3, 0xffffffff
+;   clgr %r2, %r3
+;   locgrh %r2, %r3
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -1003,6 +1854,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wcgdb %f4, %f2, 0, 5
@@ -1016,6 +1868,21 @@ block0(v0: f32):
 ;   cgr %r2, %r3
 ;   locgrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wcgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   cebr %f0, %f0
+;   locghio %r2, 0
+;   lgfi %r5, 0x7fffffff
+;   cgr %r2, %r5
+;   locgrh %r2, %r5
+;   lgfi %r3, -0x80000000
+;   cgr %r2, %r3
+;   locgrl %r2, %r3
+;   br %r14
 
 function %fcvt_to_uint_sat_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -1023,11 +1890,19 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wclgdb %f4, %f2, 0, 5
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wclgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   br %r14
 
 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 {
 block0(v0: f32):
@@ -1035,6 +1910,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldebr %f2, %f0
 ;   wcgdb %f4, %f2, 0, 5
@@ -1042,6 +1918,15 @@ block0(v0: f32):
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldebr %f2, %f0
+;   wcgdb %f4, %f2, 0, 5
+;   lgdr %r2, %f4
+;   cebr %f0, %f0
+;   locghio %r2, 0
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -1049,12 +1934,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   clgfi %r2, 0x100
+;   locghih %r2, 0xff
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i8(f64) -> i8 {
 block0(v0: f64):
@@ -1062,6 +1956,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -1072,6 +1967,18 @@ block0(v0: f64):
 ;   cghi %r2, -128
 ;   locghil %r2, -128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7f
+;   locghih %r2, 0x7f
+;   cghi %r2, -0x80
+;   locghil %r2, -0x80
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -1079,12 +1986,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   clgfi %r2, 0xffff
+;   locghih %r2, -1
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i16(f64) -> i16 {
 block0(v0: f64):
@@ -1092,6 +2008,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -1102,6 +2019,18 @@ block0(v0: f64):
 ;   cghi %r2, -32768
 ;   locghil %r2, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   cghi %r2, 0x7fff
+;   locghih %r2, 0x7fff
+;   cghi %r2, -0x8000
+;   locghil %r2, -0x8000
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -1109,6 +2038,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -1116,6 +2046,15 @@ block0(v0: f64):
 ;   clgr %r2, %r4
 ;   locgrh %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   llilf %r4, 0xffffffff
+;   clgr %r2, %r4
+;   locgrh %r2, %r4
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 {
 block0(v0: f64):
@@ -1123,6 +2062,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
@@ -1135,6 +2075,20 @@ block0(v0: f64):
 ;   cgr %r2, %r4
 ;   locgrl %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   lgfi %r3, 0x7fffffff
+;   cgr %r2, %r3
+;   locgrh %r2, %r3
+;   lgfi %r4, -0x80000000
+;   cgr %r2, %r4
+;   locgrl %r2, %r4
+;   br %r14
 
 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -1142,10 +2096,17 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wclgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wclgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   br %r14
 
 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -1153,12 +2114,21 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   wcgdb %f2, %f0, 0, 5
 ;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   wcgdb %f2, %f0, 0, 5
+;   lgdr %r2, %f2
+;   cdbr %f0, %f0
+;   locghio %r2, 0
+;   br %r14
 
 function %bitcast_i64_f64(i64) -> f64 {
 block0(v0: i64):
@@ -1166,9 +2136,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f0, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f0, %r2
+;   br %r14
 
 function %bitcast_f64_i64(f64) -> i64 {
 block0(v0: f64):
@@ -1176,9 +2152,15 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgdr %r2, %f0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgdr %r2, %f0
+;   br %r14
 
 function %bitcast_i32_f32(i32) -> f32 {
 block0(v0: i32):
@@ -1186,9 +2168,15 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v0, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v0, %r2, 0
+;   br %r14
 
 function %bitcast_f32_i32(f32) -> i32 {
 block0(v0: f32):
@@ -1196,9 +2184,15 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r2, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r2, %v0, 0
+;   br %r14
 
 function %bitcast_f32_f32(f32) -> f32 {
 block0(v0: f32):
@@ -1206,8 +2200,13 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_f64_f64(f64) -> f64 {
 block0(v0: f64):
@@ -1215,6 +2214,11 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/fp_sp_pc.clif b/cranelift/filetests/filetests/isa/s390x/fp_sp_pc.clif
index 0de44e6a13..62a8425e08 100644
--- a/cranelift/filetests/filetests/isa/s390x/fp_sp_pc.clif
+++ b/cranelift/filetests/filetests/isa/s390x/fp_sp_pc.clif
@@ -8,6 +8,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   lgr %r1, %r15
 ;   aghi %r15, -160
@@ -17,6 +18,16 @@ block0:
 ;   lg %r2, 0(%r15)
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   lgr %r1, %r15
+;   aghi %r15, -0xa0
+;   stg %r1, 0(%r15)
+; block0: ; offset 0x14
+;   lg %r2, 0(%r15)
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %sp() -> i64 {
 block0:
@@ -24,6 +35,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   lgr %r1, %r15
 ;   aghi %r15, -160
@@ -33,6 +45,16 @@ block0:
 ;   lgr %r2, %r15
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   lgr %r1, %r15
+;   aghi %r15, -0xa0
+;   stg %r1, 0(%r15)
+; block0: ; offset 0x14
+;   lgr %r2, %r15
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %return_address() -> i64 {
 block0:
@@ -40,6 +62,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   lgr %r1, %r15
 ;   aghi %r15, -160
@@ -49,4 +72,14 @@ block0:
 ;   lg %r2, 272(%r15)
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   lgr %r1, %r15
+;   aghi %r15, -0xa0
+;   stg %r1, 0(%r15)
+; block0: ; offset 0x14
+;   lg %r2, 0x110(%r15)
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/fpmem-arch13.clif b/cranelift/filetests/filetests/isa/s390x/fpmem-arch13.clif
index 736d72b7a1..9fedc9ce21 100644
--- a/cranelift/filetests/filetests/isa/s390x/fpmem-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/fpmem-arch13.clif
@@ -7,9 +7,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v0, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x00
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   br %r14
 
 function %load_f32_little(i64) -> f32 {
 block0(v0: i64):
@@ -17,9 +25,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v0, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x00
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x03
+;   br %r14
 
 function %store_f64_little(f64, i64) {
 block0(v0: f64, v1: i64):
@@ -27,9 +43,17 @@ block0(v0: f64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v0, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x00
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x0a
+;   br %r14
 
 function %store_f32_little(f32, i64) {
 block0(v0: f32, v1: i64):
@@ -37,7 +61,15 @@ block0(v0: f32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v0, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x00
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x0b
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/fpmem.clif b/cranelift/filetests/filetests/isa/s390x/fpmem.clif
index 9091592e30..1eb907d03d 100644
--- a/cranelift/filetests/filetests/isa/s390x/fpmem.clif
+++ b/cranelift/filetests/filetests/isa/s390x/fpmem.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f0, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f0, 0(%r2)
+;   br %r14
 
 function %load_f32(i64) -> f32 {
 block0(v0: i64):
@@ -17,9 +23,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   le %f0, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   le %f0, 0(%r2)
+;   br %r14
 
 function %load_f64_little(i64) -> f64 {
 block0(v0: i64):
@@ -27,10 +39,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f0, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f0, %r4
+;   br %r14
 
 function %load_f32_little(i64) -> f32 {
 block0(v0: i64):
@@ -38,10 +57,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   vlvgf %v0, %r4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   vlvgf %v0, %r4, 0
+;   br %r14
 
 function %store_f64(f64, i64) {
 block0(v0: f64, v1: i64):
@@ -49,9 +75,15 @@ block0(v0: f64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   std %f0, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   std %f0, 0(%r2)
+;   br %r14
 
 function %store_f32(f32, i64) {
 block0(v0: f32, v1: i64):
@@ -59,9 +91,15 @@ block0(v0: f32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   ste %f0, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ste %f0, 0(%r2)
+;   br %r14
 
 function %store_f64_little(f64, i64) {
 block0(v0: f64, v1: i64):
@@ -69,10 +107,17 @@ block0(v0: f64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lgdr %r5, %f0
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgdr %r5, %f0
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %store_f32_little(f32, i64) {
 block0(v0: f32, v1: i64):
@@ -80,8 +125,15 @@ block0(v0: f32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v0, 0
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v0, 0
+;   strv %r5, 0(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif b/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif
index 92796cec2a..517c6edf0e 100644
--- a/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif
+++ b/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif
@@ -7,6 +7,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -14,6 +15,15 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vceqgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %icmp_ne_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -21,6 +31,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -28,6 +39,15 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vceqgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %icmp_slt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -35,6 +55,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -42,6 +63,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vecg %v1, %v3
+;   jne 0x1c
+;   vchlgs %v5, %v3, %v1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -49,6 +81,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -56,6 +89,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vecg %v3, %v1
+;   jne 0x1c
+;   vchlgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_sle_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -63,6 +107,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -70,6 +115,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochinl %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vecg %v3, %v1
+;   jne 0x1c
+;   vchlgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochinl %r2, 1
+;   br %r14
 
 function %icmp_sge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -77,6 +133,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -84,6 +141,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochinl %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   vecg %v1, %v3
+;   jne 0x1c
+;   vchlgs %v5, %v3, %v1
+;   lhi %r2, 0
+;   lochinl %r2, 1
+;   br %r14
 
 function %icmp_ult_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -91,6 +159,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -98,6 +167,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   veclg %v1, %v3
+;   jne 0x1c
+;   vchlgs %v5, %v3, %v1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -105,6 +185,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -112,6 +193,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   veclg %v3, %v1
+;   jne 0x1c
+;   vchlgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ule_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -119,6 +211,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -126,6 +219,17 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochinl %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   veclg %v3, %v1
+;   jne 0x1c
+;   vchlgs %v5, %v1, %v3
+;   lhi %r2, 0
+;   lochinl %r2, 1
+;   br %r14
 
 function %icmp_uge_i128(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -133,6 +237,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vl %v3, 0(%r3)
@@ -140,4 +245,15 @@ block0(v0: i128, v1: i128):
 ;   lhi %r2, 0
 ;   lochinl %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vl %v3, 0(%r3)
+;   veclg %v1, %v3
+;   jne 0x1c
+;   vchlgs %v5, %v3, %v1
+;   lhi %r2, 0
+;   lochinl %r2, 1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/icmp.clif b/cranelift/filetests/filetests/isa/s390x/icmp.clif
index 6a7fa2594d..6dd667391d 100644
--- a/cranelift/filetests/filetests/isa/s390x/icmp.clif
+++ b/cranelift/filetests/filetests/isa/s390x/icmp.clif
@@ -7,11 +7,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_ext32(i64, i32) -> i8 {
 block0(v0: i64, v1: i32):
@@ -20,11 +28,19 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cgfr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgfr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_imm16(i64) -> i8 {
 block0(v0: i64):
@@ -33,11 +49,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cghi %r2, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r2, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_imm32(i64) -> i8 {
 block0(v0: i64):
@@ -46,11 +70,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgfi %r2, 32768
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgfi %r2, 0x8000
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_mem(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -59,11 +91,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cg %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cg %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_sym(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -74,11 +114,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cgrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_mem_ext16(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -87,11 +135,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cgh %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgh %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_sym_ext16(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -102,11 +158,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cghrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_mem_ext32(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -115,11 +179,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cgf %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgf %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i64_sym_ext32(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -130,11 +202,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cgfrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgfrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32(i32, i32) -> i8 {
 block0(v0: i32, v1: i32):
@@ -142,11 +222,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_imm16(i32) -> i8 {
 block0(v0: i32):
@@ -155,11 +243,19 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   chi %r2, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chi %r2, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_imm(i32) -> i8 {
 block0(v0: i32):
@@ -168,11 +264,19 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cfi %r2, 32768
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cfi %r2, 0x8000
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_mem(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -181,11 +285,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   c %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   c %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_memoff(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -194,11 +306,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cy %r2, 4096(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cy %r2, 0x1000(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_sym(i32) -> i8 {
   gv0 = symbol colocated %sym
@@ -209,11 +329,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   crl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   crl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_mem_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -222,11 +350,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   ch %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ch %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_memoff_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -235,11 +371,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   chy %r2, 4096(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chy %r2, 0x1000(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i32_sym_ext16(i32) -> i8 {
   gv0 = symbol colocated %sym
@@ -250,11 +394,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   chrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   chrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i16(i16, i16) -> i8 {
 block0(v0: i16, v1: i16):
@@ -262,6 +414,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   lhr %r3, %r3
@@ -269,6 +422,15 @@ block0(v0: i16, v1: i16):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   lhr %r3, %r3
+;   cr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i16_imm(i16) -> i8 {
 block0(v0: i16):
@@ -277,12 +439,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r4, %r2
 ;   chi %r4, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r4, %r2
+;   chi %r4, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i16_mem(i16, i64) -> i8 {
 block0(v0: i16, v1: i64):
@@ -291,12 +462,21 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   ch %r5, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   ch %r5, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i16_sym(i16) -> i8 {
   gv0 = symbol colocated %sym
@@ -307,12 +487,21 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lhr %r4, %r2
 ;   chrl %r4, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r4, %r2
+;   chrl %r4, 4 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -320,6 +509,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   lbr %r3, %r3
@@ -327,6 +517,15 @@ block0(v0: i8, v1: i8):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   lbr %r3, %r3
+;   cr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -335,12 +534,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r4, %r2
 ;   chi %r4, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r4, %r2
+;   chi %r4, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_slt_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -349,6 +557,7 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   lb %r3, 0(%r3)
@@ -356,6 +565,15 @@ block0(v0: i8, v1: i64):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   lb %r3, 0(%r3)
+;   cr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -363,11 +581,19 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_ext32(i64, i32) -> i8 {
 block0(v0: i64, v1: i32):
@@ -376,11 +602,19 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clgfr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_imm(i64) -> i8 {
 block0(v0: i64):
@@ -389,11 +623,19 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clgfi %r2, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfi %r2, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_mem(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -402,11 +644,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clg %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clg %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_sym(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -417,11 +667,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clgrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_mem_ext32(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -430,11 +688,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clgf %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgf %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_sym_ext32(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -445,11 +711,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clgfrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_mem_ext16(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
@@ -458,12 +732,21 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llgh %r3, 0(%r3)
 ;   clgr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgh %r3, 0(%r3)
+;   clgr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i64_sym_ext16(i64) -> i8 {
   gv0 = symbol colocated %sym
@@ -474,11 +757,19 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clghrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clghrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32(i32, i32) -> i8 {
 block0(v0: i32, v1: i32):
@@ -486,11 +777,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_imm(i32) -> i8 {
 block0(v0: i32):
@@ -499,11 +798,19 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clfi %r2, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clfi %r2, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_mem(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -512,11 +819,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cl %r2, 0(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cl %r2, 0(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_memoff(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -525,11 +840,19 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   cly %r2, 4096(%r3)
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cly %r2, 0x1000(%r3)
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_sym(i32) -> i8 {
   gv0 = symbol colocated %sym
@@ -540,11 +863,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_mem_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
@@ -553,12 +884,21 @@ block0(v0: i32, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llh %r3, 0(%r3)
 ;   clr %r2, %r3
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r3, 0(%r3)
+;   clr %r2, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i32_sym_ext16(i32) -> i8 {
   gv0 = symbol colocated %sym
@@ -569,11 +909,19 @@ block0(v0: i32):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   clhrl %r2, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clhrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i16(i16, i16) -> i8 {
 block0(v0: i16, v1: i16):
@@ -581,6 +929,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   llhr %r3, %r3
@@ -588,6 +937,15 @@ block0(v0: i16, v1: i16):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   llhr %r3, %r3
+;   clr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i16_imm(i16) -> i8 {
 block0(v0: i16):
@@ -596,12 +954,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   clfi %r4, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   clfi %r4, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i16_mem(i16, i64) -> i8 {
 block0(v0: i16, v1: i64):
@@ -610,6 +977,7 @@ block0(v0: i16, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   llh %r3, 0(%r3)
@@ -617,6 +985,15 @@ block0(v0: i16, v1: i64):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   llh %r3, 0(%r3)
+;   clr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i16_mem(i16) -> i8 {
   gv0 = symbol colocated %sym
@@ -627,12 +1004,21 @@ block0(v0: i16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   clhrl %r4, %sym + 0
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   clhrl %r4, 4 ; reloc_external PCRel32Dbl %sym 2
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -640,6 +1026,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   llcr %r3, %r3
@@ -647,6 +1034,15 @@ block0(v0: i8, v1: i8):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   llcr %r3, %r3
+;   clr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -655,12 +1051,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r4, %r2
 ;   clfi %r4, 1
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r4, %r2
+;   clfi %r4, 1
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
 function %icmp_ult_i8_mem(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -669,6 +1074,7 @@ block0(v0: i8, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   llc %r3, 0(%r3)
@@ -676,4 +1082,13 @@ block0(v0: i8, v1: i64):
 ;   lhi %r2, 0
 ;   lochil %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   llc %r3, 0(%r3)
+;   clr %r5, %r3
+;   lhi %r2, 0
+;   lochil %r2, 1
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/jumptable.clif b/cranelift/filetests/filetests/isa/s390x/jumptable.clif
index e40aa747f3..215ff19658 100644
--- a/cranelift/filetests/filetests/isa/s390x/jumptable.clif
+++ b/cranelift/filetests/filetests/isa/s390x/jumptable.clif
@@ -26,6 +26,7 @@ block5(v5: i32):
   return v6
 }
 
+; VCode:
 ; block0:
 ;   llgfr %r3, %r2
 ;   clgfi %r3, 3
@@ -55,4 +56,37 @@ block5(v5: i32):
 ; block9:
 ;   ar %r2, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfr %r3, %r2
+;   clgfi %r3, 3
+;   jghe 0x30
+;   sllg %r3, %r3, 2
+;   larl %r1, 0x24
+;   agf %r1, 0(%r3, %r1)
+;   br %r1
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x16
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x20
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x2a
+; block1: ; offset 0x30
+;   lhi %r5, 4
+; block2: ; offset 0x34
+;   jg 0x52
+; block3: ; offset 0x3a
+;   lhi %r5, 1
+; block4: ; offset 0x3e
+;   jg 0x52
+; block5: ; offset 0x44
+;   lhi %r5, 2
+; block6: ; offset 0x48
+;   jg 0x52
+; block7: ; offset 0x4e
+;   lhi %r5, 3
+; block8: ; offset 0x52
+;   ar %r2, %r5
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/leaf.clif b/cranelift/filetests/filetests/isa/s390x/leaf.clif
index b1e5786971..92c0d1074c 100644
--- a/cranelift/filetests/filetests/isa/s390x/leaf.clif
+++ b/cranelift/filetests/filetests/isa/s390x/leaf.clif
@@ -10,6 +10,11 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/leaf_with_preserve_frame_pointers.clif b/cranelift/filetests/filetests/isa/s390x/leaf_with_preserve_frame_pointers.clif
index 82834df6de..d7a1de8204 100644
--- a/cranelift/filetests/filetests/isa/s390x/leaf_with_preserve_frame_pointers.clif
+++ b/cranelift/filetests/filetests/isa/s390x/leaf_with_preserve_frame_pointers.clif
@@ -10,6 +10,7 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   lgr %r1, %r15
 ;   aghi %r15, -160
@@ -18,4 +19,13 @@ block0(v0: i64):
 ; block0:
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   lgr %r1, %r15
+;   aghi %r15, -0xa0
+;   stg %r1, 0(%r15)
+; block0: ; offset 0x14
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/load-little.clif b/cranelift/filetests/filetests/isa/s390x/load-little.clif
index e3cc953376..516ea8c410 100644
--- a/cranelift/filetests/filetests/isa/s390x/load-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/load-little.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r2, 0(%r2)
+;   br %r14
 
 function %load_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -19,9 +25,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvg %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvg %r2, 0(%r1)
+;   br %r14
 
 function %uload8_i64(i64) -> i64 {
 block0(v0: i64):
@@ -29,9 +42,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i64(i64) -> i64 {
 block0(v0: i64):
@@ -39,9 +58,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgb %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i64(i64) -> i64 {
 block0(v0: i64):
@@ -49,10 +74,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   llghr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   llghr %r2, %r4
+;   br %r14
 
 function %uload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -62,10 +94,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   llghr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   llghr %r2, %r2
+;   br %r14
 
 function %sload16_i64(i64) -> i64 {
 block0(v0: i64):
@@ -73,10 +113,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   lghr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   lghr %r2, %r4
+;   br %r14
 
 function %sload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -86,10 +133,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   lghr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   lghr %r2, %r2
+;   br %r14
 
 function %uload32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -97,10 +152,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   llgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   llgfr %r2, %r4
+;   br %r14
 
 function %uload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -110,10 +172,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
 ;   llgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrv %r2, 0(%r1)
+;   llgfr %r2, %r2
+;   br %r14
 
 function %sload32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -121,10 +191,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   lgfr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   lgfr %r2, %r4
+;   br %r14
 
 function %sload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -134,10 +211,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
 ;   lgfr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrv %r2, 0(%r1)
+;   lgfr %r2, %r2
+;   br %r14
 
 function %load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -145,9 +230,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrv %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r2, 0(%r2)
+;   br %r14
 
 function %load_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -157,9 +248,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrv %r2, 0(%r1)
+;   br %r14
 
 function %uload8_i32(i64) -> i32 {
 block0(v0: i64):
@@ -167,9 +265,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i32(i64) -> i32 {
 block0(v0: i64):
@@ -177,9 +281,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lb %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i32(i64) -> i32 {
 block0(v0: i64):
@@ -187,10 +297,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   llhr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   llhr %r2, %r4
+;   br %r14
 
 function %uload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -200,10 +317,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   llhr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   llhr %r2, %r2
+;   br %r14
 
 function %sload16_i32(i64) -> i32 {
 block0(v0: i64):
@@ -211,10 +336,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   lhr %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   lhr %r2, %r4
+;   br %r14
 
 function %sload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -224,10 +356,18 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   lhr %r2, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   lhr %r2, %r2
+;   br %r14
 
 function %load_i16(i64) -> i16 {
 block0(v0: i64):
@@ -235,9 +375,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r2, 0(%r2)
+;   br %r14
 
 function %load_i16_sym() -> i16 {
   gv0 = symbol colocated %sym
@@ -247,9 +393,16 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   lrvh %r2, 0(%r1)
+;   br %r14
 
 function %uload8_i16(i64) -> i16 {
 block0(v0: i64):
@@ -257,9 +410,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i16(i64) -> i16 {
 block0(v0: i64):
@@ -267,9 +426,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lb %r2, 0(%r2)
+;   br %r14
 
 function %load_i8(i64) -> i8 {
 block0(v0: i64):
@@ -277,7 +442,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/load.clif b/cranelift/filetests/filetests/isa/s390x/load.clif
index 8e53baae36..43b3540f47 100644
--- a/cranelift/filetests/filetests/isa/s390x/load.clif
+++ b/cranelift/filetests/filetests/isa/s390x/load.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lg %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lg %r2, 0(%r2)
+;   br %r14
 
 function %load_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -19,9 +25,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %uload8_i64(i64) -> i64 {
 block0(v0: i64):
@@ -29,9 +41,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i64(i64) -> i64 {
 block0(v0: i64):
@@ -39,9 +57,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgb %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i64(i64) -> i64 {
 block0(v0: i64):
@@ -49,9 +73,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgh %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -61,9 +91,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llghrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llghrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %sload16_i64(i64) -> i64 {
 block0(v0: i64):
@@ -71,9 +107,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgh %r2, 0(%r2)
+;   br %r14
 
 function %sload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -83,9 +125,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lghrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %uload32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -93,9 +141,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgf %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgf %r2, 0(%r2)
+;   br %r14
 
 function %uload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -105,9 +159,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llgfrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llgfrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %sload32_i64(i64) -> i64 {
 block0(v0: i64):
@@ -115,9 +175,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgf %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgf %r2, 0(%r2)
+;   br %r14
 
 function %sload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
@@ -127,9 +193,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgfrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgfrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %load_i32(i64) -> i32 {
 block0(v0: i64):
@@ -137,9 +209,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   l %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   l %r2, 0(%r2)
+;   br %r14
 
 function %load_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -149,9 +227,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %load_i32_off(i64) -> i32 {
 block0(v0: i64):
@@ -159,9 +243,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ly %r2, 4096(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ly %r2, 0x1000(%r2)
+;   br %r14
 
 function %uload8_i32(i64) -> i32 {
 block0(v0: i64):
@@ -169,9 +259,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i32(i64) -> i32 {
 block0(v0: i64):
@@ -179,9 +275,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lb %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i32(i64) -> i32 {
 block0(v0: i64):
@@ -189,9 +291,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r2, 0(%r2)
+;   br %r14
 
 function %uload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -201,9 +309,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llhrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %sload16_i32(i64) -> i32 {
 block0(v0: i64):
@@ -211,9 +325,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lh %r2, 0(%r2)
+;   br %r14
 
 function %sload16_i32_off(i64) -> i32 {
 block0(v0: i64):
@@ -221,9 +341,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lhy %r2, 4096(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhy %r2, 0x1000(%r2)
+;   br %r14
 
 function %sload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
@@ -233,9 +359,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lhrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %load_i16(i64) -> i16 {
 block0(v0: i64):
@@ -243,9 +375,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llh %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llh %r2, 0(%r2)
+;   br %r14
 
 function %load_i16_sym() -> i16 {
   gv0 = symbol colocated %sym
@@ -255,9 +393,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llhrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %uload8_i16(i64) -> i16 {
 block0(v0: i64):
@@ -265,9 +409,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
 function %sload8_i16(i64) -> i16 {
 block0(v0: i64):
@@ -275,9 +425,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lb %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lb %r2, 0(%r2)
+;   br %r14
 
 function %load_i8(i64) -> i8 {
 block0(v0: i64):
@@ -285,7 +441,13 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/minmax.clif b/cranelift/filetests/filetests/isa/s390x/minmax.clif
index 32fda152b1..c818a74a5f 100644
--- a/cranelift/filetests/filetests/isa/s390x/minmax.clif
+++ b/cranelift/filetests/filetests/isa/s390x/minmax.clif
@@ -7,6 +7,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v5, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -14,6 +15,18 @@ block0(v0: i128, v1: i128):
 ;   jnl 10 ; vlr %v5, %v3
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v5, 0(%r3)
+;   vl %v3, 0(%r4)
+;   veclg %v5, %v3
+;   jne 0x1c
+;   vchlgs %v6, %v3, %v5
+;   jnl 0x26
+;   vlr %v5, %v3
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %umax_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -21,10 +34,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   locgrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+;   locgrl %r2, %r3
+;   br %r14
 
 function %umax_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -32,10 +52,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clr %r2, %r3
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clr %r2, %r3
+;   locrl %r2, %r3
+;   br %r14
 
 function %umax_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -43,12 +70,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   llhr %r4, %r3
 ;   clr %r5, %r4
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   llhr %r4, %r3
+;   clr %r5, %r4
+;   locrl %r2, %r3
+;   br %r14
 
 function %umax_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -56,12 +92,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   llcr %r4, %r3
 ;   clr %r5, %r4
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   llcr %r4, %r3
+;   clr %r5, %r4
+;   locrl %r2, %r3
+;   br %r14
 
 function %umin_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -69,6 +114,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v5, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -76,6 +122,18 @@ block0(v0: i128, v1: i128):
 ;   jnl 10 ; vlr %v5, %v3
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v5, 0(%r3)
+;   vl %v3, 0(%r4)
+;   veclg %v3, %v5
+;   jne 0x1c
+;   vchlgs %v6, %v5, %v3
+;   jnl 0x26
+;   vlr %v5, %v3
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %umin_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -83,10 +141,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clgr %r2, %r3
 ;   locgrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgr %r2, %r3
+;   locgrh %r2, %r3
+;   br %r14
 
 function %umin_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -94,10 +159,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   clr %r2, %r3
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clr %r2, %r3
+;   locrh %r2, %r3
+;   br %r14
 
 function %umin_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -105,12 +177,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   llhr %r4, %r3
 ;   clr %r5, %r4
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   llhr %r4, %r3
+;   clr %r5, %r4
+;   locrh %r2, %r3
+;   br %r14
 
 function %umin_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -118,12 +199,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   llcr %r4, %r3
 ;   clr %r5, %r4
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   llcr %r4, %r3
+;   clr %r5, %r4
+;   locrh %r2, %r3
+;   br %r14
 
 function %smax_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -131,6 +221,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v5, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -138,6 +229,18 @@ block0(v0: i128, v1: i128):
 ;   jnl 10 ; vlr %v5, %v3
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v5, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vecg %v5, %v3
+;   jne 0x1c
+;   vchlgs %v6, %v3, %v5
+;   jnl 0x26
+;   vlr %v5, %v3
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %smax_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -145,10 +248,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgr %r2, %r3
 ;   locgrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgr %r2, %r3
+;   locgrl %r2, %r3
+;   br %r14
 
 function %smax_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -156,10 +266,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cr %r2, %r3
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cr %r2, %r3
+;   locrl %r2, %r3
+;   br %r14
 
 function %smax_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -167,12 +284,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   lhr %r4, %r3
 ;   cr %r5, %r4
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   lhr %r4, %r3
+;   cr %r5, %r4
+;   locrl %r2, %r3
+;   br %r14
 
 function %smax_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -180,12 +306,21 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   lbr %r4, %r3
 ;   cr %r5, %r4
 ;   locrl %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   lbr %r4, %r3
+;   cr %r5, %r4
+;   locrl %r2, %r3
+;   br %r14
 
 function %smin_i128(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -193,6 +328,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v5, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -200,6 +336,18 @@ block0(v0: i128, v1: i128):
 ;   jnl 10 ; vlr %v5, %v3
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v5, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vecg %v3, %v5
+;   jne 0x1c
+;   vchlgs %v6, %v5, %v3
+;   jnl 0x26
+;   vlr %v5, %v3
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %smin_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -207,10 +355,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cgr %r2, %r3
 ;   locgrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cgr %r2, %r3
+;   locgrh %r2, %r3
+;   br %r14
 
 function %smin_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -218,10 +373,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   cr %r2, %r3
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cr %r2, %r3
+;   locrh %r2, %r3
+;   br %r14
 
 function %smin_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -229,12 +391,21 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   lhr %r4, %r3
 ;   cr %r5, %r4
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   lhr %r4, %r3
+;   cr %r5, %r4
+;   locrh %r2, %r3
+;   br %r14
 
 function %smin_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -242,10 +413,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   lbr %r4, %r3
 ;   cr %r5, %r4
 ;   locrh %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   lbr %r4, %r3
+;   cr %r5, %r4
+;   locrh %r2, %r3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif b/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif
index 4a005599db..b88bc92702 100644
--- a/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif
+++ b/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif
@@ -10,12 +10,21 @@ block1:
   return v0, v1, v2, v3
 }
 
+; VCode:
 ; block0:
 ;   lghi %r2, 1
 ;   lghi %r3, 2
 ;   lghi %r4, 3
 ;   lghi %r5, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r2, 1
+;   lghi %r3, 2
+;   lghi %r4, 3
+;   lghi %r5, 4
+;   br %r14
 
 function %f1() -> i64, i64, i64, i64, i64, i64 {
 block1:
@@ -28,6 +37,7 @@ block1:
   return v0, v1, v2, v3, v4, v5
 }
 
+; VCode:
 ;   stmg %r7, %r15, 56(%r15)
 ; block0:
 ;   lghi %r4, 1
@@ -42,6 +52,22 @@ block1:
 ;   lgr %r2, %r14
 ;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r7, %r15, 0x38(%r15)
+; block0: ; offset 0x6
+;   lghi %r4, 1
+;   lgr %r14, %r4
+;   lghi %r3, 2
+;   lghi %r4, 3
+;   lghi %r5, 4
+;   lghi %r7, 5
+;   lghi %r9, 6
+;   stg %r7, 0(%r2)
+;   stg %r9, 8(%r2)
+;   lgr %r2, %r14
+;   lmg %r7, %r15, 0x38(%r15)
+;   br %r14
 
 function %f3() -> f64, f64, f64, f64 {
 block1:
@@ -52,12 +78,39 @@ block1:
   return v0, v1, v2, v3
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
 ;   bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
 ;   bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1)
 ;   bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f0, 0(%r1)
+;   bras %r1, 0x1c
+;   sur %f15, %f0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f2, 0(%r1)
+;   bras %r1, 0x2c
+;   sth %r0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   bras %r1, 0x3c
+;   sth %r0, 0(%r8)
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f6, 0(%r1)
+;   br %r14
 
 function %f4() -> f64, f64, f64, f64, f64, f64 {
 block1:
@@ -70,6 +123,7 @@ block1:
   return v0, v1, v2, v3, v4, v5
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
 ;   bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
@@ -80,4 +134,42 @@ block1:
 ;   vsteg %v18, 0(%r2), 0
 ;   vsteg %v20, 8(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f0, 0(%r1)
+;   bras %r1, 0x1c
+;   sur %f15, %f0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f2, 0(%r1)
+;   bras %r1, 0x2c
+;   sth %r0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f4, 0(%r1)
+;   bras %r1, 0x3c
+;   sth %r0, 0(%r8)
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ld %f6, 0(%r1)
+;   bras %r1, 0x4c
+;   sth %r1, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v18, 0(%r1), 0
+;   bras %r1, 0x5e
+;   sth %r1, 0(%r4)
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vleg %v20, 0(%r1), 0
+;   vsteg %v18, 0(%r2), 0
+;   vsteg %v20, 8(%r2), 0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/reftypes.clif b/cranelift/filetests/filetests/isa/s390x/reftypes.clif
index c8614a3c7c..11e5824a9d 100644
--- a/cranelift/filetests/filetests/isa/s390x/reftypes.clif
+++ b/cranelift/filetests/filetests/isa/s390x/reftypes.clif
@@ -6,9 +6,15 @@ block0(v0: r64, v1: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lgr %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r2, %r3
+;   br %r14
 
 function %f1(r64) -> i8 {
 block0(v0: r64):
@@ -16,11 +22,19 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cghi %r2, 0
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r2, 0
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %f2(r64) -> i8 {
 block0(v0: r64):
@@ -28,11 +42,19 @@ block0(v0: r64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   cghi %r2, -1
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   cghi %r2, -1
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %f3() -> r64 {
 block0:
@@ -40,9 +62,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   lghi %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r2, 0
+;   br %r14
 
 function %f4(r64, r64) -> r64, r64, r64 {
     fn0 = %f(r64) -> i8
@@ -64,6 +92,7 @@ block3(v7: r64, v8: r64):
     return v7, v8, v9
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -184
 ;   virtual_sp_offset_adjust 160
@@ -95,4 +124,36 @@ block3(v7: r64, v8: r64):
 ;   lg %r4, 0(%r4)
 ;   lmg %r14, %r15, 296(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xb8
+; block0: ; offset 0xa
+;   stg %r2, 0xa8(%r15)
+;   stg %r3, 0xb0(%r15)
+;   bras %r1, 0x22
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %f 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r3, 0(%r1)
+;   basr %r14, %r3
+;   la %r5, 0xa0(%r15)
+;   lg %r4, 0xa8(%r15)
+;   stg %r4, 0(%r5)
+;   lbr %r2, %r2
+;   chi %r2, 0
+;   jgnlh 0x58
+; block1: ; offset 0x48
+;   lgr %r2, %r4
+;   lg %r3, 0xb0(%r15)
+;   jg 0x62
+; block2: ; offset 0x58
+;   lgr %r3, %r4
+;   lg %r2, 0xb0(%r15)
+; block3: ; offset 0x62
+;   la %r4, 0xa0(%r15)
+;   lg %r4, 0(%r4)
+;   lmg %r14, %r15, 0x128(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/saturating-ops.clif b/cranelift/filetests/filetests/isa/s390x/saturating-ops.clif
index 21c328e4ce..ce08f57937 100644
--- a/cranelift/filetests/filetests/isa/s390x/saturating-ops.clif
+++ b/cranelift/filetests/filetests/isa/s390x/saturating-ops.clif
@@ -10,7 +10,13 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lghi %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r2, 0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif
index 98813b00d8..8923a7286a 100644
--- a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif
+++ b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif
@@ -7,6 +7,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -19,6 +20,20 @@ block0(v0: i128, v1: i128):
 ;   vo %v26, %v20, %v24
 ;   vst %v26, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vrepb %v6, %v3, 0xf
+;   vlcb %v16, %v6
+;   vslb %v18, %v1, %v16
+;   vsl %v20, %v18, %v16
+;   vsrlb %v22, %v1, %v6
+;   vsrl %v24, %v22, %v6
+;   vo %v26, %v20, %v24
+;   vst %v26, 0(%r2)
+;   br %r14
 
 function %rotr_i128_reg(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -26,6 +41,7 @@ block0(v0: i128, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vlvgb %v5, %r4, 0
@@ -38,6 +54,20 @@ block0(v0: i128, v1: i64):
 ;   vo %v27, %v21, %v25
 ;   vst %v27, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vlvgb %v5, %r4, 0
+;   vrepb %v7, %v5, 0
+;   vlcb %v17, %v7
+;   vslb %v19, %v1, %v17
+;   vsl %v21, %v19, %v17
+;   vsrlb %v23, %v1, %v7
+;   vsrl %v25, %v23, %v7
+;   vo %v27, %v21, %v25
+;   vst %v27, 0(%r2)
+;   br %r14
 
 function %rotr_i128_imm(i128) -> i128 {
 block0(v0: i128):
@@ -46,6 +76,7 @@ block0(v0: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 17
@@ -57,6 +88,19 @@ block0(v0: i128):
 ;   vo %v24, %v18, %v22
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0x11
+;   vlcb %v6, %v4
+;   vslb %v16, %v1, %v6
+;   vsl %v18, %v16, %v6
+;   vsrlb %v20, %v1, %v4
+;   vsrl %v22, %v20, %v4
+;   vo %v24, %v18, %v22
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %rotr_i64_vr(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -64,12 +108,21 @@ block0(v0: i64, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   lcr %r4, %r3
 ;   rllg %r2, %r2, 0(%r4)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   rllg %r2, %r2, 0(%r4)
+;   br %r14
 
 function %rotr_i64_reg(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -77,10 +130,17 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r3
 ;   rllg %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r3
+;   rllg %r2, %r2, 0(%r5)
+;   br %r14
 
 function %rotr_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -89,9 +149,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rllg %r2, %r2, 47
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rllg %r2, %r2, 0x2f
+;   br %r14
 
 function %rotr_i32_vr(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -99,12 +165,21 @@ block0(v0: i32, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   lcr %r4, %r3
 ;   rll %r2, %r2, 0(%r4)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   rll %r2, %r2, 0(%r4)
+;   br %r14
 
 function %rotr_i32_reg(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -112,10 +187,17 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r3
 ;   rll %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r3
+;   rll %r2, %r2, 0(%r5)
+;   br %r14
 
 function %rotr_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -124,9 +206,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rll %r2, %r2, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rll %r2, %r2, 0xf
+;   br %r14
 
 function %rotr_i16_vr(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -134,6 +222,7 @@ block0(v0: i16, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llhr %r2, %r2
@@ -145,6 +234,19 @@ block0(v0: i16, v1: i128):
 ;   srlk %r2, %r2, 0(%r3)
 ;   ork %r2, %r4, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llhr %r2, %r2
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   nill %r3, 0xf
+;   nill %r4, 0xf
+;   sllk %r4, %r2, 0(%r4)
+;   srlk %r2, %r2, 0(%r3)
+;   ork %r2, %r4, %r2
+;   br %r14
 
 function %rotr_i16_reg(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -152,6 +254,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   lcr %r2, %r3
@@ -161,6 +264,17 @@ block0(v0: i16, v1: i16):
 ;   srlk %r3, %r5, 0(%r3)
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   lcr %r2, %r3
+;   nill %r3, 0xf
+;   nill %r2, 0xf
+;   sllk %r2, %r5, 0(%r2)
+;   srlk %r3, %r5, 0(%r3)
+;   or %r2, %r3
+;   br %r14
 
 function %rotr_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -169,12 +283,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   sllk %r2, %r4, 6
 ;   srlk %r4, %r4, 10
 ;   or %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   sllk %r2, %r4, 6
+;   srlk %r4, %r4, 0xa
+;   or %r2, %r4
+;   br %r14
 
 function %rotr_i8_vr(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -182,6 +305,7 @@ block0(v0: i8, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llcr %r2, %r2
@@ -193,6 +317,19 @@ block0(v0: i8, v1: i128):
 ;   srlk %r2, %r2, 0(%r3)
 ;   ork %r2, %r4, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llcr %r2, %r2
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   nill %r3, 7
+;   nill %r4, 7
+;   sllk %r4, %r2, 0(%r4)
+;   srlk %r2, %r2, 0(%r3)
+;   ork %r2, %r4, %r2
+;   br %r14
 
 function %rotr_i8_reg(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -200,6 +337,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   lcr %r2, %r3
@@ -209,6 +347,17 @@ block0(v0: i8, v1: i8):
 ;   srlk %r3, %r5, 0(%r3)
 ;   or %r2, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   lcr %r2, %r3
+;   nill %r3, 7
+;   nill %r2, 7
+;   sllk %r2, %r5, 0(%r2)
+;   srlk %r3, %r5, 0(%r3)
+;   or %r2, %r3
+;   br %r14
 
 function %rotr_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -217,12 +366,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r4, %r2
 ;   sllk %r2, %r4, 5
 ;   srlk %r4, %r4, 3
 ;   or %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r4, %r2
+;   sllk %r2, %r4, 5
+;   srlk %r4, %r4, 3
+;   or %r2, %r4
+;   br %r14
 
 function %rotl_i128_vr(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -230,6 +388,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -242,6 +401,20 @@ block0(v0: i128, v1: i128):
 ;   vo %v26, %v20, %v24
 ;   vst %v26, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vrepb %v6, %v3, 0xf
+;   vlcb %v16, %v6
+;   vslb %v18, %v1, %v6
+;   vsl %v20, %v18, %v6
+;   vsrlb %v22, %v1, %v16
+;   vsrl %v24, %v22, %v16
+;   vo %v26, %v20, %v24
+;   vst %v26, 0(%r2)
+;   br %r14
 
 function %rotl_i128_reg(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -249,6 +422,7 @@ block0(v0: i128, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vlvgb %v5, %r4, 0
@@ -261,6 +435,20 @@ block0(v0: i128, v1: i64):
 ;   vo %v27, %v21, %v25
 ;   vst %v27, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vlvgb %v5, %r4, 0
+;   vrepb %v7, %v5, 0
+;   vlcb %v17, %v7
+;   vslb %v19, %v1, %v7
+;   vsl %v21, %v19, %v7
+;   vsrlb %v23, %v1, %v17
+;   vsrl %v25, %v23, %v17
+;   vo %v27, %v21, %v25
+;   vst %v27, 0(%r2)
+;   br %r14
 
 function %rotl_i128_imm(i128) -> i128 {
 block0(v0: i128):
@@ -269,6 +457,7 @@ block0(v0: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 17
@@ -280,6 +469,19 @@ block0(v0: i128):
 ;   vo %v24, %v18, %v22
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0x11
+;   vlcb %v6, %v4
+;   vslb %v16, %v1, %v4
+;   vsl %v18, %v16, %v4
+;   vsrlb %v20, %v1, %v6
+;   vsrl %v22, %v20, %v6
+;   vo %v24, %v18, %v22
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %rotl_i64_vr(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -287,11 +489,19 @@ block0(v0: i64, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   rllg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   rllg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %rotl_i64_reg(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -299,9 +509,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rllg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rllg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %rotl_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -310,9 +526,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rllg %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rllg %r2, %r2, 0x11
+;   br %r14
 
 function %rotl_i32_vr(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -320,11 +542,19 @@ block0(v0: i32, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   rll %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   rll %r2, %r2, 0(%r3)
+;   br %r14
 
 function %rotl_i32_reg(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -332,9 +562,15 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rll %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rll %r2, %r2, 0(%r3)
+;   br %r14
 
 function %rotl_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -343,9 +579,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   rll %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   rll %r2, %r2, 0x11
+;   br %r14
 
 function %rotl_i16_vr(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -353,6 +595,7 @@ block0(v0: i16, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llhr %r2, %r2
@@ -364,6 +607,19 @@ block0(v0: i16, v1: i128):
 ;   srlk %r2, %r2, 0(%r4)
 ;   ork %r2, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llhr %r2, %r2
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   nill %r3, 0xf
+;   nill %r4, 0xf
+;   sllk %r5, %r2, 0(%r3)
+;   srlk %r2, %r2, 0(%r4)
+;   ork %r2, %r5, %r2
+;   br %r14
 
 function %rotl_i16_reg(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -371,6 +627,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   lcr %r2, %r3
@@ -380,6 +637,17 @@ block0(v0: i16, v1: i16):
 ;   srlk %r4, %r5, 0(%r2)
 ;   ork %r2, %r3, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   lcr %r2, %r3
+;   nill %r3, 0xf
+;   nill %r2, 0xf
+;   sllk %r3, %r5, 0(%r3)
+;   srlk %r4, %r5, 0(%r2)
+;   ork %r2, %r3, %r4
+;   br %r14
 
 function %rotl_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -388,12 +656,21 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   sllk %r2, %r4, 10
 ;   srlk %r4, %r4, 6
 ;   or %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   sllk %r2, %r4, 0xa
+;   srlk %r4, %r4, 6
+;   or %r2, %r4
+;   br %r14
 
 function %rotl_i8_vr(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -401,6 +678,7 @@ block0(v0: i8, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llcr %r2, %r2
@@ -412,6 +690,19 @@ block0(v0: i8, v1: i128):
 ;   srlk %r2, %r2, 0(%r4)
 ;   ork %r2, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llcr %r2, %r2
+;   vlgvg %r3, %v2, 1
+;   lcr %r4, %r3
+;   nill %r3, 7
+;   nill %r4, 7
+;   sllk %r5, %r2, 0(%r3)
+;   srlk %r2, %r2, 0(%r4)
+;   ork %r2, %r5, %r2
+;   br %r14
 
 function %rotl_i8_reg(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -419,6 +710,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   lcr %r2, %r3
@@ -428,6 +720,17 @@ block0(v0: i8, v1: i8):
 ;   srlk %r4, %r5, 0(%r2)
 ;   ork %r2, %r3, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   lcr %r2, %r3
+;   nill %r3, 7
+;   nill %r2, 7
+;   sllk %r3, %r5, 0(%r3)
+;   srlk %r4, %r5, 0(%r2)
+;   ork %r2, %r3, %r4
+;   br %r14
 
 function %rotr_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -436,12 +739,21 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r4, %r2
 ;   sllk %r2, %r4, 3
 ;   srlk %r4, %r4, 5
 ;   or %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r4, %r2
+;   sllk %r2, %r4, 3
+;   srlk %r4, %r4, 5
+;   or %r2, %r4
+;   br %r14
 
 function %ushr_i128_vr(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -449,6 +761,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -457,6 +770,16 @@ block0(v0: i128, v1: i128):
 ;   vsrl %v18, %v16, %v6
 ;   vst %v18, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vrepb %v6, %v3, 0xf
+;   vsrlb %v16, %v1, %v6
+;   vsrl %v18, %v16, %v6
+;   vst %v18, 0(%r2)
+;   br %r14
 
 function %ushr_i128_reg(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -464,6 +787,7 @@ block0(v0: i128, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vlvgb %v5, %r4, 0
@@ -472,6 +796,16 @@ block0(v0: i128, v1: i64):
 ;   vsrl %v19, %v17, %v7
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vlvgb %v5, %r4, 0
+;   vrepb %v7, %v5, 0
+;   vsrlb %v17, %v1, %v7
+;   vsrl %v19, %v17, %v7
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %ushr_i128_imm(i128) -> i128 {
 block0(v0: i128):
@@ -480,6 +814,7 @@ block0(v0: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 17
@@ -487,6 +822,15 @@ block0(v0: i128):
 ;   vsrl %v16, %v6, %v4
 ;   vst %v16, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0x11
+;   vsrlb %v6, %v1, %v4
+;   vsrl %v16, %v6, %v4
+;   vst %v16, 0(%r2)
+;   br %r14
 
 function %ushr_i64_vr(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -494,11 +838,19 @@ block0(v0: i64, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   srlg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   srlg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ushr_i64_reg(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -506,9 +858,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srlg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srlg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ushr_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -517,9 +875,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srlg %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srlg %r2, %r2, 0x11
+;   br %r14
 
 function %ushr_i32_vr(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -527,12 +891,21 @@ block0(v0: i32, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   nill %r3, 31
 ;   srlk %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   nill %r3, 0x1f
+;   srlk %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ushr_i32_reg(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -540,11 +913,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   nill %r5, 31
 ;   srlk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   nill %r5, 0x1f
+;   srlk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ushr_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -553,9 +934,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srlk %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srlk %r2, %r2, 0x11
+;   br %r14
 
 function %ushr_i16_vr(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -563,6 +950,7 @@ block0(v0: i16, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llhr %r2, %r2
@@ -570,6 +958,15 @@ block0(v0: i16, v1: i128):
 ;   nill %r5, 15
 ;   srlk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llhr %r2, %r2
+;   vlgvg %r5, %v2, 1
+;   nill %r5, 0xf
+;   srlk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ushr_i16_reg(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -577,11 +974,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r5, %r2
 ;   nill %r3, 15
 ;   srlk %r2, %r5, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r5, %r2
+;   nill %r3, 0xf
+;   srlk %r2, %r5, 0(%r3)
+;   br %r14
 
 function %ushr_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -590,10 +995,17 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llhr %r4, %r2
 ;   srlk %r2, %r4, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llhr %r4, %r2
+;   srlk %r2, %r4, 0xa
+;   br %r14
 
 function %ushr_i8_vr(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -601,6 +1013,7 @@ block0(v0: i8, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   llcr %r2, %r2
@@ -608,6 +1021,15 @@ block0(v0: i8, v1: i128):
 ;   nill %r5, 7
 ;   srlk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   llcr %r2, %r2
+;   vlgvg %r5, %v2, 1
+;   nill %r5, 7
+;   srlk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ushr_i8_reg(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -615,11 +1037,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r5, %r2
 ;   nill %r3, 7
 ;   srlk %r2, %r5, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r5, %r2
+;   nill %r3, 7
+;   srlk %r2, %r5, 0(%r3)
+;   br %r14
 
 function %ushr_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -628,10 +1058,17 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   llcr %r4, %r2
 ;   srlk %r2, %r4, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llcr %r4, %r2
+;   srlk %r2, %r4, 3
+;   br %r14
 
 function %ishl_i128_vr(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -639,6 +1076,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -647,6 +1085,16 @@ block0(v0: i128, v1: i128):
 ;   vsl %v18, %v16, %v6
 ;   vst %v18, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vrepb %v6, %v3, 0xf
+;   vslb %v16, %v1, %v6
+;   vsl %v18, %v16, %v6
+;   vst %v18, 0(%r2)
+;   br %r14
 
 function %ishl_i128_reg(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -654,6 +1102,7 @@ block0(v0: i128, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vlvgb %v5, %r4, 0
@@ -662,6 +1111,16 @@ block0(v0: i128, v1: i64):
 ;   vsl %v19, %v17, %v7
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vlvgb %v5, %r4, 0
+;   vrepb %v7, %v5, 0
+;   vslb %v17, %v1, %v7
+;   vsl %v19, %v17, %v7
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %ishl_i128_imm(i128) -> i128 {
 block0(v0: i128):
@@ -670,6 +1129,7 @@ block0(v0: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 17
@@ -677,6 +1137,15 @@ block0(v0: i128):
 ;   vsl %v16, %v6, %v4
 ;   vst %v16, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0x11
+;   vslb %v6, %v1, %v4
+;   vsl %v16, %v6, %v4
+;   vst %v16, 0(%r2)
+;   br %r14
 
 function %ishl_i64_vr(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -684,11 +1153,19 @@ block0(v0: i64, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   sllg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   sllg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ishl_i64_reg(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -696,9 +1173,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllg %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllg %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ishl_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -707,9 +1190,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllg %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllg %r2, %r2, 0x11
+;   br %r14
 
 function %ishl_i32_vr(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -717,12 +1206,21 @@ block0(v0: i32, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   nill %r3, 31
 ;   sllk %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   nill %r3, 0x1f
+;   sllk %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ishl_i32_reg(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -730,11 +1228,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   nill %r5, 31
 ;   sllk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   nill %r5, 0x1f
+;   sllk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ishl_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -743,9 +1249,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r2, 0x11
+;   br %r14
 
 function %ishl_i16_vr(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -753,12 +1265,21 @@ block0(v0: i16, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   nill %r3, 15
 ;   sllk %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   nill %r3, 0xf
+;   sllk %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ishl_i16_reg(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -766,11 +1287,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   nill %r5, 15
 ;   sllk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   nill %r5, 0xf
+;   sllk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ishl_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -779,9 +1308,15 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r2, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r2, 0xa
+;   br %r14
 
 function %ishl_i8_vr(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -789,12 +1324,21 @@ block0(v0: i8, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   nill %r3, 7
 ;   sllk %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   nill %r3, 7
+;   sllk %r2, %r2, 0(%r3)
+;   br %r14
 
 function %ishl_i8_reg(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -802,11 +1346,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   nill %r5, 7
 ;   sllk %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   nill %r5, 7
+;   sllk %r2, %r2, 0(%r5)
+;   br %r14
 
 function %ishl_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -815,9 +1367,15 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   sllk %r2, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sllk %r2, %r2, 3
+;   br %r14
 
 function %sshr_i128_vr(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -825,6 +1383,7 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
@@ -833,6 +1392,16 @@ block0(v0: i128, v1: i128):
 ;   vsra %v18, %v16, %v6
 ;   vst %v18, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vl %v3, 0(%r4)
+;   vrepb %v6, %v3, 0xf
+;   vsrab %v16, %v1, %v6
+;   vsra %v18, %v16, %v6
+;   vst %v18, 0(%r2)
+;   br %r14
 
 function %sshr_i128_reg(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -840,6 +1409,7 @@ block0(v0: i128, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vlvgb %v5, %r4, 0
@@ -848,6 +1418,16 @@ block0(v0: i128, v1: i64):
 ;   vsra %v19, %v17, %v7
 ;   vst %v19, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vlvgb %v5, %r4, 0
+;   vrepb %v7, %v5, 0
+;   vsrab %v17, %v1, %v7
+;   vsra %v19, %v17, %v7
+;   vst %v19, 0(%r2)
+;   br %r14
 
 function %sshr_i128_imm(i128) -> i128 {
 block0(v0: i128):
@@ -856,6 +1436,7 @@ block0(v0: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vrepib %v4, 17
@@ -863,6 +1444,15 @@ block0(v0: i128):
 ;   vsra %v16, %v6, %v4
 ;   vst %v16, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r3)
+;   vrepib %v4, 0x11
+;   vsrab %v6, %v1, %v4
+;   vsra %v16, %v6, %v4
+;   vst %v16, 0(%r2)
+;   br %r14
 
 function %sshr_i64_vr(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -870,11 +1460,19 @@ block0(v0: i64, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   srag %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   srag %r2, %r2, 0(%r3)
+;   br %r14
 
 function %sshr_i64_reg(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -882,9 +1480,15 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srag %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srag %r2, %r2, 0(%r3)
+;   br %r14
 
 function %sshr_i64_imm(i64) -> i64 {
 block0(v0: i64):
@@ -893,9 +1497,15 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srag %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srag %r2, %r2, 0x11
+;   br %r14
 
 function %sshr_i32_vr(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -903,12 +1513,21 @@ block0(v0: i32, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   vlgvg %r3, %v2, 1
 ;   nill %r3, 31
 ;   srak %r2, %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   vlgvg %r3, %v2, 1
+;   nill %r3, 0x1f
+;   srak %r2, %r2, 0(%r3)
+;   br %r14
 
 function %sshr_i32_reg(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -916,11 +1535,19 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   nill %r5, 31
 ;   srak %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   nill %r5, 0x1f
+;   srak %r2, %r2, 0(%r5)
+;   br %r14
 
 function %sshr_i32_imm(i32) -> i32 {
 block0(v0: i32):
@@ -929,9 +1556,15 @@ block0(v0: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   srak %r2, %r2, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srak %r2, %r2, 0x11
+;   br %r14
 
 function %sshr_i16_vr(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -939,6 +1572,7 @@ block0(v0: i16, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   lhr %r2, %r2
@@ -946,6 +1580,15 @@ block0(v0: i16, v1: i128):
 ;   nill %r5, 15
 ;   srak %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   lhr %r2, %r2
+;   vlgvg %r5, %v2, 1
+;   nill %r5, 0xf
+;   srak %r2, %r2, 0(%r5)
+;   br %r14
 
 function %sshr_i16_reg(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -953,11 +1596,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r5, %r2
 ;   nill %r3, 15
 ;   srak %r2, %r5, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r5, %r2
+;   nill %r3, 0xf
+;   srak %r2, %r5, 0(%r3)
+;   br %r14
 
 function %sshr_i16_imm(i16) -> i16 {
 block0(v0: i16):
@@ -966,10 +1617,17 @@ block0(v0: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lhr %r4, %r2
 ;   srak %r2, %r4, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhr %r4, %r2
+;   srak %r2, %r4, 0xa
+;   br %r14
 
 function %sshr_i8_vr(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -977,6 +1635,7 @@ block0(v0: i8, v1: i128):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r3)
 ;   lbr %r2, %r2
@@ -984,6 +1643,15 @@ block0(v0: i8, v1: i128):
 ;   nill %r5, 7
 ;   srak %r2, %r2, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r3)
+;   lbr %r2, %r2
+;   vlgvg %r5, %v2, 1
+;   nill %r5, 7
+;   srak %r2, %r2, 0(%r5)
+;   br %r14
 
 function %sshr_i8_reg(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -991,11 +1659,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r5, %r2
 ;   nill %r3, 7
 ;   srak %r2, %r5, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r5, %r2
+;   nill %r3, 7
+;   srak %r2, %r5, 0(%r3)
+;   br %r14
 
 function %sshr_i8_imm(i8) -> i8 {
 block0(v0: i8):
@@ -1004,8 +1680,15 @@ block0(v0: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lbr %r4, %r2
 ;   srak %r2, %r4, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lbr %r4, %r2
+;   srak %r2, %r4, 3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/stack-limit.clif b/cranelift/filetests/filetests/isa/s390x/stack-limit.clif
index e2f802ab24..0d01c49ca2 100644
--- a/cranelift/filetests/filetests/isa/s390x/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/s390x/stack-limit.clif
@@ -6,16 +6,26 @@ block0:
     return
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %stack_limit_leaf_zero(i64 stack_limit) {
 block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %stack_limit_gv_leaf_zero(i64 vmctx) {
     gv0 = vmctx
@@ -26,8 +36,13 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %stack_limit_call_zero(i64 stack_limit) {
     fn0 = %foo()
@@ -36,6 +51,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   clgrtle %r15, %r2
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
@@ -45,6 +61,21 @@ block0(v0: i64):
 ;   basr %r14, %r4
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   clgrtle %r15, %r2 ; trap: stk_ovf
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xe
+;   bras %r1, 0x1a
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %stack_limit_gv_call_zero(i64 vmctx) {
     gv0 = vmctx
@@ -57,6 +88,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   lg %r1, 0(%r2)
 ;   lg %r1, 4(%r1)
 ;   clgrtle %r15, %r1
@@ -68,6 +100,23 @@ block0(v0: i64):
 ;   basr %r14, %r4
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   lg %r1, 0(%r2)
+;   lg %r1, 4(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0x1a
+;   bras %r1, 0x26
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %foo 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 168
@@ -75,12 +124,21 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   la %r1, 168(%r2)
 ;   clgrtle %r15, %r1
 ;   aghi %r15, -168
 ; block0:
 ;   aghi %r15, 168
 ;   br %r14
+; 
+; Disassembled:
+;   la %r1, 0xa8(%r2)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   aghi %r15, -0xa8
+; block0: ; offset 0xc
+;   aghi %r15, 0xa8
+;   br %r14
 
 function %large_stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 400000
@@ -88,6 +146,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   clgrtle %r15, %r2
 ;   lay %r1, 400000(%r2)
 ;   clgrtle %r15, %r1
@@ -95,6 +154,15 @@ block0(v0: i64):
 ; block0:
 ;   agfi %r15, 400000
 ;   br %r14
+; 
+; Disassembled:
+;   clgrtle %r15, %r2 ; trap: stk_ovf
+;   lay %r1, 0x61a80(%r2)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   agfi %r15, -0x61a80
+; block0: ; offset 0x14
+;   agfi %r15, 0x61a80
+;   br %r14
 
 function %huge_stack_limit(i64 stack_limit) {
     ss0 = explicit_slot 4000000
@@ -102,6 +170,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   clgrtle %r15, %r2
 ;   lgr %r1, %r2
 ;   algfi %r1, 4000000
@@ -110,6 +179,16 @@ block0(v0: i64):
 ; block0:
 ;   agfi %r15, 4000000
 ;   br %r14
+; 
+; Disassembled:
+;   clgrtle %r15, %r2 ; trap: stk_ovf
+;   lgr %r1, %r2
+;   algfi %r1, 0x3d0900
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   agfi %r15, -0x3d0900
+; block0: ; offset 0x18
+;   agfi %r15, 0x3d0900
+;   br %r14
 
 function %limit_preamble(i64 vmctx) {
     gv0 = vmctx
@@ -121,6 +200,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   lg %r1, 0(%r2)
 ;   lg %r1, 4(%r1)
 ;   la %r1, 24(%r1)
@@ -129,6 +209,16 @@ block0(v0: i64):
 ; block0:
 ;   aghi %r15, 24
 ;   br %r14
+; 
+; Disassembled:
+;   lg %r1, 0(%r2)
+;   lg %r1, 4(%r1)
+;   la %r1, 0x18(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   aghi %r15, -0x18
+; block0: ; offset 0x18
+;   aghi %r15, 0x18
+;   br %r14
 
 function %limit_preamble_large(i64 vmctx) {
     gv0 = vmctx
@@ -140,6 +230,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   lg %r1, 0(%r2)
 ;   lg %r1, 4(%r1)
 ;   clgrtle %r15, %r1
@@ -149,6 +240,17 @@ block0(v0: i64):
 ; block0:
 ;   agfi %r15, 400000
 ;   br %r14
+; 
+; Disassembled:
+;   lg %r1, 0(%r2)
+;   lg %r1, 4(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   lay %r1, 0x61a80(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   agfi %r15, -0x61a80
+; block0: ; offset 0x20
+;   agfi %r15, 0x61a80
+;   br %r14
 
 function %limit_preamble_huge(i64 vmctx) {
     gv0 = vmctx
@@ -160,6 +262,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   lg %r1, 0(%r2)
 ;   lg %r1, 4(%r1)
 ;   clgrtle %r15, %r1
@@ -169,6 +272,17 @@ block0(v0: i64):
 ; block0:
 ;   agfi %r15, 4000000
 ;   br %r14
+; 
+; Disassembled:
+;   lg %r1, 0(%r2)
+;   lg %r1, 4(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   algfi %r1, 0x3d0900
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   agfi %r15, -0x3d0900
+; block0: ; offset 0x20
+;   agfi %r15, 0x3d0900
+;   br %r14
 
 function %limit_preamble_huge_offset(i64 vmctx) {
     gv0 = vmctx
@@ -179,6 +293,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   lgfi %r1, 1000000 ; lg %r1, 0(%r1,%r2)
 ;   la %r1, 24(%r1)
 ;   clgrtle %r15, %r1
@@ -186,4 +301,14 @@ block0(v0: i64):
 ; block0:
 ;   aghi %r15, 24
 ;   br %r14
+; 
+; Disassembled:
+;   lgfi %r1, 0xf4240
+;   lg %r1, 0(%r1, %r2)
+;   la %r1, 0x18(%r1)
+;   clgrtle %r15, %r1 ; trap: stk_ovf
+;   aghi %r15, -0x18
+; block0: ; offset 0x18
+;   aghi %r15, 0x18
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/stack.clif b/cranelift/filetests/filetests/isa/s390x/stack.clif
index f356a7fcbf..708bd69837 100644
--- a/cranelift/filetests/filetests/isa/s390x/stack.clif
+++ b/cranelift/filetests/filetests/isa/s390x/stack.clif
@@ -11,11 +11,19 @@ block0:
   return v0
 }
 
+; VCode:
 ;   aghi %r15, -8
 ; block0:
 ;   la %r2, 0(%r15)
 ;   aghi %r15, 8
 ;   br %r14
+; 
+; Disassembled:
+;   aghi %r15, -8
+; block0: ; offset 0x4
+;   la %r2, 0(%r15)
+;   aghi %r15, 8
+;   br %r14
 
 function %stack_addr_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -26,11 +34,19 @@ block0:
   return v0
 }
 
+; VCode:
 ;   agfi %r15, -100008
 ; block0:
 ;   la %r2, 0(%r15)
 ;   agfi %r15, 100008
 ;   br %r14
+; 
+; Disassembled:
+;   agfi %r15, -0x186a8
+; block0: ; offset 0x6
+;   la %r2, 0(%r15)
+;   agfi %r15, 0x186a8
+;   br %r14
 
 function %stack_load_small() -> i64 {
 ss0 = explicit_slot 8
@@ -40,12 +56,21 @@ block0:
   return v0
 }
 
+; VCode:
 ;   aghi %r15, -8
 ; block0:
 ;   la %r3, 0(%r15)
 ;   lg %r2, 0(%r3)
 ;   aghi %r15, 8
 ;   br %r14
+; 
+; Disassembled:
+;   aghi %r15, -8
+; block0: ; offset 0x4
+;   la %r3, 0(%r15)
+;   lg %r2, 0(%r3)
+;   aghi %r15, 8
+;   br %r14
 
 function %stack_load_big() -> i64 {
 ss0 = explicit_slot 100000
@@ -56,12 +81,21 @@ block0:
   return v0
 }
 
+; VCode:
 ;   agfi %r15, -100008
 ; block0:
 ;   la %r3, 0(%r15)
 ;   lg %r2, 0(%r3)
 ;   agfi %r15, 100008
 ;   br %r14
+; 
+; Disassembled:
+;   agfi %r15, -0x186a8
+; block0: ; offset 0x6
+;   la %r3, 0(%r15)
+;   lg %r2, 0(%r3)
+;   agfi %r15, 0x186a8
+;   br %r14
 
 function %stack_store_small(i64) {
 ss0 = explicit_slot 8
@@ -71,12 +105,21 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   aghi %r15, -8
 ; block0:
 ;   la %r4, 0(%r15)
 ;   stg %r2, 0(%r4)
 ;   aghi %r15, 8
 ;   br %r14
+; 
+; Disassembled:
+;   aghi %r15, -8
+; block0: ; offset 0x4
+;   la %r4, 0(%r15)
+;   stg %r2, 0(%r4)
+;   aghi %r15, 8
+;   br %r14
 
 function %stack_store_big(i64) {
 ss0 = explicit_slot 100000
@@ -87,10 +130,19 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ;   agfi %r15, -100008
 ; block0:
 ;   la %r4, 0(%r15)
 ;   stg %r2, 0(%r4)
 ;   agfi %r15, 100008
 ;   br %r14
+; 
+; Disassembled:
+;   agfi %r15, -0x186a8
+; block0: ; offset 0x6
+;   la %r4, 0(%r15)
+;   stg %r2, 0(%r4)
+;   agfi %r15, 0x186a8
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/store-little.clif b/cranelift/filetests/filetests/isa/s390x/store-little.clif
index 1ceebec3d2..4103d87993 100644
--- a/cranelift/filetests/filetests/isa/s390x/store-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/store-little.clif
@@ -7,9 +7,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvg %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvg %r2, 0(%r3)
+;   br %r14
 
 function %store_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -19,9 +25,16 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvg %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvg %r2, 0(%r1)
+;   br %r14
 
 function %store_imm_i64(i64) {
 block0(v0: i64):
@@ -30,10 +43,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lghi %r4, 12345
 ;   strvg %r4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r4, 0x3039
+;   strvg %r4, 0(%r2)
+;   br %r14
 
 function %istore8_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -41,9 +61,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i64(i64) {
 block0(v0: i64):
@@ -52,9 +78,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %istore16_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -62,9 +94,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvh %r2, 0(%r3)
+;   br %r14
 
 function %istore16_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -74,9 +112,16 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvh %r2, 0(%r1)
+;   br %r14
 
 function %istore16_imm_i64(i64) {
 block0(v0: i64):
@@ -85,9 +130,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 14640
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3930
+;   br %r14
 
 function %istore32_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -95,9 +146,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strv %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strv %r2, 0(%r3)
+;   br %r14
 
 function %istore32_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -107,9 +164,16 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strv %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strv %r2, 0(%r1)
+;   br %r14
 
 function %istore32_imm_i64(i64) {
 block0(v0: i64):
@@ -118,10 +182,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lghi %r4, 12345
 ;   strv %r4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lghi %r4, 0x3039
+;   strv %r4, 0(%r2)
+;   br %r14
 
 function %store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -129,9 +200,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strv %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strv %r2, 0(%r3)
+;   br %r14
 
 function %store_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -141,9 +218,16 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strv %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strv %r2, 0(%r1)
+;   br %r14
 
 function %store_imm_i32(i64) {
 block0(v0: i64):
@@ -152,10 +236,17 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   lhi %r4, 12345
 ;   strv %r4, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lhi %r4, 0x3039
+;   strv %r4, 0(%r2)
+;   br %r14
 
 function %istore8_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -163,9 +254,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i32(i64) {
 block0(v0: i64):
@@ -174,9 +271,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %istore16_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -184,9 +287,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvh %r2, 0(%r3)
+;   br %r14
 
 function %istore16_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -196,9 +305,16 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvh %r2, 0(%r1)
+;   br %r14
 
 function %istore16_imm_i32(i64) {
 block0(v0: i64):
@@ -207,9 +323,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 14640
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3930
+;   br %r14
 
 function %store_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -217,9 +339,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strvh %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strvh %r2, 0(%r3)
+;   br %r14
 
 function %store_i16_sym(i16) {
   gv0 = symbol colocated %sym
@@ -229,9 +357,16 @@ block0(v0: i16):
   return
 }
 
+; VCode:
 ; block0:
 ;   larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r1, 0 ; reloc_external PCRel32Dbl %sym 2
+;   strvh %r2, 0(%r1)
+;   br %r14
 
 function %store_imm_i16(i64) {
 block0(v0: i64):
@@ -240,9 +375,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 14640
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3930
+;   br %r14
 
 function %istore8_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -250,9 +391,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i16(i64) {
 block0(v0: i64):
@@ -261,9 +408,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %store_i8(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -271,9 +424,15 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %store_i8_off(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -281,9 +440,15 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stcy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stcy %r2, 0x1000(%r3)
+;   br %r14
 
 function %store_imm_i8(i64) {
 block0(v0: i64):
@@ -292,9 +457,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %store_imm_i8_off(i64) {
 block0(v0: i64):
@@ -303,7 +474,13 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mviy 4096(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mviy 0x1000(%r2), 0x7b
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/store.clif b/cranelift/filetests/filetests/isa/s390x/store.clif
index 15c09b76b7..39057467b4 100644
--- a/cranelift/filetests/filetests/isa/s390x/store.clif
+++ b/cranelift/filetests/filetests/isa/s390x/store.clif
@@ -7,9 +7,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stg %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stg %r2, 0(%r3)
+;   br %r14
 
 function %store_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -19,9 +25,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stgrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stgrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %store_imm_i64(i64) {
 block0(v0: i64):
@@ -30,9 +42,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvghi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvghi 0(%r2), 0x3039
+;   br %r14
 
 function %istore8_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -40,9 +58,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i64(i64) {
 block0(v0: i64):
@@ -51,9 +75,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %istore16_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -61,9 +91,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sth %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sth %r2, 0(%r3)
+;   br %r14
 
 function %istore16_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -73,9 +109,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sthrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sthrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %istore16_imm_i64(i64) {
 block0(v0: i64):
@@ -84,9 +126,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3039
+;   br %r14
 
 function %istore32_i64(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -94,9 +142,15 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   st %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   st %r2, 0(%r3)
+;   br %r14
 
 function %istore32_i64_sym(i64) {
   gv0 = symbol colocated %sym
@@ -106,9 +160,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   strl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %istore32_imm_i64(i64) {
 block0(v0: i64):
@@ -117,9 +177,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhi 0(%r2), 0x3039
+;   br %r14
 
 function %store_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -127,9 +193,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   st %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   st %r2, 0(%r3)
+;   br %r14
 
 function %store_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -139,9 +211,15 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   strl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   strl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %store_i32_off(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -149,9 +227,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sty %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sty %r2, 0x1000(%r3)
+;   br %r14
 
 function %store_imm_i32(i64) {
 block0(v0: i64):
@@ -160,9 +244,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhi 0(%r2), 0x3039
+;   br %r14
 
 function %istore8_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -170,9 +260,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i32(i64) {
 block0(v0: i64):
@@ -181,9 +277,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %istore16_i32(i32, i64) {
 block0(v0: i32, v1: i64):
@@ -191,9 +293,15 @@ block0(v0: i32, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sth %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sth %r2, 0(%r3)
+;   br %r14
 
 function %istore16_i32_sym(i32) {
   gv0 = symbol colocated %sym
@@ -203,9 +311,15 @@ block0(v0: i32):
   return
 }
 
+; VCode:
 ; block0:
 ;   sthrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sthrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %istore16_imm_i32(i64) {
 block0(v0: i64):
@@ -214,9 +328,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3039
+;   br %r14
 
 function %store_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -224,9 +344,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sth %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sth %r2, 0(%r3)
+;   br %r14
 
 function %store_i16_sym(i16) {
   gv0 = symbol colocated %sym
@@ -236,9 +362,15 @@ block0(v0: i16):
   return
 }
 
+; VCode:
 ; block0:
 ;   sthrl %r2, %sym + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sthrl %r2, 0 ; reloc_external PCRel32Dbl %sym 2
+;   br %r14
 
 function %store_i16_off(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -246,9 +378,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   sthy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sthy %r2, 0x1000(%r3)
+;   br %r14
 
 function %store_imm_i16(i64) {
 block0(v0: i64):
@@ -257,9 +395,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvhhi 0(%r2), 12345
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvhhi 0(%r2), 0x3039
+;   br %r14
 
 function %istore8_i16(i16, i64) {
 block0(v0: i16, v1: i64):
@@ -267,9 +411,15 @@ block0(v0: i16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %istore8_imm_i16(i64) {
 block0(v0: i64):
@@ -278,9 +428,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %store_i8(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -288,9 +444,15 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stc %r2, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stc %r2, 0(%r3)
+;   br %r14
 
 function %store_i8_off(i8, i64) {
 block0(v0: i8, v1: i64):
@@ -298,9 +460,15 @@ block0(v0: i8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   stcy %r2, 4096(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   stcy %r2, 0x1000(%r3)
+;   br %r14
 
 function %store_imm_i8(i64) {
 block0(v0: i64):
@@ -309,9 +477,15 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mvi 0(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mvi 0(%r2), 0x7b
+;   br %r14
 
 function %store_imm_i8_off(i64) {
 block0(v0: i64):
@@ -320,7 +494,13 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   mviy 4096(%r2), 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mviy 0x1000(%r2), 0x7b
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/struct-arg.clif b/cranelift/filetests/filetests/isa/s390x/struct-arg.clif
index 11abb7ed35..6f4bfc7843 100644
--- a/cranelift/filetests/filetests/isa/s390x/struct-arg.clif
+++ b/cranelift/filetests/filetests/isa/s390x/struct-arg.clif
@@ -7,9 +7,15 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   llc %r2, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r2, 0(%r2)
+;   br %r14
 
 function u0:1(i64 sarg(64), i64) -> i8 system_v {
 block0(v0: i64, v1: i64):
@@ -19,11 +25,19 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   llc %r3, 0(%r3)
 ;   llc %r4, 0(%r2)
 ;   ark %r2, %r3, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   llc %r3, 0(%r3)
+;   llc %r4, 0(%r2)
+;   ark %r2, %r3, %r4
+;   br %r14
 
 function u0:2(i64) -> i8 system_v {
 fn1 = colocated u0:0(i64 sarg(64)) -> i8 system_v
@@ -33,6 +47,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -224
 ;   virtual_sp_offset_adjust 224
@@ -42,6 +57,16 @@ block0(v0: i64):
 ;   brasl %r14, userextname0
 ;   lmg %r14, %r15, 336(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xe0
+; block0: ; offset 0xa
+;   mvc 0xa0(0x40, %r15), 0(%r2)
+;   la %r2, 0xa0(%r15)
+;   brasl %r14, 0x14 ; reloc_external PLTRel32Dbl u0:0 2
+;   lmg %r14, %r15, 0x150(%r15)
+;   br %r14
 
 function u0:3(i64, i64) -> i8 system_v {
 fn1 = colocated u0:0(i64, i64 sarg(64)) -> i8 system_v
@@ -51,6 +76,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -224
 ;   virtual_sp_offset_adjust 224
@@ -60,6 +86,16 @@ block0(v0: i64, v1: i64):
 ;   brasl %r14, userextname0
 ;   lmg %r14, %r15, 336(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xe0
+; block0: ; offset 0xa
+;   mvc 0xa0(0x40, %r15), 0(%r3)
+;   la %r3, 0xa0(%r15)
+;   brasl %r14, 0x14 ; reloc_external PLTRel32Dbl u0:0 2
+;   lmg %r14, %r15, 0x150(%r15)
+;   br %r14
 
 function u0:4(i64 sarg(256), i64 sarg(64)) -> i8 system_v {
 block0(v0: i64, v1: i64):
@@ -69,12 +105,21 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ; block0:
 ;   lgr %r5, %r3
 ;   llc %r3, 0(%r2)
 ;   llc %r4, 0(%r5)
 ;   ark %r2, %r3, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lgr %r5, %r3
+;   llc %r3, 0(%r2)
+;   llc %r4, 0(%r5)
+;   ark %r2, %r3, %r4
+;   br %r14
 
 function u0:5(i64, i64, i64) -> i8 system_v {
 fn1 = colocated u0:0(i64, i64 sarg(256), i64 sarg(64)) -> i8 system_v
@@ -84,6 +129,7 @@ block0(v0: i64, v1: i64, v2: i64):
     return v3
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -480
 ;   virtual_sp_offset_adjust 480
@@ -95,6 +141,18 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   brasl %r14, userextname0
 ;   lmg %r14, %r15, 592(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0x1e0
+; block0: ; offset 0xa
+;   mvc 0xa0(0x100, %r15), 0(%r3)
+;   mvc 0x1a0(0x40, %r15), 0(%r4)
+;   la %r3, 0xa0(%r15)
+;   la %r4, 0x1a0(%r15)
+;   brasl %r14, 0x1e ; reloc_external PLTRel32Dbl u0:0 2
+;   lmg %r14, %r15, 0x250(%r15)
+;   br %r14
 
 function u0:6(i64, i64, i64) -> i8 system_v {
 fn1 = colocated u0:0(i64, i64 sarg(1024), i64 sarg(64)) -> i8 system_v
@@ -104,6 +162,7 @@ block0(v0: i64, v1: i64, v2: i64):
     return v3
 }
 
+; VCode:
 ;   stmg %r7, %r15, 56(%r15)
 ;   aghi %r15, -1248
 ;   virtual_sp_offset_adjust 1248
@@ -122,4 +181,23 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   brasl %r14, userextname0
 ;   lmg %r7, %r15, 1304(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r7, %r15, 0x38(%r15)
+;   aghi %r15, -0x4e0
+; block0: ; offset 0xa
+;   lgr %r7, %r2
+;   lgr %r9, %r4
+;   la %r2, 0xa0(%r15)
+;   la %r3, 0(%r3)
+;   lghi %r4, 0x400
+;   brasl %r14, 0x1e ; reloc_external PLTRel32Dbl %Memcpy 2
+;   lgr %r4, %r9
+;   mvc 0x4a0(0x40, %r15), 0(%r4)
+;   la %r3, 0xa0(%r15)
+;   la %r4, 0x4a0(%r15)
+;   lgr %r2, %r7
+;   brasl %r14, 0x3a ; reloc_external PLTRel32Dbl u0:0 2
+;   lmg %r7, %r15, 0x518(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/symbols.clif b/cranelift/filetests/filetests/isa/s390x/symbols.clif
index c995ea94eb..b76436174d 100644
--- a/cranelift/filetests/filetests/isa/s390x/symbols.clif
+++ b/cranelift/filetests/filetests/isa/s390x/symbols.clif
@@ -13,9 +13,20 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data %my_global + 0 ; lg %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %my_global 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r2, 0(%r1)
+;   br %r14
 
 function %symbol_value_colocated() -> i64 {
   gv0 = symbol colocated %my_global_colo
@@ -25,9 +36,15 @@ block0:
   return v0
 }
 
+; VCode:
 ; block0:
 ;   larl %r2, %my_global_colo + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r2, 0 ; reloc_external PCRel32Dbl %my_global_colo 2
+;   br %r14
 
 function %func_addr() -> i64 {
     fn0 = %my_func(i64) -> i64
@@ -37,9 +54,20 @@ block0:
     return v0
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data %my_func + 0 ; lg %r2, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %my_func 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r2, 0(%r1)
+;   br %r14
 
 function %func_addr_colocated() -> i64 {
     fn0 = colocated %my_func_colo(i64) -> i64
@@ -49,7 +77,13 @@ block0:
     return v0
 }
 
+; VCode:
 ; block0:
 ;   larl %r2, %my_func_colo + 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   larl %r2, 0 ; reloc_external PCRel32Dbl %my_func_colo 2
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/tls_elf.clif b/cranelift/filetests/filetests/isa/s390x/tls_elf.clif
index e23fc14d04..f895bbd0b0 100644
--- a/cranelift/filetests/filetests/isa/s390x/tls_elf.clif
+++ b/cranelift/filetests/filetests/isa/s390x/tls_elf.clif
@@ -10,6 +10,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   stmg %r12, %r15, 96(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -23,4 +24,23 @@ block0(v0: i32):
 ;   agr %r2, %r5
 ;   lmg %r12, %r15, 256(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r12, %r15, 0x60(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   larl %r12, 0xa ; reloc_external PCRel32Dbl %ElfGlobalOffsetTable 2
+;   bras %r1, 0x1c
+;   .byte 0x00, 0x00 ; reloc_external TlsGd64 u1:0 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r2, 0(%r1)
+;   brasl %r14, 0x22 ; reloc_external TlsGdCall u1:0 0
+;   ear %r3, %a0
+;   sllg %r5, %r3, 0x20
+;   ear %r5, %a1
+;   agr %r2, %r5
+;   lmg %r12, %r15, 0x100(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/traps.clif b/cranelift/filetests/filetests/isa/s390x/traps.clif
index bf7a15d842..acbc4a4133 100644
--- a/cranelift/filetests/filetests/isa/s390x/traps.clif
+++ b/cranelift/filetests/filetests/isa/s390x/traps.clif
@@ -10,16 +10,26 @@ block0:
   trap user0
 }
 
+; VCode:
 ; block0:
 ;   trap
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x00 ; trap: user0
 
 function %resumable_trap() {
 block0:
   trap user0
 }
 
+; VCode:
 ; block0:
 ;   trap
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x00 ; trap: user0
 
 function %trapz(i64) {
 block0(v0: i64):
@@ -29,6 +39,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   clgfi %r2, 42
 ;   jge label1 ; jg label2
@@ -36,6 +47,15 @@ block0(v0: i64):
 ;   br %r14
 ; block2:
 ;   trap
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfi %r2, 0x2a
+;   jgne 0xe
+; block1: ; offset 0xc
+;   br %r14
+; block2: ; offset 0xe
+;   .byte 0x00, 0x00 ; trap: user0
 
 function %trapnz(i64) {
 block0(v0: i64):
@@ -45,6 +65,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   clgfi %r2, 42
 ;   jge label1 ; jg label2
@@ -52,6 +73,15 @@ block0(v0: i64):
 ;   br %r14
 ; block1:
 ;   trap
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfi %r2, 0x2a
+;   jge 0xe
+; block1: ; offset 0xc
+;   br %r14
+; block2: ; offset 0xe
+;   .byte 0x00, 0x00 ; trap: user0
 
 function %resumable_trapnz(i64) {
 block0(v0: i64):
@@ -61,6 +91,7 @@ block0(v0: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   clgfi %r2, 42
 ;   jge label1 ; jg label2
@@ -68,6 +99,15 @@ block0(v0: i64):
 ;   br %r14
 ; block1:
 ;   trap
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   clgfi %r2, 0x2a
+;   jge 0xe
+; block1: ; offset 0xc
+;   br %r14
+; block2: ; offset 0xe
+;   .byte 0x00, 0x00 ; trap: user0
 
 function %h() {
 block0:
@@ -75,7 +115,13 @@ block0:
   return
 }
 
+; VCode:
 ; block0:
 ;   debugtrap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x01
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/s390x/uadd_overflow_trap.clif
index e0c9ddd841..f49a40590c 100644
--- a/cranelift/filetests/filetests/isa/s390x/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/s390x/uadd_overflow_trap.clif
@@ -8,10 +8,18 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   alfi %r2, 127
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   alfi %r2, 0x7f
+;   jle 0xc
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -20,10 +28,18 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   alfi %r2, 127
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   alfi %r2, 0x7f
+;   jle 0xc
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -31,10 +47,18 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   alr %r2, %r3
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   alr %r2, %r3
+;   jle 8
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -43,10 +67,18 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   algfi %r2, 127
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   algfi %r2, 0x7f
+;   jle 0xc
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -55,10 +87,18 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   algfi %r2, 127
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   algfi %r2, 0x7f
+;   jle 0xc
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -66,10 +106,18 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   algr %r2, %r3
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   algr %r2, %r3
+;   jle 0xa
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
 
 function %f5(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -78,7 +126,16 @@ block0(v0: i64, v1: i32):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   algfr %r2, %r3
 ;   jle 6 ; trap
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   algfr %r2, %r3
+;   jle 0xa
+;   .byte 0x00, 0x00 ; trap: user0
+;   br %r14
+
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-abi.clif b/cranelift/filetests/filetests/isa/s390x/vec-abi.clif
index 2055e5836c..ee2d06c0aa 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-abi.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-abi.clif
@@ -9,6 +9,7 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
     return v4
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -17,6 +18,20 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
 ;   basr %r14, %r4
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   bras %r1, 0x16
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %callee_be 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
 function %caller_be_to_le(i64x2, i32x4, i16x8, i8x16) -> i32x4 {
     fn0 = %callee_le(i64x2, i32x4, i16x8, i8x16) -> i32x4 wasmtime_system_v
@@ -26,6 +41,7 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
     return v4
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -224
 ;   virtual_sp_offset_adjust 160
@@ -62,6 +78,48 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
 ;   ld %f15, 216(%r15)
 ;   lmg %r14, %r15, 336(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xe0
+;   std %f8, 0xa0(%r15)
+;   std %f9, 0xa8(%r15)
+;   std %f10, 0xb0(%r15)
+;   std %f11, 0xb8(%r15)
+;   std %f12, 0xc0(%r15)
+;   std %f13, 0xc8(%r15)
+;   std %f14, 0xd0(%r15)
+;   std %f15, 0xd8(%r15)
+; block0: ; offset 0x2a
+;   vpdi %v24, %v24, %v24, 4
+;   vpdi %v7, %v25, %v25, 4
+;   verllg %v25, %v7, 0x20
+;   vpdi %v19, %v26, %v26, 4
+;   verllg %v21, %v19, 0x20
+;   verllf %v26, %v21, 0x10
+;   vpdi %v27, %v27, %v27, 4
+;   verllg %v27, %v27, 0x20
+;   verllf %v29, %v27, 0x10
+;   verllh %v27, %v29, 8
+;   bras %r1, 0x72
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %callee_le 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   vpdi %v5, %v24, %v24, 4
+;   verllg %v24, %v5, 0x20
+;   ld %f8, 0xa0(%r15)
+;   ld %f9, 0xa8(%r15)
+;   ld %f10, 0xb0(%r15)
+;   ld %f11, 0xb8(%r15)
+;   ld %f12, 0xc0(%r15)
+;   ld %f13, 0xc8(%r15)
+;   ld %f14, 0xd0(%r15)
+;   ld %f15, 0xd8(%r15)
+;   lmg %r14, %r15, 0x150(%r15)
+;   br %r14
 
 function %caller_le_to_be(i64x2, i32x4, i16x8, i8x16) -> i32x4 wasmtime_system_v {
     fn0 = %callee_be(i64x2, i32x4, i16x8, i8x16) -> i32x4
@@ -71,6 +129,7 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
     return v4
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -224
 ;   virtual_sp_offset_adjust 160
@@ -107,6 +166,48 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
 ;   ld %f15, 216(%r15)
 ;   lmg %r14, %r15, 336(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xe0
+;   std %f8, 0xa0(%r15)
+;   std %f9, 0xa8(%r15)
+;   std %f10, 0xb0(%r15)
+;   std %f11, 0xb8(%r15)
+;   std %f12, 0xc0(%r15)
+;   std %f13, 0xc8(%r15)
+;   std %f14, 0xd0(%r15)
+;   std %f15, 0xd8(%r15)
+; block0: ; offset 0x2a
+;   vpdi %v24, %v24, %v24, 4
+;   vpdi %v7, %v25, %v25, 4
+;   verllg %v25, %v7, 0x20
+;   vpdi %v19, %v26, %v26, 4
+;   verllg %v21, %v19, 0x20
+;   verllf %v26, %v21, 0x10
+;   vpdi %v27, %v27, %v27, 4
+;   verllg %v27, %v27, 0x20
+;   verllf %v29, %v27, 0x10
+;   verllh %v27, %v29, 8
+;   bras %r1, 0x72
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %callee_be 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   vpdi %v5, %v24, %v24, 4
+;   verllg %v24, %v5, 0x20
+;   ld %f8, 0xa0(%r15)
+;   ld %f9, 0xa8(%r15)
+;   ld %f10, 0xb0(%r15)
+;   ld %f11, 0xb8(%r15)
+;   ld %f12, 0xc0(%r15)
+;   ld %f13, 0xc8(%r15)
+;   ld %f14, 0xd0(%r15)
+;   ld %f15, 0xd8(%r15)
+;   lmg %r14, %r15, 0x150(%r15)
+;   br %r14
 
 function %caller_le_to_le(i64x2, i32x4, i16x8, i8x16) -> i32x4 wasmtime_system_v {
     fn0 = %callee_le(i64x2, i32x4, i16x8, i8x16) -> i32x4 wasmtime_system_v
@@ -116,6 +217,7 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
     return v4
 }
 
+; VCode:
 ;   stmg %r14, %r15, 112(%r15)
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
@@ -124,4 +226,18 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16):
 ;   basr %r14, %r4
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
+; 
+; Disassembled:
+;   stmg %r14, %r15, 0x70(%r15)
+;   aghi %r15, -0xa0
+; block0: ; offset 0xa
+;   bras %r1, 0x16
+;   .byte 0x00, 0x00 ; reloc_external Abs8 %callee_le 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   lg %r4, 0(%r1)
+;   basr %r14, %r4
+;   lmg %r14, %r15, 0x110(%r15)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif b/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif
index 895ec748a4..bb8da42fe5 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vag %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vag %v24, %v24, %v25
+;   br %r14
 
 function %iadd_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -17,9 +23,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vaf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vaf %v24, %v24, %v25
+;   br %r14
 
 function %iadd_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -27,9 +39,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vah %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vah %v24, %v24, %v25
+;   br %r14
 
 function %iadd_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -37,9 +55,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vab %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vab %v24, %v24, %v25
+;   br %r14
 
 function %isub_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -47,9 +71,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsg %v24, %v24, %v25
+;   br %r14
 
 function %isub_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -57,9 +87,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsf %v24, %v24, %v25
+;   br %r14
 
 function %isub_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -67,9 +103,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsh %v24, %v24, %v25
+;   br %r14
 
 function %isub_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -77,9 +119,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsb %v24, %v24, %v25
+;   br %r14
 
 function %iabs_i64x2(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -87,9 +135,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlpg %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlpg %v24, %v24
+;   br %r14
 
 function %iabs_i32x4(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -97,9 +151,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlpf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlpf %v24, %v24
+;   br %r14
 
 function %iabs_i16x8(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -107,9 +167,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlph %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlph %v24, %v24
+;   br %r14
 
 function %iabs_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -117,9 +183,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlpb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlpb %v24, %v24
+;   br %r14
 
 function %ineg_i64x2(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -127,9 +199,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlcg %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlcg %v24, %v24
+;   br %r14
 
 function %ineg_i32x4(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -137,9 +215,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlcf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlcf %v24, %v24
+;   br %r14
 
 function %ineg_i16x8(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -147,9 +231,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlch %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlch %v24, %v24
+;   br %r14
 
 function %ineg_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -157,9 +247,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlcb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlcb %v24, %v24
+;   br %r14
 
 function %umax_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -167,9 +263,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxlg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxlg %v24, %v24, %v25
+;   br %r14
 
 function %umax_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -177,9 +279,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxlf %v24, %v24, %v25
+;   br %r14
 
 function %umax_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -187,9 +295,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxlh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxlh %v24, %v24, %v25
+;   br %r14
 
 function %umax_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -197,9 +311,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxlb %v24, %v24, %v25
+;   br %r14
 
 function %umin_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -207,9 +327,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnlg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnlg %v24, %v24, %v25
+;   br %r14
 
 function %umin_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -217,9 +343,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnlf %v24, %v24, %v25
+;   br %r14
 
 function %umin_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -227,9 +359,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnlh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnlh %v24, %v24, %v25
+;   br %r14
 
 function %umin_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -237,9 +375,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnlb %v24, %v24, %v25
+;   br %r14
 
 function %smax_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -247,9 +391,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxg %v24, %v24, %v25
+;   br %r14
 
 function %smax_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -257,9 +407,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxf %v24, %v24, %v25
+;   br %r14
 
 function %smax_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -267,9 +423,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxh %v24, %v24, %v25
+;   br %r14
 
 function %smax_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -277,9 +439,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmxb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmxb %v24, %v24, %v25
+;   br %r14
 
 function %smin_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -287,9 +455,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmng %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmng %v24, %v24, %v25
+;   br %r14
 
 function %smin_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -297,9 +471,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnf %v24, %v24, %v25
+;   br %r14
 
 function %smin_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -307,9 +487,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnh %v24, %v24, %v25
+;   br %r14
 
 function %smin_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -317,9 +503,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmnb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmnb %v24, %v24, %v25
+;   br %r14
 
 function %avg_round_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -327,9 +519,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vavglg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vavglg %v24, %v24, %v25
+;   br %r14
 
 function %avg_round_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -337,9 +535,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vavglf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vavglf %v24, %v24, %v25
+;   br %r14
 
 function %avg_round_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -347,9 +551,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vavglh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vavglh %v24, %v24, %v25
+;   br %r14
 
 function %avg_round_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -357,9 +567,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vavglb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vavglb %v24, %v24, %v25
+;   br %r14
 
 function %uadd_sat64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -367,11 +583,19 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vag %v3, %v24, %v25
 ;   vchlg %v5, %v24, %v3
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vag %v3, %v24, %v25
+;   vchlg %v5, %v24, %v3
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %uadd_sat32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -379,11 +603,19 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vaf %v3, %v24, %v25
 ;   vchlf %v5, %v24, %v3
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vaf %v3, %v24, %v25
+;   vchlf %v5, %v24, %v3
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %uadd_sat16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -391,11 +623,19 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vah %v3, %v24, %v25
 ;   vchlh %v5, %v24, %v3
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vah %v3, %v24, %v25
+;   vchlh %v5, %v24, %v3
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %uadd_sat8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -403,11 +643,19 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vab %v3, %v24, %v25
 ;   vchlb %v5, %v24, %v3
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vab %v3, %v24, %v25
+;   vchlb %v5, %v24, %v3
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %sadd_sat32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -415,6 +663,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v3, %v24
 ;   vuphf %v5, %v25
@@ -424,6 +673,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   vag %v21, %v17, %v19
 ;   vpksg %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v3, %v24
+;   vuphf %v5, %v25
+;   vag %v7, %v3, %v5
+;   vuplf %v17, %v24
+;   vuplf %v19, %v25
+;   vag %v21, %v17, %v19
+;   vpksg %v24, %v7, %v21
+;   br %r14
 
 function %sadd_sat16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -431,6 +691,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphh %v3, %v24
 ;   vuphh %v5, %v25
@@ -440,6 +701,17 @@ block0(v0: i16x8, v1: i16x8):
 ;   vaf %v21, %v17, %v19
 ;   vpksf %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphh %v3, %v24
+;   vuphh %v5, %v25
+;   vaf %v7, %v3, %v5
+;   vuplhw %v17, %v24
+;   vuplhw %v19, %v25
+;   vaf %v21, %v17, %v19
+;   vpksf %v24, %v7, %v21
+;   br %r14
 
 function %sadd_sat8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -447,6 +719,7 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphb %v3, %v24
 ;   vuphb %v5, %v25
@@ -456,6 +729,17 @@ block0(v0: i8x16, v1: i8x16):
 ;   vah %v21, %v17, %v19
 ;   vpksh %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphb %v3, %v24
+;   vuphb %v5, %v25
+;   vah %v7, %v3, %v5
+;   vuplb %v17, %v24
+;   vuplb %v19, %v25
+;   vah %v21, %v17, %v19
+;   vpksh %v24, %v7, %v21
+;   br %r14
 
 function %usub_sat64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -463,11 +747,19 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsg %v3, %v24, %v25
 ;   vchlg %v5, %v24, %v25
 ;   vn %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsg %v3, %v24, %v25
+;   vchlg %v5, %v24, %v25
+;   vn %v24, %v3, %v5
+;   br %r14
 
 function %usub_sat32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -475,11 +767,19 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsf %v3, %v24, %v25
 ;   vchlf %v5, %v24, %v25
 ;   vn %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsf %v3, %v24, %v25
+;   vchlf %v5, %v24, %v25
+;   vn %v24, %v3, %v5
+;   br %r14
 
 function %usub_sat16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -487,11 +787,19 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsh %v3, %v24, %v25
 ;   vchlh %v5, %v24, %v25
 ;   vn %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsh %v3, %v24, %v25
+;   vchlh %v5, %v24, %v25
+;   vn %v24, %v3, %v5
+;   br %r14
 
 function %usub_sat8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -499,11 +807,19 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vsb %v3, %v24, %v25
 ;   vchlb %v5, %v24, %v25
 ;   vn %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsb %v3, %v24, %v25
+;   vchlb %v5, %v24, %v25
+;   vn %v24, %v3, %v5
+;   br %r14
 
 function %ssub_sat32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -511,6 +827,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v3, %v24
 ;   vuphf %v5, %v25
@@ -520,6 +837,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   vsg %v21, %v17, %v19
 ;   vpksg %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v3, %v24
+;   vuphf %v5, %v25
+;   vsg %v7, %v3, %v5
+;   vuplf %v17, %v24
+;   vuplf %v19, %v25
+;   vsg %v21, %v17, %v19
+;   vpksg %v24, %v7, %v21
+;   br %r14
 
 function %ssub_sat16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -527,6 +855,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphh %v3, %v24
 ;   vuphh %v5, %v25
@@ -536,6 +865,17 @@ block0(v0: i16x8, v1: i16x8):
 ;   vsf %v21, %v17, %v19
 ;   vpksf %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphh %v3, %v24
+;   vuphh %v5, %v25
+;   vsf %v7, %v3, %v5
+;   vuplhw %v17, %v24
+;   vuplhw %v19, %v25
+;   vsf %v21, %v17, %v19
+;   vpksf %v24, %v7, %v21
+;   br %r14
 
 function %ssub_sat8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -543,6 +883,7 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphb %v3, %v24
 ;   vuphb %v5, %v25
@@ -552,6 +893,17 @@ block0(v0: i8x16, v1: i8x16):
 ;   vsh %v21, %v17, %v19
 ;   vpksh %v24, %v7, %v21
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphb %v3, %v24
+;   vuphb %v5, %v25
+;   vsh %v7, %v3, %v5
+;   vuplb %v17, %v24
+;   vuplb %v19, %v25
+;   vsh %v21, %v17, %v19
+;   vpksh %v24, %v7, %v21
+;   br %r14
 
 function %iadd_pairwise_i32x4_be(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -559,6 +911,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 32
 ;   vsrlb %v5, %v24, %v3
@@ -567,6 +920,16 @@ block0(v0: i32x4, v1: i32x4):
 ;   vaf %v19, %v25, %v17
 ;   vpkg %v24, %v7, %v19
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 0x20
+;   vsrlb %v5, %v24, %v3
+;   vaf %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vaf %v19, %v25, %v17
+;   vpkg %v24, %v7, %v19
+;   br %r14
 
 function %iadd_pairwise_i16x8_be(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -574,6 +937,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 16
 ;   vsrlb %v5, %v24, %v3
@@ -582,6 +946,16 @@ block0(v0: i16x8, v1: i16x8):
 ;   vah %v19, %v25, %v17
 ;   vpkf %v24, %v7, %v19
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 0x10
+;   vsrlb %v5, %v24, %v3
+;   vah %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vah %v19, %v25, %v17
+;   vpkf %v24, %v7, %v19
+;   br %r14
 
 function %iadd_pairwise_i8x16_be(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -589,6 +963,7 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 8
 ;   vsrlb %v5, %v24, %v3
@@ -597,6 +972,16 @@ block0(v0: i8x16, v1: i8x16):
 ;   vab %v19, %v25, %v17
 ;   vpkh %v24, %v7, %v19
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 8
+;   vsrlb %v5, %v24, %v3
+;   vab %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vab %v19, %v25, %v17
+;   vpkh %v24, %v7, %v19
+;   br %r14
 
 function %iadd_pairwise_i32x4_le(i32x4, i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -604,6 +989,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 32
 ;   vsrlb %v5, %v24, %v3
@@ -612,6 +998,16 @@ block0(v0: i32x4, v1: i32x4):
 ;   vaf %v19, %v25, %v17
 ;   vpkg %v24, %v19, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 0x20
+;   vsrlb %v5, %v24, %v3
+;   vaf %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vaf %v19, %v25, %v17
+;   vpkg %v24, %v19, %v7
+;   br %r14
 
 function %iadd_pairwise_i16x8_le(i16x8, i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -619,6 +1015,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 16
 ;   vsrlb %v5, %v24, %v3
@@ -627,6 +1024,16 @@ block0(v0: i16x8, v1: i16x8):
 ;   vah %v19, %v25, %v17
 ;   vpkf %v24, %v19, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 0x10
+;   vsrlb %v5, %v24, %v3
+;   vah %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vah %v19, %v25, %v17
+;   vpkf %v24, %v19, %v7
+;   br %r14
 
 function %iadd_pairwise_i8x16_le(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -634,6 +1041,7 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 8
 ;   vsrlb %v5, %v24, %v3
@@ -642,6 +1050,16 @@ block0(v0: i8x16, v1: i8x16):
 ;   vab %v19, %v25, %v17
 ;   vpkh %v24, %v19, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 8
+;   vsrlb %v5, %v24, %v3
+;   vab %v7, %v24, %v5
+;   vsrlb %v17, %v25, %v3
+;   vab %v19, %v25, %v17
+;   vpkh %v24, %v19, %v7
+;   br %r14
 
 function %imul_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -649,6 +1067,7 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   vlgvg %r3, %v25, 0
@@ -658,6 +1077,17 @@ block0(v0: i64x2, v1: i64x2):
 ;   msgr %r3, %r2
 ;   vlvgp %v24, %r5, %r3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   vlgvg %r3, %v25, 0
+;   msgr %r5, %r3
+;   vlgvg %r3, %v24, 1
+;   vlgvg %r2, %v25, 1
+;   msgr %r3, %r2
+;   vlvgp %v24, %r5, %r3
+;   br %r14
 
 function %imul_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -665,9 +1095,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlf %v24, %v24, %v25
+;   br %r14
 
 function %imul_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -675,9 +1111,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlhw %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlhw %v24, %v24, %v25
+;   br %r14
 
 function %imul_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -685,9 +1127,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlb %v24, %v24, %v25
+;   br %r14
 
 function %umulhi_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -695,6 +1143,7 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r3, %v24, 0
 ;   vlgvg %r4, %v25, 0
@@ -705,6 +1154,18 @@ block0(v0: i64x2, v1: i64x2):
 ;   mlgr %r2, %r4
 ;   vlvgp %v24, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r3, %v24, 0
+;   vlgvg %r4, %v25, 0
+;   mlgr %r2, %r4
+;   lgr %r5, %r2
+;   vlgvg %r3, %v24, 1
+;   vlgvg %r4, %v25, 1
+;   mlgr %r2, %r4
+;   vlvgp %v24, %r5, %r2
+;   br %r14
 
 function %umulhi_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -712,9 +1173,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlhf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlhf %v24, %v24, %v25
+;   br %r14
 
 function %umulhi_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -722,9 +1189,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlhh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlhh %v24, %v24, %v25
+;   br %r14
 
 function %umulhi_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -732,9 +1205,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmlhb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmlhb %v24, %v24, %v25
+;   br %r14
 
 function %smulhi_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -742,6 +1221,7 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   vlgvg %r3, %v25, 0
@@ -752,6 +1232,18 @@ block0(v0: i64x2, v1: i64x2):
 ;   mgrk %r2, %r2, %r4
 ;   vlvgp %v24, %r5, %r2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   vlgvg %r3, %v25, 0
+;   mgrk %r2, %r5, %r3
+;   lgr %r5, %r2
+;   vlgvg %r2, %v24, 1
+;   vlgvg %r4, %v25, 1
+;   mgrk %r2, %r2, %r4
+;   vlvgp %v24, %r5, %r2
+;   br %r14
 
 function %smulhi_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -759,9 +1251,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmhf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmhf %v24, %v24, %v25
+;   br %r14
 
 function %smulhi_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -769,9 +1267,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmhh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmhh %v24, %v24, %v25
+;   br %r14
 
 function %smulhi_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -779,9 +1283,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmhb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmhb %v24, %v24, %v25
+;   br %r14
 
 function %widening_pairwise_dot_product_s_i16x8(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -789,11 +1299,19 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vmeh %v3, %v24, %v25
 ;   vmoh %v5, %v24, %v25
 ;   vaf %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmeh %v3, %v24, %v25
+;   vmoh %v5, %v24, %v25
+;   vaf %v24, %v3, %v5
+;   br %r14
 
 function %sqmul_round_sat(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -801,6 +1319,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphh %v3, %v24
 ;   vuphh %v5, %v25
@@ -816,6 +1335,23 @@ block0(v0: i16x8, v1: i16x8):
 ;   vesraf %v1, %v31, 15
 ;   vpksf %v24, %v21, %v1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphh %v3, %v24
+;   vuphh %v5, %v25
+;   vmlf %v7, %v3, %v5
+;   vgmf %v17, 0x11, 0x11
+;   vaf %v19, %v7, %v17
+;   vesraf %v21, %v19, 0xf
+;   vuplhw %v23, %v24
+;   vuplhw %v25, %v25
+;   vmlf %v27, %v23, %v25
+;   vgmf %v29, 0x11, 0x11
+;   vaf %v31, %v27, %v29
+;   vesraf %v1, %v31, 0xf
+;   vpksf %v24, %v21, %v1
+;   br %r14
 
 function %sqmul_round_sat(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -823,6 +1359,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v3, %v24
 ;   vuphf %v5, %v25
@@ -850,4 +1387,33 @@ block0(v0: i32x4, v1: i32x4):
 ;   vesrag %v2, %v31, 31
 ;   vpksg %v24, %v1, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v3, %v24
+;   vuphf %v5, %v25
+;   lgdr %r5, %f3
+;   lgdr %r3, %f5
+;   msgr %r5, %r3
+;   vlgvg %r3, %v3, 1
+;   vlgvg %r2, %v5, 1
+;   msgr %r3, %r2
+;   vlvgp %v27, %r5, %r3
+;   vgmg %v29, 0x21, 0x21
+;   vag %v31, %v27, %v29
+;   vesrag %v1, %v31, 0x1f
+;   vuplf %v3, %v24
+;   vuplf %v5, %v25
+;   lgdr %r5, %f3
+;   lgdr %r3, %f5
+;   msgr %r5, %r3
+;   vlgvg %r3, %v3, 1
+;   vlgvg %r2, %v5, 1
+;   msgr %r3, %r2
+;   vlvgp %v27, %r5, %r3
+;   vgmg %v29, 0x21, 0x21
+;   vag %v31, %v27, %v29
+;   vesrag %v2, %v31, 0x1f
+;   vpksg %v24, %v1, %v2
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif b/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif
index 961142e1c0..5319fdd56c 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif
@@ -11,8 +11,13 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64x2_i32x4(i64x2) -> i32x4 {
 block0(v0: i64x2):
@@ -20,11 +25,19 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v2, %v24, %v24, 4
 ;   vpdi %v4, %v2, %v2, 4
 ;   verllg %v24, %v4, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v2, %v24, %v24, 4
+;   vpdi %v4, %v2, %v2, 4
+;   verllg %v24, %v4, 0x20
+;   br %r14
 
 function %bitcast_i64x2_i32x4(i64x2) -> i32x4 wasmtime_system_v {
 block0(v0: i64x2):
@@ -32,11 +45,19 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v2, %v24, %v24, 4
 ;   vpdi %v4, %v2, %v2, 4
 ;   verllg %v24, %v4, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v2, %v24, %v24, 4
+;   vpdi %v4, %v2, %v2, 4
+;   verllg %v24, %v4, 0x20
+;   br %r14
 
 function %bitcast_i64x2_i32x4(i64x2) -> i32x4 wasmtime_system_v {
 block0(v0: i64x2):
@@ -44,8 +65,13 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -53,8 +79,13 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -62,8 +93,13 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
 function %bitcast_i64x2_f64x2(i64x2) -> f64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -71,6 +107,11 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-bitops.clif b/cranelift/filetests/filetests/isa/s390x/vec-bitops.clif
index a5cff95c47..498850e0d6 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-bitops.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-bitops.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vpopctg %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpopctg %v24, %v24
+;   br %r14
 
 function %popcnt_i32x4(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -17,9 +23,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vpopctf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpopctf %v24, %v24
+;   br %r14
 
 function %popcnt_i16x8(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -27,9 +39,15 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vpopcth %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpopcth %v24, %v24
+;   br %r14
 
 function %popcnt_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -37,7 +55,13 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vpopctb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpopctb %v24, %v24
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-bitwise.clif b/cranelift/filetests/filetests/isa/s390x/vec-bitwise.clif
index 8b92db5881..1fdbb2e64f 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-bitwise.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-bitwise.clif
@@ -8,9 +8,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vn %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vn %v24, %v24, %v25
+;   br %r14
 
 function %band_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -18,9 +24,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vn %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vn %v24, %v24, %v25
+;   br %r14
 
 function %band_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -28,9 +40,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vn %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vn %v24, %v24, %v25
+;   br %r14
 
 function %band_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -38,9 +56,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vn %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vn %v24, %v24, %v25
+;   br %r14
 
 function %bor_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -48,9 +72,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vo %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vo %v24, %v24, %v25
+;   br %r14
 
 function %bor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -58,9 +88,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vo %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vo %v24, %v24, %v25
+;   br %r14
 
 function %bor_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -68,9 +104,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vo %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vo %v24, %v24, %v25
+;   br %r14
 
 function %bor_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -78,9 +120,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vo %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vo %v24, %v24, %v25
+;   br %r14
 
 function %bxor_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -88,9 +136,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -98,9 +152,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -108,9 +168,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -118,9 +184,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vx %v24, %v24, %v25
+;   br %r14
 
 function %band_not_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -128,9 +200,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnc %v24, %v24, %v25
+;   br %r14
 
 function %band_not_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -138,9 +216,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnc %v24, %v24, %v25
+;   br %r14
 
 function %band_not_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -148,9 +232,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnc %v24, %v24, %v25
+;   br %r14
 
 function %band_not_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -158,9 +248,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnc %v24, %v24, %v25
+;   br %r14
 
 function %bor_not_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -168,9 +264,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   voc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   voc %v24, %v24, %v25
+;   br %r14
 
 function %bor_not_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -178,9 +280,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   voc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   voc %v24, %v24, %v25
+;   br %r14
 
 function %bor_not_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -188,9 +296,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   voc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   voc %v24, %v24, %v25
+;   br %r14
 
 function %bor_not_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -198,9 +312,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   voc %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   voc %v24, %v24, %v25
+;   br %r14
 
 function %bxor_not_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -208,9 +328,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_not_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -218,9 +344,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_not_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -228,9 +360,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnx %v24, %v24, %v25
+;   br %r14
 
 function %bxor_not_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -238,9 +376,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vnx %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vnx %v24, %v24, %v25
+;   br %r14
 
 function %bnot_i64x2(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -248,9 +392,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vno %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vno %v24, %v24, %v24
+;   br %r14
 
 function %bnot_i32x4(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -258,9 +408,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vno %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vno %v24, %v24, %v24
+;   br %r14
 
 function %bnot_i16x8(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -268,9 +424,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vno %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vno %v24, %v24, %v24
+;   br %r14
 
 function %bnot_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -278,9 +440,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vno %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vno %v24, %v24, %v24
+;   br %r14
 
 function %bitselect_i64x2(i64x2, i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2, v2: i64x2):
@@ -288,9 +456,15 @@ block0(v0: i64x2, v1: i64x2, v2: i64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %bitselect_i32x4(i32x4, i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4, v2: i32x4):
@@ -298,9 +472,15 @@ block0(v0: i32x4, v1: i32x4, v2: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %bitselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8, v2: i16x8):
@@ -308,9 +488,15 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %bitselect_i8x16(i8x16, i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16, v2: i8x16):
@@ -318,9 +504,15 @@ block0(v0: i8x16, v1: i8x16, v2: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %vselect_i64x2(i64x2, i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2, v2: i64x2):
@@ -328,9 +520,15 @@ block0(v0: i64x2, v1: i64x2, v2: i64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %vselect_i32x4(i32x4, i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4, v2: i32x4):
@@ -338,9 +536,15 @@ block0(v0: i32x4, v1: i32x4, v2: i32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8, v2: i16x8):
@@ -348,9 +552,15 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
 function %vselect_i8x16(i8x16, i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16, v2: i8x16):
@@ -358,7 +568,13 @@ block0(v0: i8x16, v1: i8x16, v2: i8x16):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vsel %v24, %v25, %v26, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsel %v24, %v25, %v26, %v24
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-constants-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-constants-le-lane.clif
index 0d99f426c9..f8c5490a33 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-constants-le-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-constants-le-lane.clif
@@ -7,9 +7,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i64x2_splat1() -> i64x2 wasmtime_system_v {
 block0:
@@ -17,9 +23,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, 0x7fff
+;   br %r14
 
 function %vconst_i64x2_splat2() -> i64x2 wasmtime_system_v {
 block0:
@@ -27,9 +39,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, -0x8000
+;   br %r14
 
 function %vconst_i64x2_splat3() -> i64x2 wasmtime_system_v {
 block0:
@@ -37,9 +55,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0x0000000000008000 ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ssm 0x780(%r14)
+;   lpr %r0, %r0
+;   ler %f0, %f5
+;   br %r14
 
 function %vconst_i64x2_splat4() -> i64x2 wasmtime_system_v {
 block0:
@@ -47,9 +77,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0xffffffffffff7fff ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0xff, 0xff
+;   .byte 0xff, 0xff
+;   .byte 0xff, 0xff
+;   su %f15, 0x780(%r15, %r14)
+;   lpr %r0, %r0
+;   ler %f0, %f5
+;   br %r14
 
 function %vconst_i64x2_mixed() -> i64x2 wasmtime_system_v {
 block0:
@@ -57,9 +99,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00000000000000020000000000000001 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i32x4_zero() -> i32x4 wasmtime_system_v {
 block0:
@@ -67,9 +124,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i32x4_splat1() -> i32x4 wasmtime_system_v {
 block0:
@@ -77,9 +140,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, 0x7fff
+;   br %r14
 
 function %vconst_i32x4_splat2() -> i32x4 wasmtime_system_v {
 block0:
@@ -87,9 +156,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, -0x8000
+;   br %r14
 
 function %vconst_i32x4_splat3() -> i32x4 wasmtime_system_v {
 block0:
@@ -97,9 +172,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.u32 0x00008000 ; vlrepf %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   .byte 0x00, 0x00
+;   ssm 0x780(%r14)
+;   lpr %r0, %r0
+;   ldr %f0, %f5
+;   br %r14
 
 function %vconst_i32x4_splat4() -> i32x4 wasmtime_system_v {
 block0:
@@ -107,9 +192,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.u32 0xffff7fff ; vlrepf %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   .byte 0xff, 0xff
+;   su %f15, 0x780(%r15, %r14)
+;   lpr %r0, %r0
+;   ldr %f0, %f5
+;   br %r14
 
 function %vconst_i32x4_splat_i64() -> i32x4 wasmtime_system_v {
 block0:
@@ -117,9 +212,20 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0x0000000200000001 ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   vlrepg %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i32x4_mixed() -> i32x4 wasmtime_system_v {
 block0:
@@ -127,9 +233,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00000004000000030000000200000001 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x04
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x03
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i16x8_zero() -> i16x8 wasmtime_system_v {
 block0:
@@ -137,9 +258,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i16x8_splat1() -> i16x8 wasmtime_system_v {
 block0:
@@ -147,9 +274,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, 0x7fff
+;   br %r14
 
 function %vconst_i16x8_splat2() -> i16x8 wasmtime_system_v {
 block0:
@@ -157,9 +290,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, -0x8000
+;   br %r14
 
 function %vconst_i16x8_mixed() -> i16x8 wasmtime_system_v {
 block0:
@@ -167,9 +306,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00080007000600050004000300020001 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x08
+;   .byte 0x00, 0x07
+;   .byte 0x00, 0x06
+;   .byte 0x00, 0x05
+;   .byte 0x00, 0x04
+;   .byte 0x00, 0x03
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x01
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i8x16_zero() -> i8x16 wasmtime_system_v {
 block0:
@@ -177,9 +331,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i8x16_splat1() -> i8x16 wasmtime_system_v {
 block0:
@@ -187,9 +347,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 127
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x7f
+;   br %r14
 
 function %vconst_i8x16_splat2() -> i8x16 wasmtime_system_v {
 block0:
@@ -197,9 +363,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x80
+;   br %r14
 
 function %vconst_i8x16_mixed() -> i8x16 wasmtime_system_v {
 block0:
@@ -207,7 +379,22 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x100f0e0d0c0b0a090807060504030201 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   lpr %r0, %r15
+;   .byte 0x0e, 0x0d
+;   bassm %r0, %r11
+;   svc 9
+;   .byte 0x08, 0x07
+;   bctr %r0, %r5
+;   .byte 0x04, 0x03
+;   .byte 0x02, 0x01
+;   vl %v24, 0(%r1)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-constants.clif b/cranelift/filetests/filetests/isa/s390x/vec-constants.clif
index 31858dafe3..905f1eab65 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-constants.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-constants.clif
@@ -7,9 +7,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i64x2_splat1() -> i64x2 {
 block0:
@@ -17,9 +23,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, 0x7fff
+;   br %r14
 
 function %vconst_i64x2_splat2() -> i64x2 {
 block0:
@@ -27,9 +39,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, -0x8000
+;   br %r14
 
 function %vconst_i64x2_splat3() -> i64x2 {
 block0:
@@ -37,9 +55,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0x0000000000008000 ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   ssm 0x780(%r14)
+;   lpr %r0, %r0
+;   ler %f0, %f5
+;   br %r14
 
 function %vconst_i64x2_splat4() -> i64x2 {
 block0:
@@ -47,9 +77,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0xffffffffffff7fff ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0xff, 0xff
+;   .byte 0xff, 0xff
+;   .byte 0xff, 0xff
+;   su %f15, 0x780(%r15, %r14)
+;   lpr %r0, %r0
+;   ler %f0, %f5
+;   br %r14
 
 function %vconst_i64x2_mixed() -> i64x2 {
 block0:
@@ -57,9 +99,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00000000000000010000000000000002 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i32x4_zero() -> i32x4 {
 block0:
@@ -67,9 +124,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i32x4_splat1() -> i32x4 {
 block0:
@@ -77,9 +140,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, 0x7fff
+;   br %r14
 
 function %vconst_i32x4_splat2() -> i32x4 {
 block0:
@@ -87,9 +156,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, -0x8000
+;   br %r14
 
 function %vconst_i32x4_splat3() -> i32x4 {
 block0:
@@ -97,9 +172,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.u32 0x00008000 ; vlrepf %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   .byte 0x00, 0x00
+;   ssm 0x780(%r14)
+;   lpr %r0, %r0
+;   ldr %f0, %f5
+;   br %r14
 
 function %vconst_i32x4_splat4() -> i32x4 {
 block0:
@@ -107,9 +192,19 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 8 ; data.u32 0xffff7fff ; vlrepf %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 8
+;   .byte 0xff, 0xff
+;   su %f15, 0x780(%r15, %r14)
+;   lpr %r0, %r0
+;   ldr %f0, %f5
+;   br %r14
 
 function %vconst_i32x4_splat_i64() -> i32x4 {
 block0:
@@ -117,9 +212,20 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 12 ; data.u64 0x0000000100000002 ; vlrepg %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0xc
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   vlrepg %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i32x4_mixed() -> i32x4 {
 block0:
@@ -127,9 +233,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00000001000000020000000300000004 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x01
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x03
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x04
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i16x8_zero() -> i16x8 {
 block0:
@@ -137,9 +258,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i16x8_splat1() -> i16x8 {
 block0:
@@ -147,9 +274,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, 32767
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, 0x7fff
+;   br %r14
 
 function %vconst_i16x8_splat2() -> i16x8 {
 block0:
@@ -157,9 +290,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, -32768
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, -0x8000
+;   br %r14
 
 function %vconst_i16x8_mixed() -> i16x8 {
 block0:
@@ -167,9 +306,24 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00010002000300040005000600070008 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x01
+;   .byte 0x00, 0x02
+;   .byte 0x00, 0x03
+;   .byte 0x00, 0x04
+;   .byte 0x00, 0x05
+;   .byte 0x00, 0x06
+;   .byte 0x00, 0x07
+;   .byte 0x00, 0x08
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_i8x16_zero() -> i8x16 {
 block0:
@@ -177,9 +331,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_i8x16_splat1() -> i8x16 {
 block0:
@@ -187,9 +347,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 127
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x7f
+;   br %r14
 
 function %vconst_i8x16_splat2() -> i8x16 {
 block0:
@@ -197,9 +363,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 128
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x80
+;   br %r14
 
 function %vconst_i8x16_mixed() -> i8x16 {
 block0:
@@ -207,7 +379,22 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x0102030405060708090a0b0c0d0e0f10 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   upt
+;   .byte 0x03, 0x04
+;   balr %r0, %r6
+;   bcr 0, %r8
+;   .byte 0x09, 0x0a
+;   bsm %r0, %r12
+;   basr %r0, %r14
+;   .byte 0x0f, 0x10
+;   vl %v24, 0(%r1)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif
index 249d80ce92..5e5f1f80e3 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksg %v24, %v25, %v24
+;   br %r14
 
 function %snarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -17,9 +23,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksf %v24, %v25, %v24
+;   br %r14
 
 function %snarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -27,9 +39,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksh %v24, %v25, %v24
+;   br %r14
 
 function %unarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -37,12 +55,21 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxg %v5, %v24, %v3
 ;   vmxg %v7, %v25, %v3
 ;   vpklsg %v24, %v7, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxg %v5, %v24, %v3
+;   vmxg %v7, %v25, %v3
+;   vpklsg %v24, %v7, %v5
+;   br %r14
 
 function %unarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -50,12 +77,21 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxf %v5, %v24, %v3
 ;   vmxf %v7, %v25, %v3
 ;   vpklsf %v24, %v7, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxf %v5, %v24, %v3
+;   vmxf %v7, %v25, %v3
+;   vpklsf %v24, %v7, %v5
+;   br %r14
 
 function %unarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -63,12 +99,21 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxh %v5, %v24, %v3
 ;   vmxh %v7, %v25, %v3
 ;   vpklsh %v24, %v7, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxh %v5, %v24, %v3
+;   vmxh %v7, %v25, %v3
+;   vpklsh %v24, %v7, %v5
+;   br %r14
 
 function %uunarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -76,9 +121,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsg %v24, %v25, %v24
+;   br %r14
 
 function %uunarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -86,9 +137,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsf %v24, %v25, %v24
+;   br %r14
 
 function %uunarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -96,9 +153,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsh %v24, %v25, %v24
+;   br %r14
 
 function %swiden_low_i32x4_i64x2(i32x4) -> i64x2 wasmtime_system_v {
 block0(v0: i32x4):
@@ -106,9 +169,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplf %v24, %v24
+;   br %r14
 
 function %swiden_low_i16x8_i32x4(i16x8) -> i32x4 wasmtime_system_v {
 block0(v0: i16x8):
@@ -116,9 +185,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhw %v24, %v24
+;   br %r14
 
 function %swiden_low_i8x16_i16x8(i8x16) -> i16x8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -126,9 +201,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplb %v24, %v24
+;   br %r14
 
 function %swiden_high_i32x4_i64x2(i32x4) -> i64x2 wasmtime_system_v {
 block0(v0: i32x4):
@@ -136,9 +217,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v24, %v24
+;   br %r14
 
 function %swiden_high_i16x8_i32x4(i16x8) -> i32x4 wasmtime_system_v {
 block0(v0: i16x8):
@@ -146,9 +233,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphh %v24, %v24
+;   br %r14
 
 function %swiden_high_i8x16_i16x8(i8x16) -> i16x8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -156,9 +249,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphb %v24, %v24
+;   br %r14
 
 function %uwiden_low_i32x4_i64x2(i32x4) -> i64x2 wasmtime_system_v {
 block0(v0: i32x4):
@@ -166,9 +265,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllf %v24, %v24
+;   br %r14
 
 function %uwiden_low_i16x8_i32x4(i16x8) -> i32x4 wasmtime_system_v {
 block0(v0: i16x8):
@@ -176,9 +281,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllh %v24, %v24
+;   br %r14
 
 function %uwiden_low_i8x16_i16x8(i8x16) -> i16x8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -186,9 +297,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllb %v24, %v24
+;   br %r14
 
 function %uwiden_high_i32x4_i64x2(i32x4) -> i64x2 wasmtime_system_v {
 block0(v0: i32x4):
@@ -196,9 +313,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhf %v24, %v24
+;   br %r14
 
 function %uwiden_high_i16x8_i32x4(i16x8) -> i32x4 wasmtime_system_v {
 block0(v0: i16x8):
@@ -206,9 +329,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhh %v24, %v24
+;   br %r14
 
 function %uwiden_high_i8x16_i16x8(i8x16) -> i16x8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -216,7 +345,13 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhb %v24, %v24
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif b/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif
index 37dccadf94..ec43a3e940 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksg %v24, %v24, %v25
+;   br %r14
 
 function %snarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -17,9 +23,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksf %v24, %v24, %v25
+;   br %r14
 
 function %snarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -27,9 +39,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpksh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpksh %v24, %v24, %v25
+;   br %r14
 
 function %unarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 {
 block0(v0: i64x2, v1: i64x2):
@@ -37,12 +55,21 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxg %v5, %v24, %v3
 ;   vmxg %v7, %v25, %v3
 ;   vpklsg %v24, %v5, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxg %v5, %v24, %v3
+;   vmxg %v7, %v25, %v3
+;   vpklsg %v24, %v5, %v7
+;   br %r14
 
 function %unarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -50,12 +77,21 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxf %v5, %v24, %v3
 ;   vmxf %v7, %v25, %v3
 ;   vpklsf %v24, %v5, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxf %v5, %v24, %v3
+;   vmxf %v7, %v25, %v3
+;   vpklsf %v24, %v5, %v7
+;   br %r14
 
 function %unarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -63,12 +99,21 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vmxh %v5, %v24, %v3
 ;   vmxh %v7, %v25, %v3
 ;   vpklsh %v24, %v5, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vmxh %v5, %v24, %v3
+;   vmxh %v7, %v25, %v3
+;   vpklsh %v24, %v5, %v7
+;   br %r14
 
 function %uunarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 {
 block0(v0: i64x2, v1: i64x2):
@@ -76,9 +121,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsg %v24, %v24, %v25
+;   br %r14
 
 function %uunarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -86,9 +137,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsf %v24, %v24, %v25
+;   br %r14
 
 function %uunarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -96,9 +153,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vpklsh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpklsh %v24, %v24, %v25
+;   br %r14
 
 function %swiden_low_i32x4_i64x2(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -106,9 +169,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v24, %v24
+;   br %r14
 
 function %swiden_low_i16x8_i32x4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -116,9 +185,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphh %v24, %v24
+;   br %r14
 
 function %swiden_low_i8x16_i16x8(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -126,9 +201,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphb %v24, %v24
+;   br %r14
 
 function %swiden_high_i32x4_i64x2(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -136,9 +217,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplf %v24, %v24
+;   br %r14
 
 function %swiden_high_i16x8_i32x4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -146,9 +233,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhw %v24, %v24
+;   br %r14
 
 function %swiden_high_i8x16_i16x8(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -156,9 +249,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplb %v24, %v24
+;   br %r14
 
 function %uwiden_low_i32x4_i64x2(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -166,9 +265,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhf %v24, %v24
+;   br %r14
 
 function %uwiden_low_i16x8_i32x4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -176,9 +281,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhh %v24, %v24
+;   br %r14
 
 function %uwiden_low_i8x16_i16x8(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -186,9 +297,15 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhb %v24, %v24
+;   br %r14
 
 function %uwiden_high_i32x4_i64x2(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -196,9 +313,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllf %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllf %v24, %v24
+;   br %r14
 
 function %uwiden_high_i16x8_i32x4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -206,9 +329,15 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllh %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllh %v24, %v24
+;   br %r14
 
 function %uwiden_high_i8x16_i16x8(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -216,7 +345,13 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vupllb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vupllb %v24, %v24
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif b/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif
index 16bc92e6ee..ccf0478e79 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif
@@ -7,9 +7,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfcedb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_ne_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -17,10 +23,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfcedb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_gt_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -28,9 +41,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_lt_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -38,9 +57,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v24, %v25, %v24
+;   br %r14
 
 function %fcmp_ge_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -48,9 +73,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_le_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -58,9 +89,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v24, %v25, %v24
+;   br %r14
 
 function %fcmp_ueq_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -68,11 +105,19 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v3, %v24, %v25
 ;   vfchdb %v5, %v25, %v24
 ;   vno %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v3, %v24, %v25
+;   vfchdb %v5, %v25, %v24
+;   vno %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_one_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -80,11 +125,19 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v3, %v24, %v25
 ;   vfchdb %v5, %v25, %v24
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v3, %v24, %v25
+;   vfchdb %v5, %v25, %v24
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_ugt_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -92,10 +145,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ult_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -103,10 +163,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_uge_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -114,10 +181,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ule_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -125,10 +199,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchdb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ord_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -136,11 +217,19 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v3, %v24, %v25
 ;   vfchedb %v5, %v25, %v24
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v3, %v24, %v25
+;   vfchedb %v5, %v25, %v24
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_uno_f64x2(f64x2, f64x2) -> i64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -148,11 +237,19 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchedb %v3, %v24, %v25
 ;   vfchedb %v5, %v25, %v24
 ;   vno %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedb %v3, %v24, %v25
+;   vfchedb %v5, %v25, %v24
+;   vno %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_eq_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -160,9 +257,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfcesb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcesb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_ne_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -170,10 +273,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfcesb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcesb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_gt_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -181,9 +291,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_lt_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -191,9 +307,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v24, %v25, %v24
+;   br %r14
 
 function %fcmp_ge_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -201,9 +323,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v24, %v24, %v25
+;   br %r14
 
 function %fcmp_le_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -211,9 +339,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v24, %v25, %v24
+;   br %r14
 
 function %fcmp_ueq_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -221,11 +355,19 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v3, %v24, %v25
 ;   vfchsb %v5, %v25, %v24
 ;   vno %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v3, %v24, %v25
+;   vfchsb %v5, %v25, %v24
+;   vno %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_one_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -233,11 +375,19 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v3, %v24, %v25
 ;   vfchsb %v5, %v25, %v24
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v3, %v24, %v25
+;   vfchsb %v5, %v25, %v24
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_ugt_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -245,10 +395,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ult_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -256,10 +413,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_uge_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -267,10 +431,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ule_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -278,10 +449,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchsb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchsb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %fcmp_ord_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -289,11 +467,19 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v3, %v24, %v25
 ;   vfchesb %v5, %v25, %v24
 ;   vo %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v3, %v24, %v25
+;   vfchesb %v5, %v25, %v24
+;   vo %v24, %v3, %v5
+;   br %r14
 
 function %fcmp_uno_f32x4(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -301,9 +487,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfchesb %v3, %v24, %v25
 ;   vfchesb %v5, %v25, %v24
 ;   vno %v24, %v3, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchesb %v3, %v24, %v25
+;   vfchesb %v5, %v25, %v24
+;   vno %v24, %v3, %v5
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif
index ec89bc215a..cb4e4809f9 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif
@@ -7,9 +7,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcelfb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdlg %v24, %v24, 2, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i32x4_f32x4(i32x4) -> f32x4 {
 block0(v0: i32x4):
@@ -17,9 +23,15 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcefb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdg %v24, %v24, 2, 0, 4
+;   br %r14
 
 function %fcvt_from_uint_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -27,9 +39,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcdlgb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdlgb %v24, %v24, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -37,10 +55,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcdgb %v24, %v24, 0, 4
 ;   br %r14
-
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdgb %v24, %v24, 0, 4
+;   br %r14
 
 function %fcvt_to_uint_sat_f32x4_i32x4(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -48,9 +71,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vclfeb %v24, %v24, 0, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgd %v24, %v24, 2, 0, 5
+;   br %r14
 
 function %fcvt_to_sint_sat_f32x4_i32x4(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -58,12 +87,21 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcfeb %v2, %v24, 0, 5
 ;   vgbm %v4, 0
 ;   vfcesb %v6, %v24, %v24
 ;   vsel %v24, %v2, %v4, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgd %v2, %v24, 2, 0, 5
+;   vzero %v4
+;   vfcesb %v6, %v24, %v24
+;   vsel %v24, %v2, %v4, %v6
+;   br %r14
 
 function %fcvt_to_uint_sat_f64x2_i64x2(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -71,9 +109,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vclgdb %v24, %v24, 0, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgdb %v24, %v24, 0, 5
+;   br %r14
 
 function %fcvt_to_sint_sat_f64x2_i64x2(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -81,10 +125,19 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcgdb %v2, %v24, 0, 5
 ;   vgbm %v4, 0
 ;   vfcedb %v6, %v24, %v24
 ;   vsel %v24, %v2, %v4, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgdb %v2, %v24, 0, 5
+;   vzero %v4
+;   vfcedb %v6, %v24, %v24
+;   vsel %v24, %v2, %v4, %v6
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fp.clif b/cranelift/filetests/filetests/isa/s390x/vec-fp.clif
index e93a9fcaef..3a18c5efeb 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-fp.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-fp.clif
@@ -7,9 +7,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_f64x2_zero() -> f64x2 {
 block0:
@@ -17,9 +23,15 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   br %r14
 
 function %vconst_f32x4_mixed_be() -> f32x4 {
 block0:
@@ -27,9 +39,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x3f800000400000004040000040800000 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   sur %f8, %f0
+;   .byte 0x00, 0x00
+;   sth %r0, 0
+;   sth %r4, 0
+;   sth %r8, 0
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_f32x4_mixed_le() -> f32x4 wasmtime_system_v {
 block0:
@@ -37,9 +61,21 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x4080000040400000400000003f800000 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   sth %r8, 0
+;   sth %r4, 0
+;   sth %r0, 0
+;   sur %f8, %f0
+;   .byte 0x00, 0x00
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_f64x2_mixed_be() -> f64x2 {
 block0:
@@ -47,9 +83,23 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x3ff00000000000004000000000000000 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   sur %f15, %f0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   sth %r0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %vconst_f64x2_mixed_le() -> f64x2 wasmtime_system_v {
 block0:
@@ -57,9 +107,23 @@ block0:
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x40000000000000003ff0000000000000 ; vl %v24, 0(%r1)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   sth %r0, 0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   sur %f15, %f0
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   .byte 0x00, 0x00
+;   vl %v24, 0(%r1)
+;   br %r14
 
 function %fadd_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -67,9 +131,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfasb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfasb %v24, %v24, %v25
+;   br %r14
 
 function %fadd_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -77,9 +147,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfadb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfadb %v24, %v24, %v25
+;   br %r14
 
 function %fsub_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -87,9 +163,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfssb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfssb %v24, %v24, %v25
+;   br %r14
 
 function %fsub_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -97,9 +179,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfsdb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfsdb %v24, %v24, %v25
+;   br %r14
 
 function %fmul_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -107,9 +195,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmsb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmsb %v24, %v24, %v25
+;   br %r14
 
 function %fmul_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -117,9 +211,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmdb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmdb %v24, %v24, %v25
+;   br %r14
 
 function %fdiv_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -127,9 +227,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfdsb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfdsb %v24, %v24, %v25
+;   br %r14
 
 function %fdiv_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -137,9 +243,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfddb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfddb %v24, %v24, %v25
+;   br %r14
 
 function %fmin_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -147,9 +259,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfminsb %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfminsb %v24, %v24, %v25, 1
+;   br %r14
 
 function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -157,9 +275,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmindb %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmindb %v24, %v24, %v25, 1
+;   br %r14
 
 function %fmax_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -167,9 +291,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmaxsb %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmaxsb %v24, %v24, %v25, 1
+;   br %r14
 
 function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -177,9 +307,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmaxdb %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmaxdb %v24, %v24, %v25, 1
+;   br %r14
 
 function %fmin_pseudo_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -187,9 +323,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfminsb %v24, %v24, %v25, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfminsb %v24, %v24, %v25, 3
+;   br %r14
 
 function %fmin_pseudo_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -197,9 +339,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmindb %v24, %v24, %v25, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmindb %v24, %v24, %v25, 3
+;   br %r14
 
 function %fmax_pseudo_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -207,9 +355,15 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmaxsb %v24, %v24, %v25, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmaxsb %v24, %v24, %v25, 3
+;   br %r14
 
 function %fmax_pseudo_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -217,9 +371,15 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vfmaxdb %v24, %v24, %v25, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmaxdb %v24, %v24, %v25, 3
+;   br %r14
 
 function %sqrt_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -227,9 +387,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfsqsb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfsqsb %v24, %v24
+;   br %r14
 
 function %sqrt_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -237,9 +403,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfsqdb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfsqdb %v24, %v24
+;   br %r14
 
 function %fabs_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -247,9 +419,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vflpsb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vflpsb %v24, %v24
+;   br %r14
 
 function %fabs_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -257,9 +435,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vflpdb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vflpdb %v24, %v24
+;   br %r14
 
 function %fneg_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -267,9 +451,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vflcsb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vflcsb %v24, %v24
+;   br %r14
 
 function %fneg_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -277,9 +467,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vflcdb %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vflcdb %v24, %v24
+;   br %r14
 
 function %fvpromote_low_f32x4_be(f32x4) -> f64x2 {
 block0(v0: f32x4):
@@ -287,10 +483,17 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v2, %v24, %v24
 ;   vldeb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v2, %v24, %v24
+;   vldeb %v24, %v2
+;   br %r14
 
 function %fvpromote_low_f32x4_le(f32x4) -> f64x2 wasmtime_system_v {
 block0(v0: f32x4):
@@ -298,10 +501,17 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v2, %v24, %v24
 ;   vldeb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v2, %v24, %v24
+;   vldeb %v24, %v2
+;   br %r14
 
 function %fvdemote_f64x2_be(f64x2) -> f32x4 {
 block0(v0: f64x2):
@@ -309,12 +519,21 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vledb %v2, %v24, 0, 0
 ;   vesrlg %v4, %v2, 32
 ;   vgbm %v6, 0
 ;   vpkg %v24, %v4, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vledb %v2, %v24, 0, 0
+;   vesrlg %v4, %v2, 0x20
+;   vzero %v6
+;   vpkg %v24, %v4, %v6
+;   br %r14
 
 function %fvdemote_f64x2_le(f64x2) -> f32x4 wasmtime_system_v {
 block0(v0: f64x2):
@@ -322,12 +541,21 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vledb %v2, %v24, 0, 0
 ;   vesrlg %v4, %v2, 32
 ;   vgbm %v6, 0
 ;   vpkg %v24, %v6, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vledb %v2, %v24, 0, 0
+;   vesrlg %v4, %v2, 0x20
+;   vzero %v6
+;   vpkg %v24, %v6, %v4
+;   br %r14
 
 function %ceil_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -335,9 +563,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfisb %v24, %v24, 0, 6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfisb %v24, %v24, 0, 6
+;   br %r14
 
 function %ceil_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -345,9 +579,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfidb %v24, %v24, 0, 6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfidb %v24, %v24, 0, 6
+;   br %r14
 
 function %floor_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -355,9 +595,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfisb %v24, %v24, 0, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfisb %v24, %v24, 0, 7
+;   br %r14
 
 function %floor_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -365,9 +611,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfidb %v24, %v24, 0, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfidb %v24, %v24, 0, 7
+;   br %r14
 
 function %trunc_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -375,9 +627,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfisb %v24, %v24, 0, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfisb %v24, %v24, 0, 5
+;   br %r14
 
 function %trunc_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -385,9 +643,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfidb %v24, %v24, 0, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfidb %v24, %v24, 0, 5
+;   br %r14
 
 function %nearest_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -395,9 +659,15 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfisb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfisb %v24, %v24, 0, 4
+;   br %r14
 
 function %nearest_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -405,9 +675,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vfidb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfidb %v24, %v24, 0, 4
+;   br %r14
 
 function %fma_f32x4(f32x4, f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4, v2: f32x4):
@@ -415,9 +691,15 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vfmasb %v24, %v24, %v25, %v26
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmasb %v24, %v24, %v25, %v26
+;   br %r14
 
 function %fma_f64x2(f64x2, f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2, v2: f64x2):
@@ -425,9 +707,15 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   vfmadb %v24, %v24, %v25, %v26
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfmadb %v24, %v24, %v25, %v26
+;   br %r14
 
 function %fcopysign_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -435,10 +723,17 @@ block0(v0: f32x4, v1: f32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgmf %v3, 1, 31
 ;   vsel %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgmf %v3, 1, 0x1f
+;   vsel %v24, %v24, %v25, %v3
+;   br %r14
 
 function %fcopysign_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -446,10 +741,17 @@ block0(v0: f64x2, v1: f64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vgmg %v3, 1, 63
 ;   vsel %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgmg %v3, 1, 0x3f
+;   vsel %v24, %v24, %v25, %v3
+;   br %r14
 
 function %fcvt_from_uint_i32x4_f32x4(i32x4) -> f32x4 {
 block0(v0: i32x4):
@@ -457,6 +759,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplhf %v2, %v24
 ;   vcdlgb %v4, %v2, 0, 3
@@ -467,6 +770,27 @@ block0(v0: i32x4):
 ;   bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v22, 0(%r1)
 ;   vperm %v24, %v6, %v20, %v22
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplhf %v2, %v24
+;   vcdlgb %v4, %v2, 0, 3
+;   vledb %v6, %v4, 0, 4
+;   vupllf %v16, %v24
+;   vcdlgb %v18, %v16, 0, 3
+;   vledb %v20, %v18, 0, 4
+;   bras %r1, 0x38
+;   .byte 0x00, 0x01
+;   .byte 0x02, 0x03
+;   .byte 0x08, 0x09
+;   svc 0xb
+;   lpr %r1, %r1
+;   ltr %r1, %r3
+;   lr %r1, %r9
+;   ar %r1, %r11
+;   vl %v22, 0(%r1)
+;   vperm %v24, %v6, %v20, %v22
+;   br %r14
 
 function %fcvt_from_sint_i32x4_f32x4(i32x4) -> f32x4 {
 block0(v0: i32x4):
@@ -474,6 +798,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v2, %v24
 ;   vcdgb %v4, %v2, 0, 3
@@ -484,6 +809,27 @@ block0(v0: i32x4):
 ;   bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v22, 0(%r1)
 ;   vperm %v24, %v6, %v20, %v22
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v2, %v24
+;   vcdgb %v4, %v2, 0, 3
+;   vledb %v6, %v4, 0, 4
+;   vuplf %v16, %v24
+;   vcdgb %v18, %v16, 0, 3
+;   vledb %v20, %v18, 0, 4
+;   bras %r1, 0x38
+;   .byte 0x00, 0x01
+;   .byte 0x02, 0x03
+;   .byte 0x08, 0x09
+;   svc 0xb
+;   lpr %r1, %r1
+;   ltr %r1, %r3
+;   lr %r1, %r9
+;   ar %r1, %r11
+;   vl %v22, 0(%r1)
+;   vperm %v24, %v6, %v20, %v22
+;   br %r14
 
 function %fcvt_from_uint_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -491,9 +837,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcdlgb %v24, %v24, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdlgb %v24, %v24, 0, 4
+;   br %r14
 
 function %fcvt_from_sint_i64x2_f64x2(i64x2) -> f64x2 {
 block0(v0: i64x2):
@@ -501,10 +853,15 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcdgb %v24, %v24, 0, 4
 ;   br %r14
-
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcdgb %v24, %v24, 0, 4
+;   br %r14
 
 function %fcvt_low_from_sint_i32x4_f64x2_be(i32x4) -> f64x2 {
 block0(v0: i32x4):
@@ -512,10 +869,17 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuphf %v2, %v24
 ;   vcdgb %v24, %v2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuphf %v2, %v24
+;   vcdgb %v24, %v2, 0, 4
+;   br %r14
 
 function %fcvt_low_from_sint_i32x4_f64x2_le(i32x4) -> f64x2 wasmtime_system_v {
 block0(v0: i32x4):
@@ -523,10 +887,17 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vuplf %v2, %v24
 ;   vcdgb %v24, %v2, 0, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vuplf %v2, %v24
+;   vcdgb %v24, %v2, 0, 4
+;   br %r14
 
 function %fcvt_to_uint_sat_f32x4_i32x4(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -534,6 +905,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v2, %v24, %v24
 ;   vldeb %v4, %v2
@@ -543,6 +915,17 @@ block0(v0: f32x4):
 ;   vclgdb %v20, %v18, 0, 5
 ;   vpklsg %v24, %v6, %v20
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v2, %v24, %v24
+;   vldeb %v4, %v2
+;   vclgdb %v6, %v4, 0, 5
+;   vmrlf %v16, %v24, %v24
+;   vldeb %v18, %v16
+;   vclgdb %v20, %v18, 0, 5
+;   vpklsg %v24, %v6, %v20
+;   br %r14
 
 function %fcvt_to_sint_sat_f32x4_i32x4(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -550,6 +933,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v2, %v24, %v24
 ;   vldeb %v4, %v2
@@ -562,6 +946,20 @@ block0(v0: f32x4):
 ;   vfcesb %v26, %v24, %v24
 ;   vsel %v24, %v22, %v25, %v26
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v2, %v24, %v24
+;   vldeb %v4, %v2
+;   vcgdb %v6, %v4, 0, 5
+;   vmrlf %v16, %v24, %v24
+;   vldeb %v18, %v16
+;   vcgdb %v20, %v18, 0, 5
+;   vpksg %v22, %v6, %v20
+;   vzero %v25
+;   vfcesb %v26, %v24, %v24
+;   vsel %v24, %v22, %v25, %v26
+;   br %r14
 
 function %fcvt_to_uint_sat_f64x2_i64x2(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -569,9 +967,15 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vclgdb %v24, %v24, 0, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vclgdb %v24, %v24, 0, 5
+;   br %r14
 
 function %fcvt_to_sint_sat_f64x2_i64x2(f64x2) -> i64x2 {
 block0(v0: f64x2):
@@ -579,10 +983,19 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vcgdb %v2, %v24, 0, 5
 ;   vgbm %v4, 0
 ;   vfcedb %v6, %v24, %v24
 ;   vsel %v24, %v2, %v4, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vcgdb %v2, %v24, 0, 5
+;   vzero %v4
+;   vfcedb %v6, %v24, %v24
+;   vsel %v24, %v2, %v4, %v6
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif b/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif
index b4f812532e..d3ae8b0528 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqg %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ne_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -17,10 +23,17 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqg %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqg %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sgt_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -28,9 +41,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchg %v24, %v24, %v25
+;   br %r14
 
 function %icmp_slt_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -38,9 +57,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchg %v24, %v25, %v24
+;   br %r14
 
 function %icmp_sge_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -48,10 +73,17 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchg %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchg %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sle_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -59,10 +91,17 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchg %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchg %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ugt_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -70,9 +109,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlg %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ult_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -80,9 +125,15 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlg %v24, %v25, %v24
+;   br %r14
 
 function %icmp_uge_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -90,10 +141,17 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlg %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlg %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ule_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -101,10 +159,17 @@ block0(v0: i64x2, v1: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlg %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlg %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_eq_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -112,9 +177,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqf %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ne_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -122,10 +193,17 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqf %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqf %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sgt_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -133,9 +211,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchf %v24, %v24, %v25
+;   br %r14
 
 function %icmp_slt_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -143,9 +227,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchf %v24, %v25, %v24
+;   br %r14
 
 function %icmp_sge_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -153,10 +243,17 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchf %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchf %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sle_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -164,10 +261,17 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchf %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchf %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -175,9 +279,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlf %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ult_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -185,9 +295,15 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlf %v24, %v25, %v24
+;   br %r14
 
 function %icmp_uge_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -195,10 +311,17 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlf %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlf %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ule_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -206,10 +329,17 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlf %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlf %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_eq_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -217,9 +347,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqh %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ne_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -227,10 +363,17 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqh %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqh %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sgt_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -238,9 +381,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchh %v24, %v24, %v25
+;   br %r14
 
 function %icmp_slt_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -248,9 +397,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchh %v24, %v25, %v24
+;   br %r14
 
 function %icmp_sge_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -258,10 +413,17 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchh %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchh %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sle_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -269,10 +431,17 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchh %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchh %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ugt_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -280,9 +449,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlh %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ult_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -290,9 +465,15 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlh %v24, %v25, %v24
+;   br %r14
 
 function %icmp_uge_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -300,10 +481,17 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlh %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlh %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ule_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -311,10 +499,17 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlh %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlh %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_eq_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -322,9 +517,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqb %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ne_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -332,10 +533,17 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vceqb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sgt_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -343,9 +551,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchb %v24, %v24, %v25
+;   br %r14
 
 function %icmp_slt_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -353,9 +567,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchb %v24, %v25, %v24
+;   br %r14
 
 function %icmp_sge_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -363,10 +583,17 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_sle_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -374,10 +601,17 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ugt_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -385,9 +619,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlb %v24, %v24, %v25
+;   br %r14
 
 function %icmp_ult_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -395,9 +635,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlb %v24, %v25, %v24
+;   br %r14
 
 function %icmp_uge_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -405,10 +651,17 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlb %v3, %v25, %v24
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlb %v3, %v25, %v24
+;   vno %v24, %v3, %v3
+;   br %r14
 
 function %icmp_ule_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -416,8 +669,15 @@ block0(v0: i8x16, v1: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vchlb %v3, %v24, %v25
 ;   vno %v24, %v3, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlb %v3, %v24, %v25
+;   vno %v24, %v3, %v3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane-arch13.clif
index 9fc1406e31..7ce4b474e7 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-lane-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-lane-arch13.clif
@@ -8,9 +8,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i64x2_mem_1(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -19,9 +25,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_i64x2_mem_little_0(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -30,9 +42,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -41,9 +61,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -52,9 +80,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -63,9 +97,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_0(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -74,9 +114,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -85,9 +133,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -96,9 +152,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i16x8_mem_7(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -107,9 +169,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %insertlane_i16x8_mem_little_0(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -118,9 +186,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x01
+;   br %r14
 
 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -129,9 +205,16 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   le %f0, 0x7fe(%r1)
 
 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -140,9 +223,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_15(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -151,9 +240,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_little_0(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -162,9 +257,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_little_15(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -173,9 +274,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_f64x2_mem_0(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -184,9 +291,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_mem_1(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -195,9 +308,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_f64x2_mem_little_0(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -206,9 +325,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -217,9 +344,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 {
 block0(v0: f32x4, v1: i64):
@@ -228,9 +363,15 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -239,9 +380,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_f32x4_mem_little_0(f32x4, i64) -> f32x4 {
 block0(v0: f32x4, v1: i64):
@@ -250,9 +397,17 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -261,9 +416,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
 function %extractlane_i64x2_mem_0(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -272,9 +435,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i64x2_mem_1(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -283,9 +452,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_i64x2_mem_little_0(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -294,9 +469,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0a
+;   br %r14
 
 function %extractlane_i64x2_mem_little_1(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -305,9 +488,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r10
+;   br %r14
 
 function %extractlane_i32x4_mem_0(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -316,9 +507,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i32x4_mem_3(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -327,9 +524,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_i32x4_mem_little_0(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -338,9 +541,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0b
+;   br %r14
 
 function %extractlane_i32x4_mem_little_3(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -349,9 +560,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f11
+;   br %r14
 
 function %extractlane_i16x8_mem_0(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -360,9 +579,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i16x8_mem_7(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -371,9 +596,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 7
+;   br %r14
 
 function %extractlane_i16x8_mem_little_0(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -382,9 +613,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x09
+;   br %r14
 
 function %extractlane_i16x8_mem_little_7(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -393,9 +632,16 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   le %f0, 0x7fe(%r9)
 
 function %extractlane_i8x16_mem_0(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -404,9 +650,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_15(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -415,9 +667,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_little_0(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -426,9 +684,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_little_15(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -437,9 +701,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_f64x2_mem_0(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -448,9 +718,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_mem_1(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -459,9 +735,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_f64x2_mem_little_0(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -470,9 +752,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0a
+;   br %r14
 
 function %extractlane_f64x2_mem_little_1(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -481,9 +771,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r10
+;   br %r14
 
 function %extractlane_f32x4_mem_0(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -492,9 +790,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f32x4_mem_3(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -503,9 +807,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_f32x4_mem_little_0(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -514,9 +824,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0b
+;   br %r14
 
 function %extractlane_f32x4_mem_little_3(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -525,9 +843,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f11
+;   br %r14
 
 function %splat_i64x2_mem(i64) -> i64x2 {
 block0(v0: i64):
@@ -536,9 +862,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_i64x2_mem_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -547,9 +879,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f5
+;   br %r14
 
 function %splat_i32x4_mem(i64) -> i32x4 {
 block0(v0: i64):
@@ -558,9 +898,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_i32x4_mem_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -569,9 +915,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f5
+;   br %r14
 
 function %splat_i16x8_mem(i64) -> i16x8 {
 block0(v0: i64):
@@ -580,9 +934,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlreph %v24, 0(%r2)
+;   br %r14
 
 function %splat_i16x8_mem_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -591,9 +951,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r5
+;   br %r14
 
 function %splat_i8x16_mem(i64) -> i8x16 {
 block0(v0: i64):
@@ -602,9 +970,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_i8x16_mem_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -613,9 +987,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem(i64) -> f64x2 {
 block0(v0: i64):
@@ -624,9 +1004,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -635,9 +1021,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f5
+;   br %r14
 
 function %splat_f32x4_mem(i64) -> f32x4 {
 block0(v0: i64):
@@ -646,9 +1040,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_f32x4_mem_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -657,9 +1057,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f5
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 {
 block0(v0: i64):
@@ -668,10 +1076,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -680,10 +1095,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 {
 block0(v0: i64):
@@ -692,10 +1116,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -704,10 +1135,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 {
 block0(v0: i64):
@@ -716,10 +1156,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -728,10 +1175,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x01
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 {
 block0(v0: i64):
@@ -740,10 +1196,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -752,10 +1215,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 {
 block0(v0: i64):
@@ -764,10 +1234,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -776,10 +1253,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 {
 block0(v0: i64):
@@ -788,10 +1274,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -800,8 +1293,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane-arch13.clif
index 19fbc0827e..f3885f4a20 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane-arch13.clif
@@ -8,9 +8,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_i64x2_mem_1(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -19,9 +25,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i64x2_mem_little_0(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -30,9 +42,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -41,9 +61,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -52,9 +80,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -63,9 +97,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_little_0(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -74,9 +114,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -85,9 +133,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -96,9 +152,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %insertlane_i16x8_mem_7(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -107,9 +169,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i16x8_mem_little_0(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -118,9 +186,16 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   le %f0, 0x7fe(%r1)
 
 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -129,9 +204,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x01
+;   br %r14
 
 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -140,9 +223,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_15(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -151,9 +240,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_little_0(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -162,9 +257,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_little_15(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -173,9 +274,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_mem_0(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -184,9 +291,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_f64x2_mem_1(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -195,9 +308,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_mem_little_0(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -206,9 +325,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -217,9 +344,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x02
+;   br %r14
 
 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -228,9 +363,15 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -239,9 +380,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f32x4_mem_little_0(f32x4, i64) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -250,9 +397,17 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -261,9 +416,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x03
+;   br %r14
 
 function %extractlane_i64x2_mem_0(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -272,9 +435,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_i64x2_mem_1(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -283,9 +452,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i64x2_mem_little_0(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -294,9 +469,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r10
+;   br %r14
 
 function %extractlane_i64x2_mem_little_1(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -305,9 +488,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0a
+;   br %r14
 
 function %extractlane_i32x4_mem_0(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -316,9 +507,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_i32x4_mem_3(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -327,9 +524,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i32x4_mem_little_0(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -338,9 +541,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f11
+;   br %r14
 
 function %extractlane_i32x4_mem_little_3(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -349,9 +560,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0b
+;   br %r14
 
 function %extractlane_i16x8_mem_0(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -360,9 +579,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 7
+;   br %r14
 
 function %extractlane_i16x8_mem_7(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -371,9 +596,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i16x8_mem_little_0(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -382,9 +613,16 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   le %f0, 0x7fe(%r9)
 
 function %extractlane_i16x8_mem_little_7(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -393,9 +631,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x09
+;   br %r14
 
 function %extractlane_i8x16_mem_0(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -404,9 +650,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_15(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -415,9 +667,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_little_0(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -426,9 +684,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_little_15(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -437,9 +701,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_mem_0(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -448,9 +718,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_f64x2_mem_1(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -459,9 +735,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_mem_little_0(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -470,9 +752,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r10
+;   br %r14
 
 function %extractlane_f64x2_mem_little_1(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -481,9 +771,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0a
+;   br %r14
 
 function %extractlane_f32x4_mem_0(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -492,9 +790,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_f32x4_mem_3(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -503,9 +807,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f32x4_mem_little_0(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -514,9 +824,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f11
+;   br %r14
 
 function %extractlane_f32x4_mem_little_3(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -525,9 +843,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstebrf %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   .byte 0x08, 0x0b
+;   br %r14
 
 function %splat_i64x2_mem(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -536,9 +862,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_i64x2_mem_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -547,9 +879,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f5
+;   br %r14
 
 function %splat_i32x4_mem(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -558,9 +898,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_i32x4_mem_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -569,9 +915,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f5
+;   br %r14
 
 function %splat_i16x8_mem(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -580,9 +934,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlreph %v24, 0(%r2)
+;   br %r14
 
 function %splat_i16x8_mem_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -591,9 +951,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r5
+;   br %r14
 
 function %splat_i8x16_mem(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -602,9 +970,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_i8x16_mem_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -613,9 +987,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -624,9 +1004,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -635,9 +1021,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f5
+;   br %r14
 
 function %splat_f32x4_mem(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -646,9 +1040,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_f32x4_mem_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -657,9 +1057,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlbrrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f5
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -668,10 +1076,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -680,10 +1095,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -692,10 +1116,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -704,10 +1135,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -716,10 +1156,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -728,10 +1175,18 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   le %f0, 0x7fe(%r1)
 
 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -740,10 +1195,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -752,10 +1214,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -764,10 +1233,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -776,10 +1252,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r2
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -788,10 +1273,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -800,8 +1292,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlebrf %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif
index 3c60ac3325..913bfbd18e 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgg %v24, %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgg %v24, %r2, 1
+;   br %r14
 
 function %insertlane_i64x2_1(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -17,9 +23,15 @@ block0(v0: i64x2, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgg %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgg %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i64x2_imm_0(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -28,9 +40,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleig %v24, 123, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleig %v24, 0x7b, 1
+;   br %r14
 
 function %insertlane_i64x2_imm_1(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -39,9 +57,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleig %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleig %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i64x2_lane_0_0(i64x2, i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -50,9 +74,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 1
+;   br %r14
 
 function %insertlane_i64x2_lane_0_1(i64x2, i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -61,9 +91,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 5
+;   br %r14
 
 function %insertlane_i64x2_lane_1_0(i64x2, i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -72,9 +108,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 0
+;   br %r14
 
 function %insertlane_i64x2_lane_1_1(i64x2, i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64x2):
@@ -83,9 +125,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 1
+;   br %r14
 
 function %insertlane_i64x2_mem_0(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -94,9 +142,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_i64x2_mem_1(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -105,9 +159,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i64x2_mem_little_0(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -116,10 +176,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 1
+;   br %r14
 
 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -128,10 +195,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i32x4_0(i32x4, i32) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32):
@@ -139,9 +213,15 @@ block0(v0: i32x4, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v24, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v24, %r2, 3
+;   br %r14
 
 function %insertlane_i32x4_3(i32x4, i32) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32):
@@ -149,9 +229,15 @@ block0(v0: i32x4, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i32x4_imm_0(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -160,9 +246,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleif %v24, 123, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleif %v24, 0x7b, 3
+;   br %r14
 
 function %insertlane_i32x4_imm_3(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -171,9 +263,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleif %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleif %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i32x4_lane_0_0(i32x4, i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -182,10 +280,17 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 15
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i32x4_lane_0_3(i32x4, i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -194,11 +299,19 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 3
 ;   vgbm %v5, 61440
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 3
+;   vgbm %v5, 0xf000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i32x4_lane_3_0(i32x4, i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -207,11 +320,19 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i32x4_lane_3_3(i32x4, i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i32x4):
@@ -220,10 +341,17 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -232,9 +360,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -243,9 +377,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_little_0(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -254,10 +394,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -266,10 +413,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i16x8_0(i16x8, i16) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16):
@@ -277,9 +431,15 @@ block0(v0: i16x8, v1: i16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v24, %r2, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v24, %r2, 7
+;   br %r14
 
 function %insertlane_i16x8_7(i16x8, i16) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16):
@@ -287,9 +447,15 @@ block0(v0: i16x8, v1: i16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i16x8_imm_0(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -298,9 +464,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleih %v24, 123, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleih %v24, 0x7b, 7
+;   br %r14
 
 function %insertlane_i16x8_imm_7(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -309,9 +481,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleih %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleih %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i16x8_lane_0_0(i16x8, i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -320,10 +498,17 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 3
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 3
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i16x8_lane_0_7(i16x8, i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -332,11 +517,19 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vreph %v3, %v25, 7
 ;   vgbm %v5, 49152
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v3, %v25, 7
+;   vgbm %v5, 0xc000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i16x8_lane_7_0(i16x8, i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -345,11 +538,19 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vreph %v3, %v25, 0
 ;   vgbm %v5, 3
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v3, %v25, 0
+;   vgbm %v5, 3
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i16x8_lane_7_7(i16x8, i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i16x8):
@@ -358,10 +559,17 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 49152
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xc000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -370,9 +578,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %insertlane_i16x8_mem_7(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -381,9 +595,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i16x8_mem_little_0(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -392,10 +612,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r5, 0(%r2)
 ;   vlvgh %v24, %r5, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r5, 0(%r2)
+;   vlvgh %v24, %r5, 7
+;   br %r14
 
 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -404,10 +631,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r5, 0(%r2)
 ;   vlvgh %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r5, 0(%r2)
+;   vlvgh %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i8x16_0(i8x16, i8) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8):
@@ -415,9 +649,15 @@ block0(v0: i8x16, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v24, %r2, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v24, %r2, 0xf
+;   br %r14
 
 function %insertlane_i8x16_15(i8x16, i8) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8):
@@ -425,9 +665,15 @@ block0(v0: i8x16, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i8x16_imm_0(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -436,9 +682,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleib %v24, 123, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleib %v24, 0x7b, 0xf
+;   br %r14
 
 function %insertlane_i8x16_imm_15(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -447,9 +699,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleib %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleib %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i8x16_lane_0_0(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -458,10 +716,17 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 1
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 1
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i8x16_lane_0_15(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -470,11 +735,19 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v3, %v25, 15
 ;   vgbm %v5, 32768
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v3, %v25, 0xf
+;   vgbm %v5, 0x8000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i8x16_lane_15_0(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -483,11 +756,19 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v3, %v25, 0
 ;   vgbm %v5, 1
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v3, %v25, 0
+;   vgbm %v5, 1
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i8x16_lane_15_15(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -496,10 +777,17 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 32768
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0x8000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -508,9 +796,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_15(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -519,9 +813,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_little_0(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -530,9 +830,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_little_15(i8x16, i64) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -541,9 +847,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_0(f64x2, f64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64):
@@ -551,9 +863,15 @@ block0(v0: f64x2, v1: f64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v0, 0
+;   br %r14
 
 function %insertlane_f64x2_1(f64x2, f64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64):
@@ -561,9 +879,15 @@ block0(v0: f64x2, v1: f64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v0, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v0, %v24, 1
+;   br %r14
 
 function %insertlane_f64x2_lane_0_0(f64x2, f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64x2):
@@ -572,9 +896,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 1
+;   br %r14
 
 function %insertlane_f64x2_lane_0_1(f64x2, f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64x2):
@@ -583,9 +913,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 5
+;   br %r14
 
 function %insertlane_f64x2_lane_1_0(f64x2, f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64x2):
@@ -594,9 +930,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 0
+;   br %r14
 
 function %insertlane_f64x2_lane_1_1(f64x2, f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: f64x2):
@@ -605,9 +947,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 1
+;   br %r14
 
 function %insertlane_f64x2_mem_0(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -616,9 +964,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_f64x2_mem_1(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -627,9 +981,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_mem_little_0(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -638,10 +998,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 1
+;   br %r14
 
 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -650,10 +1017,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 0
+;   br %r14
 
 function %insertlane_f32x4_0(f32x4, f32) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32):
@@ -661,11 +1035,19 @@ block0(v0: f32x4, v1: f32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v0, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v0, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_3(f32x4, f32) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32):
@@ -673,10 +1055,17 @@ block0(v0: f32x4, v1: f32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v0, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v0, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_lane_0_0(f32x4, f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32x4):
@@ -685,10 +1074,17 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 15
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_lane_0_3(f32x4, f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32x4):
@@ -697,11 +1093,19 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 3
 ;   vgbm %v5, 61440
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 3
+;   vgbm %v5, 0xf000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_lane_3_0(f32x4, f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32x4):
@@ -710,11 +1114,19 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_lane_3_3(f32x4, f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: f32x4):
@@ -723,10 +1135,17 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -735,9 +1154,15 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -746,9 +1171,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f32x4_mem_little_0(f32x4, i64) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -757,10 +1188,17 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -769,10 +1207,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 0
+;   br %r14
 
 function %extractlane_i64x2_0(i64x2) -> i64 wasmtime_system_v {
 block0(v0: i64x2):
@@ -780,9 +1225,15 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r2, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r2, %v24, 1
+;   br %r14
 
 function %extractlane_i64x2_1(i64x2) -> i64 wasmtime_system_v {
 block0(v0: i64x2):
@@ -790,9 +1241,15 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i64x2_mem_0(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -801,9 +1258,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_i64x2_mem_1(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -812,9 +1275,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i64x2_mem_little_0(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -823,10 +1292,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i64x2_mem_little_1(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -835,10 +1311,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i32x4_0(i32x4) -> i32 wasmtime_system_v {
 block0(v0: i32x4):
@@ -846,9 +1329,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r2, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r2, %v24, 3
+;   br %r14
 
 function %extractlane_i32x4_3(i32x4) -> i32 wasmtime_system_v {
 block0(v0: i32x4):
@@ -856,9 +1345,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i32x4_mem_0(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -867,9 +1362,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_i32x4_mem_3(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -878,9 +1379,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i32x4_mem_little_0(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -889,10 +1396,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 3
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 3
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i32x4_mem_little_3(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -901,10 +1415,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 0
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 0
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i16x8_0(i16x8) -> i16 wasmtime_system_v {
 block0(v0: i16x8):
@@ -912,9 +1433,15 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r2, %v24, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r2, %v24, 7
+;   br %r14
 
 function %extractlane_i16x8_7(i16x8) -> i16 wasmtime_system_v {
 block0(v0: i16x8):
@@ -922,9 +1449,15 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i16x8_mem_0(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -933,9 +1466,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 7
+;   br %r14
 
 function %extractlane_i16x8_mem_7(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -944,9 +1483,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i16x8_mem_little_0(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -955,10 +1500,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r5, %v24, 7
 ;   strvh %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r5, %v24, 7
+;   strvh %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i16x8_mem_little_7(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -967,10 +1519,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r5, %v24, 0
 ;   strvh %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r5, %v24, 0
+;   strvh %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i8x16_0(i8x16) -> i8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -978,9 +1537,15 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvb %r2, %v24, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvb %r2, %v24, 0xf
+;   br %r14
 
 function %extractlane_i8x16_15(i8x16) -> i8 wasmtime_system_v {
 block0(v0: i8x16):
@@ -988,9 +1553,15 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvb %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvb %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i8x16_mem_0(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -999,9 +1570,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_15(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -1010,9 +1587,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_little_0(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -1021,9 +1604,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_little_15(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -1032,9 +1621,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_0(f64x2) -> f64 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1042,9 +1637,15 @@ block0(v0: f64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v0, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v0, %v24, 1
+;   br %r14
 
 function %extractlane_f64x2_1(f64x2) -> f64 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1052,9 +1653,15 @@ block0(v0: f64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v0, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v0, %v24, 0
+;   br %r14
 
 function %extractlane_f64x2_mem_0(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -1063,9 +1670,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_f64x2_mem_1(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -1074,9 +1687,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_mem_little_0(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -1085,10 +1704,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f64x2_mem_little_1(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -1097,10 +1723,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f32x4_0(f32x4) -> f32 wasmtime_system_v {
 block0(v0: f32x4):
@@ -1108,9 +1741,15 @@ block0(v0: f32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v0, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v0, %v24, 3
+;   br %r14
 
 function %extractlane_f32x4_3(f32x4) -> f32 wasmtime_system_v {
 block0(v0: f32x4):
@@ -1118,9 +1757,15 @@ block0(v0: f32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v0, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v0, %v24, 0
+;   br %r14
 
 function %extractlane_f32x4_mem_0(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -1129,9 +1774,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_f32x4_mem_3(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -1140,9 +1791,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f32x4_mem_little_0(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -1151,10 +1808,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 3
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 3
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f32x4_mem_little_3(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -1163,10 +1827,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 0
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 0
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %splat_i64x2(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1174,10 +1845,17 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   vrepg %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   vrepg %v24, %v2, 0
+;   br %r14
 
 function %splat_i64x2_imm() -> i64x2 wasmtime_system_v {
 block0:
@@ -1186,9 +1864,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, 0x7b
+;   br %r14
 
 function %splat_i64x2_lane_0(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -1197,9 +1881,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 1
+;   br %r14
 
 function %splat_i64x2_lane_1(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -1208,9 +1898,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 0
+;   br %r14
 
 function %splat_i64x2_mem(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1219,9 +1915,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_i64x2_mem_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1230,11 +1932,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vrepg %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vrepg %v24, %v4, 0
+;   br %r14
 
 function %splat_i32x4(i32) -> i32x4 wasmtime_system_v {
 block0(v0: i32):
@@ -1242,10 +1952,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v2, %r2, 0
 ;   vrepf %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v2, %r2, 0
+;   vrepf %v24, %v2, 0
+;   br %r14
 
 function %splat_i32x4_imm() -> i32x4 wasmtime_system_v {
 block0:
@@ -1254,9 +1971,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, 0x7b
+;   br %r14
 
 function %splat_i32x4_lane_0(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -1265,9 +1988,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 3
+;   br %r14
 
 function %splat_i32x4_lane_3(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -1276,9 +2005,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 0
+;   br %r14
 
 function %splat_i32x4_mem(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1287,9 +2022,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_i32x4_mem_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1298,11 +2039,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   vlvgf %v4, %r4, 0
 ;   vrepf %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   vlvgf %v4, %r4, 0
+;   vrepf %v24, %v4, 0
+;   br %r14
 
 function %splat_i16x8(i16) -> i16x8 wasmtime_system_v {
 block0(v0: i16):
@@ -1310,10 +2059,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v2, %r2, 0
 ;   vreph %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v2, %r2, 0
+;   vreph %v24, %v2, 0
+;   br %r14
 
 function %splat_i16x8_imm() -> i16x8 wasmtime_system_v {
 block0:
@@ -1322,9 +2078,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, 0x7b
+;   br %r14
 
 function %splat_i16x8_lane_0(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -1333,9 +2095,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v24, %v24, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v24, %v24, 7
+;   br %r14
 
 function %splat_i16x8_lane_7(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -1344,9 +2112,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v24, %v24, 0
+;   br %r14
 
 function %splat_i16x8_mem(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -1355,9 +2129,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlreph %v24, 0(%r2)
+;   br %r14
 
 function %splat_i16x8_mem_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -1366,11 +2146,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   vlvgh %v4, %r4, 0
 ;   vreph %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   vlvgh %v4, %r4, 0
+;   vreph %v24, %v4, 0
+;   br %r14
 
 function %splat_i8x16(i8) -> i8x16 wasmtime_system_v {
 block0(v0: i8):
@@ -1378,10 +2166,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v2, %r2, 0
 ;   vrepb %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v2, %r2, 0
+;   vrepb %v24, %v2, 0
+;   br %r14
 
 function %splat_i8x16_imm() -> i8x16 wasmtime_system_v {
 block0:
@@ -1390,9 +2185,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x7b
+;   br %r14
 
 function %splat_i8x16_lane_0(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -1401,9 +2202,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v24, %v24, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v24, %v24, 0xf
+;   br %r14
 
 function %splat_i8x16_lane_15(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -1412,9 +2219,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v24, %v24, 0
+;   br %r14
 
 function %splat_i8x16_mem(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -1423,9 +2236,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_i8x16_mem_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -1434,9 +2253,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2(f64) -> f64x2 wasmtime_system_v {
 block0(v0: f64):
@@ -1444,9 +2269,15 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v0, 0
+;   br %r14
 
 function %splat_f64x2_lane_0(f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1455,9 +2286,15 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 1
+;   br %r14
 
 function %splat_f64x2_lane_1(f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1466,9 +2303,15 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 0
+;   br %r14
 
 function %splat_f64x2_mem(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1477,9 +2320,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1488,11 +2337,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vrepg %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vrepg %v24, %v4, 0
+;   br %r14
 
 function %splat_f32x4(f32) -> f32x4 wasmtime_system_v {
 block0(v0: f32):
@@ -1500,9 +2357,15 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v0, 0
+;   br %r14
 
 function %splat_f32x4_lane_0(f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4):
@@ -1511,9 +2374,15 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 3
+;   br %r14
 
 function %splat_i32x4_lane_3(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -1522,9 +2391,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 0
+;   br %r14
 
 function %splat_f32x4_mem(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1533,9 +2408,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_f32x4_mem_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1544,11 +2425,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   vlvgf %v4, %r4, 0
 ;   vrepf %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   vlvgf %v4, %r4, 0
+;   vrepf %v24, %v4, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1556,10 +2445,17 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgg %v24, %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgg %v24, %r2, 1
+;   br %r14
 
 function %scalar_to_vector_i64x2_imm() -> i64x2 wasmtime_system_v {
 block0:
@@ -1568,10 +2464,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleig %v24, 123, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleig %v24, 0x7b, 1
+;   br %r14
 
 function %scalar_to_vector_i64x2_lane_0(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -1580,10 +2483,17 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v2, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v2, %v24, 1
+;   br %r14
 
 function %scalar_to_vector_i64x2_lane_1(i64x2) -> i64x2 wasmtime_system_v {
 block0(v0: i64x2):
@@ -1592,10 +2502,17 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v2, %v24, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1604,10 +2521,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1616,11 +2540,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvg %r2, 0(%r2)
 ;   vlvgg %v24, %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvg %r2, 0(%r2)
+;   vlvgg %v24, %r2, 1
+;   br %r14
 
 function %scalar_to_vector_i32x4(i32) -> i32x4 wasmtime_system_v {
 block0(v0: i32):
@@ -1628,10 +2560,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgf %v24, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgf %v24, %r2, 3
+;   br %r14
 
 function %scalar_to_vector_i32x4_imm() -> i32x4 wasmtime_system_v {
 block0:
@@ -1640,10 +2579,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleif %v24, 123, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleif %v24, 0x7b, 3
+;   br %r14
 
 function %scalar_to_vector_i32x4_lane_0(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -1652,10 +2598,17 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 15
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xf
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i32x4_lane_3(i32x4) -> i32x4 wasmtime_system_v {
 block0(v0: i32x4):
@@ -1664,11 +2617,19 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v2, %v24, 0
 ;   vgbm %v4, 15
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v2, %v24, 0
+;   vgbm %v4, 0xf
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1677,10 +2638,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1689,11 +2657,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrv %r2, 0(%r2)
 ;   vlvgf %v24, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrv %r2, 0(%r2)
+;   vlvgf %v24, %r2, 3
+;   br %r14
 
 function %scalar_to_vector_i16x8(i16) -> i16x8 wasmtime_system_v {
 block0(v0: i16):
@@ -1701,10 +2677,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgh %v24, %r2, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgh %v24, %r2, 7
+;   br %r14
 
 function %scalar_to_vector_i16x8_imm() -> i16x8 wasmtime_system_v {
 block0:
@@ -1713,10 +2696,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleih %v24, 123, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleih %v24, 0x7b, 7
+;   br %r14
 
 function %scalar_to_vector_i16x8_lane_0(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -1725,10 +2715,17 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 3
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 3
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i16x8_lane_7(i16x8) -> i16x8 wasmtime_system_v {
 block0(v0: i16x8):
@@ -1737,11 +2734,19 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v2, %v24, 0
 ;   vgbm %v4, 3
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v2, %v24, 0
+;   vgbm %v4, 3
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -1750,10 +2755,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -1762,11 +2774,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvh %r2, 0(%r2)
 ;   vlvgh %v24, %r2, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvh %r2, 0(%r2)
+;   vlvgh %v24, %r2, 7
+;   br %r14
 
 function %scalar_to_vector_i8x16(i8) -> i8x16 wasmtime_system_v {
 block0(v0: i8):
@@ -1774,10 +2794,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgb %v24, %r2, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgb %v24, %r2, 0xf
+;   br %r14
 
 function %scalar_to_vector_i8x16_imm() -> i8x16 wasmtime_system_v {
 block0:
@@ -1786,10 +2813,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleib %v24, 123, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleib %v24, 0x7b, 0xf
+;   br %r14
 
 function %scalar_to_vector_i8x16_lane_0(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -1798,10 +2832,17 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 1
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 1
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i8x16_lane_15(i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16):
@@ -1810,11 +2851,19 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v2, %v24, 0
 ;   vgbm %v4, 1
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v2, %v24, 0
+;   vgbm %v4, 1
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -1823,10 +2872,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -1835,10 +2891,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %scalar_to_vector_f64x2(f64) -> f64x2 wasmtime_system_v {
 block0(v0: f64):
@@ -1846,10 +2909,17 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v2, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v2, %v0, 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_lane_0(f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1858,10 +2928,17 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v2, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v2, %v24, 1
+;   br %r14
 
 function %scalar_to_vector_f64x2_lane_1(f64x2) -> f64x2 wasmtime_system_v {
 block0(v0: f64x2):
@@ -1870,10 +2947,17 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v2, %v24, 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1882,10 +2966,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -1894,11 +2985,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvg %r2, 0(%r2)
 ;   vlvgg %v24, %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvg %r2, 0(%r2)
+;   vlvgg %v24, %r2, 1
+;   br %r14
 
 function %scalar_to_vector_f32x4(f32) -> f32x4 wasmtime_system_v {
 block0(v0: f32):
@@ -1906,11 +3005,19 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v2, %v0, 0
 ;   vgbm %v4, 15
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v2, %v0, 0
+;   vgbm %v4, 0xf
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_f32x4_lane_0(f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4):
@@ -1919,10 +3026,17 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 15
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xf
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_f32x4_lane_3(f32x4) -> f32x4 wasmtime_system_v {
 block0(v0: f32x4):
@@ -1931,11 +3045,19 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v2, %v24, 0
 ;   vgbm %v4, 15
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v2, %v24, 0
+;   vgbm %v4, 0xf
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1944,10 +3066,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -1956,9 +3085,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrv %r2, 0(%r2)
 ;   vlvgf %v24, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrv %r2, 0(%r2)
+;   vlvgf %v24, %r2, 3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane.clif
index 3f0a6244f1..cfbdcf3272 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-lane.clif
@@ -7,9 +7,15 @@ block0(v0: i64x2, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgg %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgg %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i64x2_1(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -17,9 +23,15 @@ block0(v0: i64x2, v1: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgg %v24, %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgg %v24, %r2, 1
+;   br %r14
 
 function %insertlane_i64x2_imm_0(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -28,9 +40,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleig %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleig %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i64x2_imm_1(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -39,9 +57,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleig %v24, 123, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleig %v24, 0x7b, 1
+;   br %r14
 
 function %insertlane_i64x2_lane_0_0(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -50,9 +74,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 1
+;   br %r14
 
 function %insertlane_i64x2_lane_0_1(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -61,9 +91,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 0
+;   br %r14
 
 function %insertlane_i64x2_lane_1_0(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -72,9 +108,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 5
+;   br %r14
 
 function %insertlane_i64x2_lane_1_1(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
@@ -83,9 +125,15 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 1
+;   br %r14
 
 function %insertlane_i64x2_mem_0(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -94,9 +142,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i64x2_mem_1(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -105,9 +159,15 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_i64x2_mem_little_0(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -116,10 +176,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -128,10 +195,17 @@ block0(v0: i64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 1
+;   br %r14
 
 function %insertlane_i32x4_0(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -139,9 +213,15 @@ block0(v0: i32x4, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i32x4_3(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -149,9 +229,15 @@ block0(v0: i32x4, v1: i32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v24, %r2, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v24, %r2, 3
+;   br %r14
 
 function %insertlane_i32x4_imm_0(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -160,9 +246,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleif %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleif %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i32x4_imm_3(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -171,9 +263,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleif %v24, 123, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleif %v24, 0x7b, 3
+;   br %r14
 
 function %insertlane_i32x4_lane_0_0(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -182,10 +280,17 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i32x4_lane_0_3(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -194,11 +299,19 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i32x4_lane_3_0(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -207,11 +320,19 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 3
 ;   vgbm %v5, 61440
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 3
+;   vgbm %v5, 0xf000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i32x4_lane_3_3(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -220,10 +341,17 @@ block0(v0: i32x4, v1: i32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 15
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -232,9 +360,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -243,9 +377,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_i32x4_mem_little_0(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -254,10 +394,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -266,10 +413,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 3
+;   br %r14
 
 function %insertlane_i16x8_0(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -277,9 +431,15 @@ block0(v0: i16x8, v1: i16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i16x8_7(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -287,9 +447,15 @@ block0(v0: i16x8, v1: i16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v24, %r2, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v24, %r2, 7
+;   br %r14
 
 function %insertlane_i16x8_imm_0(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -298,9 +464,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleih %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleih %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i16x8_imm_7(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -309,9 +481,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleih %v24, 123, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleih %v24, 0x7b, 7
+;   br %r14
 
 function %insertlane_i16x8_lane_0_0(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -320,10 +498,17 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 49152
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xc000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i16x8_lane_0_7(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -332,11 +517,19 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vreph %v3, %v25, 0
 ;   vgbm %v5, 3
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v3, %v25, 0
+;   vgbm %v5, 3
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i16x8_lane_7_0(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -345,11 +538,19 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vreph %v3, %v25, 7
 ;   vgbm %v5, 49152
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v3, %v25, 7
+;   vgbm %v5, 0xc000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i16x8_lane_7_7(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -358,10 +559,17 @@ block0(v0: i16x8, v1: i16x8):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 3
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 3
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -370,9 +578,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i16x8_mem_7(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -381,9 +595,15 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleh %v24, 0(%r2), 7
+;   br %r14
 
 function %insertlane_i16x8_mem_little_0(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -392,10 +612,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r5, 0(%r2)
 ;   vlvgh %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r5, 0(%r2)
+;   vlvgh %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 {
 block0(v0: i16x8, v1: i64):
@@ -404,10 +631,17 @@ block0(v0: i16x8, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r5, 0(%r2)
 ;   vlvgh %v24, %r5, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r5, 0(%r2)
+;   vlvgh %v24, %r5, 7
+;   br %r14
 
 function %insertlane_i8x16_0(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -415,9 +649,15 @@ block0(v0: i8x16, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v24, %r2, 0
+;   br %r14
 
 function %insertlane_i8x16_15(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -425,9 +665,15 @@ block0(v0: i8x16, v1: i8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v24, %r2, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v24, %r2, 0xf
+;   br %r14
 
 function %insertlane_i8x16_imm_0(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -436,9 +682,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleib %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleib %v24, 0x7b, 0
+;   br %r14
 
 function %insertlane_i8x16_imm_15(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -447,9 +699,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vleib %v24, 123, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleib %v24, 0x7b, 0xf
+;   br %r14
 
 function %insertlane_i8x16_lane_0_0(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -458,10 +716,17 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 32768
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0x8000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i8x16_lane_0_15(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -470,11 +735,19 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v3, %v25, 0
 ;   vgbm %v5, 1
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v3, %v25, 0
+;   vgbm %v5, 1
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i8x16_lane_15_0(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -483,11 +756,19 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v3, %v25, 15
 ;   vgbm %v5, 32768
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v3, %v25, 0xf
+;   vgbm %v5, 0x8000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_i8x16_lane_15_15(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -496,10 +777,17 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 1
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 1
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -508,9 +796,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_15(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -519,9 +813,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_i8x16_mem_little_0(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -530,9 +830,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i8x16_mem_little_15(i8x16, i64) -> i8x16 {
 block0(v0: i8x16, v1: i64):
@@ -541,9 +847,15 @@ block0(v0: i8x16, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %insertlane_f64x2_0(f64x2, f64) -> f64x2 {
 block0(v0: f64x2, v1: f64):
@@ -551,9 +863,15 @@ block0(v0: f64x2, v1: f64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v0, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v0, %v24, 1
+;   br %r14
 
 function %insertlane_f64x2_1(f64x2, f64) -> f64x2 {
 block0(v0: f64x2, v1: f64):
@@ -561,9 +879,15 @@ block0(v0: f64x2, v1: f64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v0, 0
+;   br %r14
 
 function %insertlane_f64x2_lane_0_0(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -572,9 +896,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 1
+;   br %r14
 
 function %insertlane_f64x2_lane_0_1(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -583,9 +913,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 0
+;   br %r14
 
 function %insertlane_f64x2_lane_1_0(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -594,9 +930,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v25, %v24, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v25, %v24, 5
+;   br %r14
 
 function %insertlane_f64x2_lane_1_1(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -605,9 +947,15 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v24, %v24, %v25, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v24, %v24, %v25, 1
+;   br %r14
 
 function %insertlane_f64x2_mem_0(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -616,9 +964,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_f64x2_mem_1(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -627,9 +981,15 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vleg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vleg %v24, 0(%r2), 1
+;   br %r14
 
 function %insertlane_f64x2_mem_little_0(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -638,10 +998,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 0
+;   br %r14
 
 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 {
 block0(v0: f64x2, v1: i64):
@@ -650,10 +1017,17 @@ block0(v0: f64x2, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r2)
 ;   vlvgg %v24, %r5, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r2)
+;   vlvgg %v24, %r5, 1
+;   br %r14
 
 function %insertlane_f32x4_0(f32x4, f32) -> f32x4 {
 block0(v0: f32x4, v1: f32):
@@ -661,10 +1035,17 @@ block0(v0: f32x4, v1: f32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v0, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v0, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_3(f32x4, f32) -> f32x4 {
 block0(v0: f32x4, v1: f32):
@@ -672,11 +1053,19 @@ block0(v0: f32x4, v1: f32):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v0, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v0, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_lane_0_0(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -685,10 +1074,17 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 61440
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf000
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_lane_0_3(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -697,11 +1093,19 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 0
 ;   vgbm %v5, 15
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 0
+;   vgbm %v5, 0xf
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_lane_3_0(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -710,11 +1114,19 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v3, %v25, 3
 ;   vgbm %v5, 61440
 ;   vsel %v24, %v3, %v24, %v5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v3, %v25, 3
+;   vgbm %v5, 0xf000
+;   vsel %v24, %v3, %v24, %v5
+;   br %r14
 
 function %insertlane_f32x4_lane_3_3(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -723,10 +1135,17 @@ block0(v0: f32x4, v1: f32x4):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 15
 ;   vsel %v24, %v25, %v24, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0xf
+;   vsel %v24, %v25, %v24, %v3
+;   br %r14
 
 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 {
 block0(v0: f32x4, v1: i64):
@@ -735,9 +1154,15 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %insertlane_i32x4_mem_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -746,9 +1171,15 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vlef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlef %v24, 0(%r2), 3
+;   br %r14
 
 function %insertlane_f32x4_mem_little_0(f32x4, i64) -> f32x4 {
 block0(v0: f32x4, v1: i64):
@@ -757,10 +1188,17 @@ block0(v0: f32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 0
+;   br %r14
 
 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 {
 block0(v0: i32x4, v1: i64):
@@ -769,10 +1207,17 @@ block0(v0: i32x4, v1: i64):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   lrv %r5, 0(%r2)
 ;   vlvgf %v24, %r5, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r5, 0(%r2)
+;   vlvgf %v24, %r5, 3
+;   br %r14
 
 function %extractlane_i64x2_0(i64x2) -> i64 {
 block0(v0: i64x2):
@@ -780,9 +1225,15 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i64x2_1(i64x2) -> i64 {
 block0(v0: i64x2):
@@ -790,9 +1241,15 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r2, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r2, %v24, 1
+;   br %r14
 
 function %extractlane_i64x2_mem_0(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -801,9 +1258,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i64x2_mem_1(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -812,9 +1275,15 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_i64x2_mem_little_0(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -823,10 +1292,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i64x2_mem_little_1(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -835,10 +1311,17 @@ block0(v0: i64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i32x4_0(i32x4) -> i32 {
 block0(v0: i32x4):
@@ -846,9 +1329,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i32x4_3(i32x4) -> i32 {
 block0(v0: i32x4):
@@ -856,9 +1345,15 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r2, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r2, %v24, 3
+;   br %r14
 
 function %extractlane_i32x4_mem_0(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -867,9 +1362,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i32x4_mem_3(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -878,9 +1379,15 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_i32x4_mem_little_0(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -889,10 +1396,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 0
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 0
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i32x4_mem_little_3(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -901,10 +1415,17 @@ block0(v0: i32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 3
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 3
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i16x8_0(i16x8) -> i16 {
 block0(v0: i16x8):
@@ -912,9 +1433,15 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i16x8_7(i16x8) -> i16 {
 block0(v0: i16x8):
@@ -922,9 +1449,15 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r2, %v24, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r2, %v24, 7
+;   br %r14
 
 function %extractlane_i16x8_mem_0(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -933,9 +1466,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i16x8_mem_7(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -944,9 +1483,15 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteh %v24, 0(%r2), 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteh %v24, 0(%r2), 7
+;   br %r14
 
 function %extractlane_i16x8_mem_little_0(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -955,10 +1500,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r5, %v24, 0
 ;   strvh %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r5, %v24, 0
+;   strvh %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i16x8_mem_little_7(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -967,10 +1519,17 @@ block0(v0: i16x8, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvh %r5, %v24, 7
 ;   strvh %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvh %r5, %v24, 7
+;   strvh %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_i8x16_0(i8x16) -> i8 {
 block0(v0: i8x16):
@@ -978,9 +1537,15 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvb %r2, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvb %r2, %v24, 0
+;   br %r14
 
 function %extractlane_i8x16_15(i8x16) -> i8 {
 block0(v0: i8x16):
@@ -988,9 +1553,15 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlgvb %r2, %v24, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvb %r2, %v24, 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_0(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -999,9 +1570,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_15(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -1010,9 +1587,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_i8x16_mem_little_0(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -1021,9 +1604,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_i8x16_mem_little_15(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -1032,9 +1621,15 @@ block0(v0: i8x16, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteb %v24, 0(%r2), 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteb %v24, 0(%r2), 0xf
+;   br %r14
 
 function %extractlane_f64x2_0(f64x2) -> f64 {
 block0(v0: f64x2):
@@ -1042,9 +1637,15 @@ block0(v0: f64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v0, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v0, %v24, 0
+;   br %r14
 
 function %extractlane_f64x2_1(f64x2) -> f64 {
 block0(v0: f64x2):
@@ -1052,9 +1653,15 @@ block0(v0: f64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v0, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v0, %v24, 1
+;   br %r14
 
 function %extractlane_f64x2_mem_0(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -1063,9 +1670,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f64x2_mem_1(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -1074,9 +1687,15 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vsteg %v24, 0(%r2), 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vsteg %v24, 0(%r2), 1
+;   br %r14
 
 function %extractlane_f64x2_mem_little_0(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -1085,10 +1704,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 0
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f64x2_mem_little_1(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -1097,10 +1723,17 @@ block0(v0: f64x2, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   strvg %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   strvg %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f32x4_0(f32x4) -> f32 {
 block0(v0: f32x4):
@@ -1108,9 +1741,15 @@ block0(v0: f32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v0, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v0, %v24, 0
+;   br %r14
 
 function %extractlane_f32x4_3(f32x4) -> f32 {
 block0(v0: f32x4):
@@ -1118,9 +1757,15 @@ block0(v0: f32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v0, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v0, %v24, 3
+;   br %r14
 
 function %extractlane_f32x4_mem_0(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -1129,9 +1774,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 0
+;   br %r14
 
 function %extractlane_f32x4_mem_3(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -1140,9 +1791,15 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vstef %v24, 0(%r2), 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vstef %v24, 0(%r2), 3
+;   br %r14
 
 function %extractlane_f32x4_mem_little_0(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -1151,10 +1808,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 0
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 0
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %extractlane_f32x4_mem_little_3(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -1163,10 +1827,17 @@ block0(v0: f32x4, v1: i64):
     return
 }
 
+; VCode:
 ; block0:
 ;   vlgvf %r5, %v24, 3
 ;   strv %r5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvf %r5, %v24, 3
+;   strv %r5, 0(%r2)
+;   br %r14
 
 function %splat_i64x2(i64) -> i64x2 {
 block0(v0: i64):
@@ -1174,10 +1845,17 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   ldgr %f2, %r2
 ;   vrepg %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ldgr %f2, %r2
+;   vrepg %v24, %v2, 0
+;   br %r14
 
 function %splat_i64x2_imm() -> i64x2 {
 block0:
@@ -1186,9 +1864,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepig %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepig %v24, 0x7b
+;   br %r14
 
 function %splat_i64x2_lane_0(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -1197,9 +1881,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 0
+;   br %r14
 
 function %splat_i64x2_lane_1(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -1208,9 +1898,15 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 1
+;   br %r14
 
 function %splat_i64x2_mem(i64) -> i64x2 {
 block0(v0: i64):
@@ -1219,9 +1915,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_i64x2_mem_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -1230,11 +1932,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vrepg %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vrepg %v24, %v4, 0
+;   br %r14
 
 function %splat_i32x4(i32) -> i32x4 {
 block0(v0: i32):
@@ -1242,10 +1952,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgf %v2, %r2, 0
 ;   vrepf %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgf %v2, %r2, 0
+;   vrepf %v24, %v2, 0
+;   br %r14
 
 function %splat_i32x4_imm() -> i32x4 {
 block0:
@@ -1254,9 +1971,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepif %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepif %v24, 0x7b
+;   br %r14
 
 function %splat_i32x4_lane_0(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -1265,9 +1988,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 0
+;   br %r14
 
 function %splat_i32x4_lane_3(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -1276,9 +2005,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 3
+;   br %r14
 
 function %splat_i32x4_mem(i64) -> i32x4 {
 block0(v0: i64):
@@ -1287,9 +2022,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_i32x4_mem_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -1298,11 +2039,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   vlvgf %v4, %r4, 0
 ;   vrepf %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   vlvgf %v4, %r4, 0
+;   vrepf %v24, %v4, 0
+;   br %r14
 
 function %splat_i16x8(i16) -> i16x8 {
 block0(v0: i16):
@@ -1310,10 +2059,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgh %v2, %r2, 0
 ;   vreph %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgh %v2, %r2, 0
+;   vreph %v24, %v2, 0
+;   br %r14
 
 function %splat_i16x8_imm() -> i16x8 {
 block0:
@@ -1322,9 +2078,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepih %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepih %v24, 0x7b
+;   br %r14
 
 function %splat_i16x8_lane_0(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -1333,9 +2095,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v24, %v24, 0
+;   br %r14
 
 function %splat_i16x8_lane_7(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -1344,9 +2112,15 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v24, %v24, 7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v24, %v24, 7
+;   br %r14
 
 function %splat_i16x8_mem(i64) -> i16x8 {
 block0(v0: i64):
@@ -1355,9 +2129,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlreph %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlreph %v24, 0(%r2)
+;   br %r14
 
 function %splat_i16x8_mem_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -1366,11 +2146,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvh %r4, 0(%r2)
 ;   vlvgh %v4, %r4, 0
 ;   vreph %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvh %r4, 0(%r2)
+;   vlvgh %v4, %r4, 0
+;   vreph %v24, %v4, 0
+;   br %r14
 
 function %splat_i8x16(i8) -> i8x16 {
 block0(v0: i8):
@@ -1378,10 +2166,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vlvgb %v2, %r2, 0
 ;   vrepb %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlvgb %v2, %r2, 0
+;   vrepb %v24, %v2, 0
+;   br %r14
 
 function %splat_i8x16_imm() -> i8x16 {
 block0:
@@ -1390,9 +2185,15 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v24, 123
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v24, 0x7b
+;   br %r14
 
 function %splat_i8x16_lane_0(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -1401,9 +2202,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v24, %v24, 0
+;   br %r14
 
 function %splat_i8x16_lane_15(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -1412,9 +2219,15 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v24, %v24, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v24, %v24, 0xf
+;   br %r14
 
 function %splat_i8x16_mem(i64) -> i8x16 {
 block0(v0: i64):
@@ -1423,9 +2236,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_i8x16_mem_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -1434,9 +2253,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepb %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepb %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2(f64) -> f64x2 {
 block0(v0: f64):
@@ -1444,9 +2269,15 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v0, 0
+;   br %r14
 
 function %splat_f64x2_lane_0(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -1455,9 +2286,15 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 0
+;   br %r14
 
 function %splat_f64x2_lane_1(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -1466,9 +2303,15 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepg %v24, %v24, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepg %v24, %v24, 1
+;   br %r14
 
 function %splat_f64x2_mem(i64) -> f64x2 {
 block0(v0: i64):
@@ -1477,9 +2320,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepg %v24, 0(%r2)
+;   br %r14
 
 function %splat_f64x2_mem_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -1488,11 +2337,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vrepg %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vrepg %v24, %v4, 0
+;   br %r14
 
 function %splat_f32x4(f32) -> f32x4 {
 block0(v0: f32):
@@ -1500,9 +2357,15 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v0, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v0, 0
+;   br %r14
 
 function %splat_f32x4_lane_0(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -1511,9 +2374,15 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 0
+;   br %r14
 
 function %splat_i32x4_lane_3(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -1522,9 +2391,15 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v24, %v24, 3
+;   br %r14
 
 function %splat_f32x4_mem(i64) -> f32x4 {
 block0(v0: i64):
@@ -1533,9 +2408,15 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vlrepf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlrepf %v24, 0(%r2)
+;   br %r14
 
 function %splat_f32x4_mem_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -1544,11 +2425,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   lrv %r4, 0(%r2)
 ;   vlvgf %v4, %r4, 0
 ;   vrepf %v24, %v4, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrv %r4, 0(%r2)
+;   vlvgf %v4, %r4, 0
+;   vrepf %v24, %v4, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2(i64) -> i64x2 {
 block0(v0: i64):
@@ -1556,10 +2445,17 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgg %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgg %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_imm() -> i64x2 {
 block0:
@@ -1568,10 +2464,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleig %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleig %v24, 0x7b, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_lane_0(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -1580,10 +2483,17 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v24, %v2, 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_lane_1(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -1592,10 +2502,17 @@ block0(v0: i64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v24, %v2, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v24, %v2, 4
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 {
 block0(v0: i64):
@@ -1604,10 +2521,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i64x2_mem_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -1616,11 +2540,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvg %r2, 0(%r2)
 ;   vlvgg %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvg %r2, 0(%r2)
+;   vlvgg %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i32x4(i32) -> i32x4 {
 block0(v0: i32):
@@ -1628,10 +2560,17 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgf %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgf %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i32x4_imm() -> i32x4 {
 block0:
@@ -1640,10 +2579,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleif %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleif %v24, 0x7b, 0
+;   br %r14
 
 function %scalar_to_vector_i32x4_lane_0(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -1652,10 +2598,17 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 61440
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xf000
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i32x4_lane_3(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -1664,11 +2617,19 @@ block0(v0: i32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v2, %v24, 3
 ;   vgbm %v4, 61440
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v2, %v24, 3
+;   vgbm %v4, 0xf000
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 {
 block0(v0: i64):
@@ -1677,10 +2638,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i32x4_mem_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -1689,11 +2657,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrv %r2, 0(%r2)
 ;   vlvgf %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrv %r2, 0(%r2)
+;   vlvgf %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i16x8(i16) -> i16x8 {
 block0(v0: i16):
@@ -1701,10 +2677,17 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgh %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgh %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i16x8_imm() -> i16x8 {
 block0:
@@ -1713,10 +2696,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleih %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleih %v24, 0x7b, 0
+;   br %r14
 
 function %scalar_to_vector_i16x8_lane_0(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -1725,10 +2715,17 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 49152
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xc000
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i16x8_lane_7(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -1737,11 +2734,19 @@ block0(v0: i16x8):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vreph %v2, %v24, 7
 ;   vgbm %v4, 49152
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vreph %v2, %v24, 7
+;   vgbm %v4, 0xc000
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 {
 block0(v0: i64):
@@ -1750,10 +2755,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleh %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleh %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i16x8_mem_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -1762,11 +2774,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvh %r2, 0(%r2)
 ;   vlvgh %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvh %r2, 0(%r2)
+;   vlvgh %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i8x16(i8) -> i8x16 {
 block0(v0: i8):
@@ -1774,10 +2794,17 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlvgb %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlvgb %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_i8x16_imm() -> i8x16 {
 block0:
@@ -1786,10 +2813,17 @@ block0:
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleib %v24, 123, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleib %v24, 0x7b, 0
+;   br %r14
 
 function %scalar_to_vector_i8x16_lane_0(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -1798,10 +2832,17 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 32768
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0x8000
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_i8x16_lane_15(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -1810,11 +2851,19 @@ block0(v0: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepb %v2, %v24, 15
 ;   vgbm %v4, 32768
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepb %v2, %v24, 0xf
+;   vgbm %v4, 0x8000
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 {
 block0(v0: i64):
@@ -1823,10 +2872,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_i8x16_mem_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -1835,10 +2891,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleb %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleb %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f64x2(f64) -> f64x2 {
 block0(v0: f64):
@@ -1846,10 +2909,17 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v0, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v0, %v2, 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_lane_0(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -1858,10 +2928,17 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v24, %v2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v24, %v2, 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_lane_1(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -1870,10 +2947,17 @@ block0(v0: f64x2):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vpdi %v24, %v24, %v2, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vpdi %v24, %v24, %v2, 4
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 {
 block0(v0: i64):
@@ -1882,10 +2966,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vleg %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vleg %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f64x2_mem_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -1894,11 +2985,19 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrvg %r2, 0(%r2)
 ;   vlvgg %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrvg %r2, 0(%r2)
+;   vlvgg %v24, %r2, 0
+;   br %r14
 
 function %scalar_to_vector_f32x4(f32) -> f32x4 {
 block0(v0: f32):
@@ -1906,10 +3005,17 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 61440
 ;   vn %v24, %v0, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xf000
+;   vn %v24, %v0, %v2
+;   br %r14
 
 function %scalar_to_vector_f32x4_lane_0(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -1918,10 +3024,17 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 61440
 ;   vn %v24, %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v2, 0xf000
+;   vn %v24, %v24, %v2
+;   br %r14
 
 function %scalar_to_vector_f32x4_lane_3(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -1930,11 +3043,19 @@ block0(v0: f32x4):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepf %v2, %v24, 3
 ;   vgbm %v4, 61440
 ;   vn %v24, %v2, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepf %v2, %v24, 3
+;   vgbm %v4, 0xf000
+;   vn %v24, %v2, %v4
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 {
 block0(v0: i64):
@@ -1943,10 +3064,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   vlef %v24, 0(%r2), 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   vlef %v24, 0(%r2), 0
+;   br %r14
 
 function %scalar_to_vector_f32x4_mem_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -1955,9 +3083,17 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v24, 0
 ;   lrv %r2, 0(%r2)
 ;   vlvgf %v24, %r2, 0
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v24
+;   lrv %r2, 0(%r2)
+;   vlvgf %v24, %r2, 0
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-logical.clif b/cranelift/filetests/filetests/isa/s390x/vec-logical.clif
index 04aa8cfd85..9eea149644 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-logical.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-logical.clif
@@ -7,12 +7,21 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqgs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqgs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_i32x4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -20,12 +29,21 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqfs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqfs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_i16x8(i16x8) -> i8 {
 block0(v0: i16x8):
@@ -33,12 +51,21 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqhs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqhs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_i8x16(i8x16) -> i8 {
 block0(v0: i8x16):
@@ -46,12 +73,21 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqbs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqbs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vall_true_i64x2(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -59,12 +95,21 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqgs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqgs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_i32x4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -72,12 +117,21 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqfs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqfs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_i16x8(i16x8) -> i8 {
 block0(v0: i16x8):
@@ -85,12 +139,21 @@ block0(v0: i16x8):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqhs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqhs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_i8x16(i8x16) -> i8 {
 block0(v0: i8x16):
@@ -98,12 +161,21 @@ block0(v0: i8x16):
     return v1
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v2, 0
 ;   vceqbs %v4, %v24, %v2
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v2
+;   vceqbs %v4, %v24, %v2
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vany_true_icmp_eq_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -112,11 +184,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vceqgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_icmp_ne_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -125,11 +205,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vceqgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_icmp_sgt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -138,11 +226,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_icmp_sle_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -151,11 +247,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_icmp_slt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -164,11 +268,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_icmp_sge_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -177,11 +289,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_icmp_ugt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -190,11 +310,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_icmp_ule_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -203,11 +331,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_icmp_ult_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -216,11 +352,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_icmp_uge_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -229,11 +373,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_eq_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -242,11 +394,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfcedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_ne_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -255,11 +415,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfcedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_gt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -268,11 +436,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_ule_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -281,11 +457,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_ge_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -294,11 +478,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_ult_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -307,11 +499,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_lt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -320,11 +520,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_uge_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -333,11 +541,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_le_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -346,11 +562,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochino %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochino %r2, 1
+;   br %r14
 
 function %vany_true_fcmp_ugt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -359,11 +583,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochine %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochine %r2, 1
+;   br %r14
 
 function %vall_true_icmp_eq_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -372,11 +604,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vceqgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_icmp_ne_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -385,11 +625,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vceqgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vceqgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_icmp_sgt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -398,11 +646,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_icmp_sle_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -411,11 +667,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_icmp_slt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -424,11 +688,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_icmp_sge_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -437,11 +709,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_icmp_ugt_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -450,11 +730,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_icmp_ule_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -463,11 +751,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_icmp_ult_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -476,11 +772,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_icmp_uge_i64x2(i64x2, i64x2) -> i8 {
 block0(v0: i64x2, v1: i64x2):
@@ -489,11 +793,19 @@ block0(v0: i64x2, v1: i64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vchlgs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vchlgs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_eq_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -502,11 +814,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfcedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_ne_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -515,11 +835,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfcedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfcedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_gt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -528,11 +856,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_ule_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -541,11 +877,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_ge_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -554,11 +898,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_ult_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -567,11 +919,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v24, %v25
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v24, %v25
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_lt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -580,11 +940,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_uge_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -593,11 +961,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchdbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchdbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_le_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -606,11 +982,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochie %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochie %r2, 1
+;   br %r14
 
 function %vall_true_fcmp_ugt_f64x2(f64x2, f64x2) -> i8 {
 block0(v0: f64x2, v1: f64x2):
@@ -619,11 +1003,19 @@ block0(v0: f64x2, v1: f64x2):
     return v3
 }
 
+; VCode:
 ; block0:
 ;   vfchedbs %v3, %v25, %v24
 ;   lhi %r2, 0
 ;   lochio %r2, 1
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vfchedbs %v3, %v25, %v24
+;   lhi %r2, 0
+;   lochio %r2, 1
+;   br %r14
 
 function %vhigh_bits_be(i64x2) -> i64 {
 block0(v0: i64x2):
@@ -631,11 +1023,29 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080808080808080804000 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   sth %r0, 0x720(%r14)
+;   lpr %r0, %r0
+;   .byte 0x00, 0x06
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_be(i32x4) -> i64 {
 block0(v0: i32x4):
@@ -643,11 +1053,27 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080808080808060402000 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   std %f4, 0(%r2)
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_be(i16x8) -> i64 {
 block0(v0: i16x8):
@@ -655,11 +1081,27 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080807060504030201000 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   ste %f6, 0x40(%r5)
+;   lper %f2, %f0
+;   lpr %r0, %r0
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_be(i8x16) -> i64 {
 block0(v0: i8x16):
@@ -667,11 +1109,26 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x78706860585048403830282018100800 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   le %f7, 0x860(%r6)
+;   l %r5, 0x840(%r4)
+;   ler %f3, %f0
+;   ldr %f2, %f0
+;   lr %r1, %r0
+;   .byte 0x08, 0x00
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_le(i64x2) -> i64 wasmtime_system_v {
 block0(v0: i64x2):
@@ -679,11 +1136,28 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080808080808080800040 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x00, 0x40
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_le(i32x4) -> i64 wasmtime_system_v {
 block0(v0: i32x4):
@@ -691,11 +1165,29 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080808080808000204060 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x00, 0x20
+;   sth %r6, 0x720(%r14)
+;   lpr %r0, %r0
+;   .byte 0x00, 0x06
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_le(i16x8) -> i64 wasmtime_system_v {
 block0(v0: i16x8):
@@ -703,11 +1195,27 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x80808080808080800010203040506070 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x00, 0x10
+;   lpdr %f3, %f0
+;   sth %r5, 0x70(%r6)
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
 function %vhigh_bits_le(i8x16) -> i64 wasmtime_system_v {
 block0(v0: i8x16):
@@ -715,9 +1223,24 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x00081018202830384048505860687078 ; vl %v2, 0(%r1)
 ;   vbperm %v4, %v24, %v2
 ;   lgdr %r2, %f4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x00, 0x08
+;   lpr %r1, %r8
+;   lpdr %f2, %f8
+;   lper %f3, %f8
+;   sth %r4, 0x58(%r8, %r5)
+;   std %f6, 0x78(%r8, %r7)
+;   vl %v2, 0(%r1)
+;   vbperm %v4, %v24, %v2
+;   lgdr %r2, %f4
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif
index 5faacca81b..61caaaa1fc 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif
@@ -7,6 +7,7 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vrepib %v5, 239
@@ -14,6 +15,15 @@ block0(v0: i8x16, v1: i8x16):
 ;   vmxlb %v17, %v5, %v7
 ;   vperm %v24, %v3, %v24, %v17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vrepib %v5, 0xef
+;   vno %v7, %v25, %v25
+;   vmxlb %v17, %v5, %v7
+;   vperm %v24, %v3, %v24, %v17
+;   br %r14
 
 function %shuffle_0(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -21,10 +31,17 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vrepib %v3, 15
 ;   vperm %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vrepib %v3, 0xf
+;   vperm %v24, %v24, %v25, %v3
+;   br %r14
 
 function %shuffle_1(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -32,10 +49,26 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x0a1e000d0b1702180403090b15100f0c ; vl %v3, 0(%r1)
 ;   vperm %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   svc 0x1e
+;   .byte 0x00, 0x0d
+;   bsm %r1, %r7
+;   .byte 0x02, 0x18
+;   .byte 0x04, 0x03
+;   .byte 0x09, 0x0b
+;   clr %r1, %r0
+;   clcl %r0, %r12
+;   vl %v3, 0(%r1)
+;   vperm %v24, %v24, %v25, %v3
+;   br %r14
 
 function %shuffle_2(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -43,12 +76,30 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 1
 ;   bras %r1, 20 ; data.u128 0x8080808080808080808080808080800f ; vl %v5, 0(%r1)
 ;   vperm %v7, %v24, %v25, %v5
 ;   vn %v24, %v3, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 1
+;   bras %r1, 0x1a
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x0f
+;   vl %v5, 0(%r1)
+;   vperm %v7, %v24, %v25, %v5
+;   vn %v24, %v3, %v7
+;   br %r14
 
 function %shuffle_vmrhg_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -56,9 +107,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhf_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -66,9 +123,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhh_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -76,9 +139,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhb_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -86,9 +155,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhg_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -96,9 +171,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhf_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -106,9 +187,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhh_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -116,9 +203,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhb_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -126,9 +219,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhg_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -136,9 +235,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhf_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -146,9 +251,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhh_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -156,9 +267,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhb_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -166,9 +283,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhg_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -176,9 +299,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhf_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -186,9 +315,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhh_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -196,9 +331,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhb_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -206,9 +347,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlg_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -216,9 +363,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlf_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -226,9 +379,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlh_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -236,9 +395,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlb_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -246,9 +411,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlg_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -256,9 +427,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlf_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -266,9 +443,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlh_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -276,9 +459,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlb_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -286,9 +475,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlg_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -296,9 +491,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlf_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -306,9 +507,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlh_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -316,9 +523,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlb_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -326,9 +539,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlg_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -336,9 +555,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlf_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -346,9 +571,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlh_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -356,9 +587,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlb_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -366,9 +603,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v25, %v25
+;   br %r14
 
 ;; Special patterns that can be implemented via PACK.
 function %shuffle_vpkg_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
@@ -377,9 +620,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkf_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -387,9 +636,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkh_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -397,9 +652,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkg_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -407,9 +668,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkf_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -417,9 +684,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkh_yx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -427,9 +700,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkg_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -437,9 +716,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkf_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -447,9 +732,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkh_xx(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -457,9 +748,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkg_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -467,9 +764,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vpkf_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -477,9 +780,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vpkh_yy(i8x16, i8x16) -> i8x16 wasmtime_system_v {
 block0(v0: i8x16, v1: i8x16):
@@ -487,7 +796,13 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v25, %v25
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-permute.clif b/cranelift/filetests/filetests/isa/s390x/vec-permute.clif
index 96af760111..2fa220a68f 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-permute.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-permute.clif
@@ -7,12 +7,21 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vrepib %v5, 16
 ;   vmnlb %v7, %v5, %v25
 ;   vperm %v24, %v24, %v3, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vrepib %v5, 0x10
+;   vmnlb %v7, %v5, %v25
+;   vperm %v24, %v24, %v3, %v7
+;   br %r14
 
 function %shuffle_0(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -20,10 +29,17 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 0
 ;   vperm %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vzero %v3
+;   vperm %v24, %v24, %v25, %v3
+;   br %r14
 
 function %shuffle_1(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -31,10 +47,26 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   bras %r1, 20 ; data.u128 0x03001f1a04060c0b170d1804020f1105 ; vl %v3, 0(%r1)
 ;   vperm %v24, %v24, %v25, %v3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   bras %r1, 0x14
+;   .byte 0x03, 0x00
+;   slr %r1, %r10
+;   .byte 0x04, 0x06
+;   bassm %r0, %r11
+;   xr %r0, %r13
+;   lr %r0, %r4
+;   .byte 0x02, 0x0f
+;   lnr %r0, %r5
+;   vl %v3, 0(%r1)
+;   vperm %v24, %v24, %v25, %v3
+;   br %r14
 
 function %shuffle_2(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -42,12 +74,30 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vgbm %v3, 32768
 ;   bras %r1, 20 ; data.u128 0x00808080808080808080808080808080 ; vl %v5, 0(%r1)
 ;   vperm %v7, %v24, %v25, %v5
 ;   vn %v24, %v3, %v7
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vgbm %v3, 0x8000
+;   bras %r1, 0x1a
+;   .byte 0x00, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   .byte 0x80, 0x80
+;   vl %v5, 0(%r1)
+;   vperm %v7, %v24, %v25, %v5
+;   vn %v24, %v3, %v7
+;   br %r14
 
 function %shuffle_vmrhg_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -55,9 +105,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhf_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -65,9 +121,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhh_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -75,9 +137,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhb_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -85,9 +153,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrhg_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -95,9 +169,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhf_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -105,9 +185,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhh_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -115,9 +201,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhb_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -125,9 +217,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrhg_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -135,9 +233,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhf_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -145,9 +249,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhh_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -155,9 +265,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhb_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -165,9 +281,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrhg_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -175,9 +297,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhf_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -185,9 +313,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhh_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -195,9 +329,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhh %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrhb_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -205,9 +345,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrhb %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrhb %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlg_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -215,9 +361,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlf_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -225,9 +377,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlh_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -235,9 +393,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlb_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -245,9 +409,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vmrlg_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -255,9 +425,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlf_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -265,9 +441,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlh_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -275,9 +457,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlb_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -285,9 +473,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vmrlg_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -295,9 +489,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlf_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -305,9 +505,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlh_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -315,9 +521,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlb_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -325,9 +537,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vmrlg_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -335,9 +553,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlf_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -345,9 +569,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlh_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -355,9 +585,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlh %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vmrlb_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -365,9 +601,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vmrlb %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vmrlb %v24, %v25, %v25
+;   br %r14
 
 ;; Special patterns that can be implemented via PACK.
 function %shuffle_vpkg_xy(i8x16, i8x16) -> i8x16 {
@@ -376,9 +618,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkf_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -386,9 +634,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkh_xy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -396,9 +650,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v24, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v24, %v25
+;   br %r14
 
 function %shuffle_vpkg_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -406,9 +666,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkf_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -416,9 +682,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkh_yx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -426,9 +698,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v25, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v25, %v24
+;   br %r14
 
 function %shuffle_vpkg_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -436,9 +714,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkf_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -446,9 +730,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkh_xx(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -456,9 +746,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v24, %v24
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v24, %v24
+;   br %r14
 
 function %shuffle_vpkg_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -466,9 +762,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkg %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkg %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vpkf_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -476,9 +778,15 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkf %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkf %v24, %v25, %v25
+;   br %r14
 
 function %shuffle_vpkh_yy(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -486,7 +794,13 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ; block0:
 ;   vpkh %v24, %v25, %v25
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpkh %v24, %v25, %v25
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif b/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif
index 74445bbac4..5628ed5bf8 100644
--- a/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif
@@ -7,10 +7,17 @@ block0(v0: i64x2, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r2
 ;   verllg %v24, %v24, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r2
+;   verllg %v24, %v24, 0(%r5)
+;   br %r14
 
 function %rotr_i64x4_imm(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -19,9 +26,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllg %v24, %v24, 47
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllg %v24, %v24, 0x2f
+;   br %r14
 
 function %rotr_i32x4_reg(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -29,10 +42,17 @@ block0(v0: i32x4, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r2
 ;   verllf %v24, %v24, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r2
+;   verllf %v24, %v24, 0(%r5)
+;   br %r14
 
 function %rotr_i32x4_imm(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -41,9 +61,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllf %v24, %v24, 15
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllf %v24, %v24, 0xf
+;   br %r14
 
 function %rotr_i16x8_reg(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -51,10 +77,17 @@ block0(v0: i16x8, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r2
 ;   verllh %v24, %v24, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r2
+;   verllh %v24, %v24, 0(%r5)
+;   br %r14
 
 function %rotr_i16x8_imm(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -63,9 +96,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllh %v24, %v24, 6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllh %v24, %v24, 6
+;   br %r14
 
 function %rotr_i8x16_reg(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -73,10 +112,17 @@ block0(v0: i8x16, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   lcr %r5, %r2
 ;   verllb %v24, %v24, 0(%r5)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lcr %r5, %r2
+;   verllb %v24, %v24, 0(%r5)
+;   br %r14
 
 function %rotr_i8x16_imm(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -85,9 +131,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllb %v24, %v24, 5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllb %v24, %v24, 5
+;   br %r14
 
 function %rotl_i64x2_reg(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -95,9 +147,15 @@ block0(v0: i64x2, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllg %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllg %v24, %v24, 0(%r2)
+;   br %r14
 
 function %rotl_i64x2_imm(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -106,9 +164,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllg %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllg %v24, %v24, 0x11
+;   br %r14
 
 function %rotl_i32x4_reg(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -116,9 +180,15 @@ block0(v0: i32x4, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllf %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllf %v24, %v24, 0(%r2)
+;   br %r14
 
 function %rotl_i32x4_imm(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -127,9 +197,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllf %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllf %v24, %v24, 0x11
+;   br %r14
 
 function %rotl_i16x8_reg(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -137,9 +213,15 @@ block0(v0: i16x8, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllh %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllh %v24, %v24, 0(%r2)
+;   br %r14
 
 function %rotl_i16x8_imm(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -148,9 +230,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllh %v24, %v24, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllh %v24, %v24, 0xa
+;   br %r14
 
 function %rotl_i8x16_reg(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -158,9 +246,15 @@ block0(v0: i8x16, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllb %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllb %v24, %v24, 0(%r2)
+;   br %r14
 
 function %rotr_i8x16_imm(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -169,9 +263,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   verllb %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   verllb %v24, %v24, 3
+;   br %r14
 
 function %ushr_i64x2_reg(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -179,9 +279,15 @@ block0(v0: i64x2, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlg %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlg %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ushr_i64x2_imm(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -190,9 +296,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlg %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlg %v24, %v24, 0x11
+;   br %r14
 
 function %ushr_i32x4_reg(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -200,9 +312,15 @@ block0(v0: i32x4, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlf %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlf %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ushr_i32x4_imm(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -211,9 +329,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlf %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlf %v24, %v24, 0x11
+;   br %r14
 
 function %ushr_i16x8_reg(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -221,9 +345,15 @@ block0(v0: i16x8, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlh %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlh %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ushr_i16x8_imm(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -232,9 +362,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlh %v24, %v24, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlh %v24, %v24, 0xa
+;   br %r14
 
 function %ushr_i8x16_reg(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -242,9 +378,15 @@ block0(v0: i8x16, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlb %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlb %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ushr_i8x16_imm(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -253,9 +395,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrlb %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrlb %v24, %v24, 3
+;   br %r14
 
 function %ishl_i64x2_reg(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -263,9 +411,15 @@ block0(v0: i64x2, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslg %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslg %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ishl_i64x2_imm(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -274,9 +428,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslg %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslg %v24, %v24, 0x11
+;   br %r14
 
 function %ishl_i32x4_reg(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -284,9 +444,15 @@ block0(v0: i32x4, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslf %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslf %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ishl_i32x4_imm(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -295,9 +461,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslf %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslf %v24, %v24, 0x11
+;   br %r14
 
 function %ishl_i16x8_reg(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -305,9 +477,15 @@ block0(v0: i16x8, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslh %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslh %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ishl_i16x8_imm(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -316,9 +494,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslh %v24, %v24, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslh %v24, %v24, 0xa
+;   br %r14
 
 function %ishl_i8x16_reg(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -326,9 +510,15 @@ block0(v0: i8x16, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslb %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslb %v24, %v24, 0(%r2)
+;   br %r14
 
 function %ishl_i8x16_imm(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -337,9 +527,15 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   veslb %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   veslb %v24, %v24, 3
+;   br %r14
 
 function %sshr_i64x2_reg(i64x2, i64) -> i64x2 {
 block0(v0: i64x2, v1: i64):
@@ -347,9 +543,15 @@ block0(v0: i64x2, v1: i64):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrag %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrag %v24, %v24, 0(%r2)
+;   br %r14
 
 function %sshr_i64x2_imm(i64x2) -> i64x2 {
 block0(v0: i64x2):
@@ -358,9 +560,15 @@ block0(v0: i64x2):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrag %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrag %v24, %v24, 0x11
+;   br %r14
 
 function %sshr_i32x4_reg(i32x4, i32) -> i32x4 {
 block0(v0: i32x4, v1: i32):
@@ -368,9 +576,15 @@ block0(v0: i32x4, v1: i32):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesraf %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesraf %v24, %v24, 0(%r2)
+;   br %r14
 
 function %sshr_i32x4_imm(i32x4) -> i32x4 {
 block0(v0: i32x4):
@@ -379,9 +593,15 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesraf %v24, %v24, 17
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesraf %v24, %v24, 0x11
+;   br %r14
 
 function %sshr_i16x8_reg(i16x8, i16) -> i16x8 {
 block0(v0: i16x8, v1: i16):
@@ -389,9 +609,15 @@ block0(v0: i16x8, v1: i16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrah %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrah %v24, %v24, 0(%r2)
+;   br %r14
 
 function %sshr_i16x8_imm(i16x8) -> i16x8 {
 block0(v0: i16x8):
@@ -400,9 +626,15 @@ block0(v0: i16x8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrah %v24, %v24, 10
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrah %v24, %v24, 0xa
+;   br %r14
 
 function %sshr_i8x16_reg(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):
@@ -410,9 +642,15 @@ block0(v0: i8x16, v1: i8):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrab %v24, %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrab %v24, %v24, 0(%r2)
+;   br %r14
 
 function %sshr_i8x16_imm(i8x16) -> i8x16 {
 block0(v0: i8x16):
@@ -421,7 +659,13 @@ block0(v0: i8x16):
   return v2
 }
 
+; VCode:
 ; block0:
 ;   vesrab %v24, %v24, 3
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vesrab %v24, %v24, 3
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif
index ef01336558..16fa58ef5b 100644
--- a/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif
@@ -7,10 +7,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -18,10 +25,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhh %v24, %v2
+;   br %r14
 
 function %uload32x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -29,10 +43,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhf %v24, %v2
+;   br %r14
 
 function %sload8x8_big(i64) -> i16x8 {
 block0(v0: i64):
@@ -40,10 +61,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -51,10 +79,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphh %v24, %v2
+;   br %r14
 
 function %sload32x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -62,10 +97,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphf %v24, %v2
+;   br %r14
 
 function %load_i8x16_big(i64) -> i8x16 {
 block0(v0: i64):
@@ -73,9 +115,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i16x8_big(i64) -> i16x8 {
 block0(v0: i64):
@@ -83,9 +131,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i32x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -93,9 +147,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i64x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -103,9 +163,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i128_big(i64) -> i128 {
 block0(v0: i64):
@@ -113,10 +179,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v3, 0(%r3)
 ;   vst %v3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v3, 0(%r3)
+;   vst %v3, 0(%r2)
+;   br %r14
 
 function %load_f32x4_big(i64) -> f32x4 {
 block0(v0: i64):
@@ -124,9 +197,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_f64x2_big(i64) -> f64x2 {
 block0(v0: i64):
@@ -134,9 +213,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %store_i8x16_big(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -144,9 +229,15 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i16x8_big(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -154,9 +245,15 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i32x4_big(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -164,9 +261,15 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i64x2_big(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -174,9 +277,15 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i128_big(i128, i64) {
 block0(v0: i128, v1: i64):
@@ -184,10 +293,17 @@ block0(v0: i128, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vst %v1, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vst %v1, 0(%r3)
+;   br %r14
 
 function %store_f32x4_big(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -195,9 +311,15 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_f64x2_big(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -205,9 +327,15 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %uload8x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -215,10 +343,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -226,11 +361,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllh %v4, %v2, 8
 ;   vuplhh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllh %v4, %v2, 8
+;   vuplhh %v24, %v4
+;   br %r14
 
 function %uload32x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -238,11 +381,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   verllg %v4, %v2, 32
 ;   vuplhf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   verllg %v4, %v2, 0x20
+;   vuplhf %v24, %v4
+;   br %r14
 
 function %sload8x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -250,10 +403,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -261,11 +421,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllh %v4, %v2, 8
 ;   vuphh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllh %v4, %v2, 8
+;   vuphh %v24, %v4
+;   br %r14
 
 function %sload32x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -273,11 +441,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   verllg %v4, %v2, 32
 ;   vuphf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   verllg %v4, %v2, 0x20
+;   vuphf %v24, %v4
+;   br %r14
 
 function %load_i8x16_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -285,9 +463,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i16x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -295,9 +479,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrh %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r6
+;   br %r14
 
 function %load_i32x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -305,9 +497,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f6
+;   br %r14
 
 function %load_i64x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -315,9 +515,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f6
+;   br %r14
 
 function %load_i128_little(i64) -> i128 {
 block0(v0: i64):
@@ -325,10 +533,20 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v3, 0(%r3)
 ;   vst %v3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x30
+;   lper %f0, %f0
+;   sth %r0, 0x730(%r6, %r14)
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x0e
+;   br %r14
 
 function %load_f32x4_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -336,9 +554,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f6
+;   br %r14
 
 function %load_f64x2_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -346,9 +572,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f6
+;   br %r14
 
 function %store_i8x16_little(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -356,9 +590,15 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i16x8_little(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -366,9 +606,17 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrh %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r14
+;   br %r14
 
 function %store_i32x4_little(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -376,9 +624,17 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f14
+;   br %r14
 
 function %store_i64x2_little(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -386,9 +642,17 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f14
+;   br %r14
 
 function %store_i128_little(i128, i64) {
 block0(v0: i128, v1: i64):
@@ -396,10 +660,18 @@ block0(v0: i128, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vstbrq %v1, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   .byte 0xe6, 0x10
+;   lper %f0, %f0
+;   sth %r0, 0x7fe(%r14)
 
 function %store_f32x4_little(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -407,9 +679,17 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f14
+;   br %r14
 
 function %store_f64x2_little(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -417,7 +697,15 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f14
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif
index 19211d0855..af12fa8727 100644
--- a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif
@@ -7,10 +7,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -18,11 +27,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   verllh %v4, %v2, 8
 ;   vuplhh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   verllh %v4, %v2, 8
+;   vuplhh %v24, %v4
+;   br %r14
 
 function %uload32x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -30,11 +49,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllg %v4, %v2, 32
 ;   vuplhf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllg %v4, %v2, 0x20
+;   vuplhf %v24, %v4
+;   br %r14
 
 function %sload8x8_big(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -42,10 +69,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -53,11 +89,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   verllh %v4, %v2, 8
 ;   vuphh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   verllh %v4, %v2, 8
+;   vuphh %v24, %v4
+;   br %r14
 
 function %sload32x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -65,11 +111,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllg %v4, %v2, 32
 ;   vuphf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllg %v4, %v2, 0x20
+;   vuphf %v24, %v4
+;   br %r14
 
 function %load_i8x16_big(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -77,9 +131,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_i16x8_big(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -87,9 +148,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlerh %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r7
+;   br %r14
 
 function %load_i32x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -97,9 +166,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlerf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f7
+;   br %r14
 
 function %load_i64x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -107,9 +184,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlerg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f7
+;   br %r14
 
 function %load_f32x4_big(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -117,9 +202,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlerf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f7
+;   br %r14
 
 function %load_f64x2_big(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -127,9 +220,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlerg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f7
+;   br %r14
 
 function %store_i8x16_big(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -137,9 +238,16 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_i16x8_big(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -147,9 +255,17 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vsterh %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lr %r0, %r15
+;   br %r14
 
 function %store_i32x4_big(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -157,9 +273,17 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vsterf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f15
+;   br %r14
 
 function %store_i64x2_big(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -167,9 +291,17 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vsterg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f15
+;   br %r14
 
 function %store_f32x4_big(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -177,9 +309,17 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vsterf %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ldr %f0, %f15
+;   br %r14
 
 function %store_f64x2_big(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -187,9 +327,17 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vsterg %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   ler %f0, %f15
+;   br %r14
 
 function %uload8x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -197,10 +345,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -208,10 +365,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuplhh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuplhh %v24, %v2
+;   br %r14
 
 function %uload32x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -219,10 +385,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuplhf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuplhf %v24, %v2
+;   br %r14
 
 function %sload8x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -230,10 +405,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -241,10 +425,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuphh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuphh %v24, %v2
+;   br %r14
 
 function %sload32x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -252,10 +445,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlebrg %v2, 0(%r2), 0
 ;   vuphf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x20
+;   lpdr %f0, %f0
+;   .byte 0x00, 0x02
+;   vuphf %v24, %v2
+;   br %r14
 
 function %load_i8x16_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -263,9 +465,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_i16x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -273,9 +482,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_i32x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -283,9 +499,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_i64x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -293,9 +516,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_f32x4_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -303,9 +533,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %load_f64x2_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -313,9 +550,16 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vlbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r6)
 
 function %store_i8x16_little(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -323,9 +567,16 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_i16x8_little(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -333,9 +584,16 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_i32x4_little(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -343,9 +601,16 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_i64x2_little(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -353,9 +618,16 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_f32x4_little(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -363,9 +635,16 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
 function %store_f64x2_little(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -373,7 +652,14 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vstbrq %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0xe6, 0x80
+;   lpdr %f0, %f0
+;   lh %r0, 0x7fe(%r14)
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif
index 8f989d11a3..e372d86fe7 100644
--- a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif
@@ -7,11 +7,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuplhb %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuplhb %v24, %v4
+;   br %r14
 
 function %uload16x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -19,12 +27,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   verllh %v6, %v4, 8
 ;   vuplhh %v24, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   verllh %v6, %v4, 8
+;   vuplhh %v24, %v6
+;   br %r14
 
 function %uload32x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -32,11 +49,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllg %v4, %v2, 32
 ;   vuplhf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllg %v4, %v2, 0x20
+;   vuplhf %v24, %v4
+;   br %r14
 
 function %sload8x8_big(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -44,11 +69,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuphb %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuphb %v24, %v4
+;   br %r14
 
 function %sload16x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -56,12 +89,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   verllh %v6, %v4, 8
 ;   vuphh %v24, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   verllh %v6, %v4, 8
+;   vuphh %v24, %v6
+;   br %r14
 
 function %sload32x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -69,11 +111,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllg %v4, %v2, 32
 ;   vuphf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllg %v4, %v2, 0x20
+;   vuphf %v24, %v4
+;   br %r14
 
 function %load_i8x16_big(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -81,11 +131,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_i16x8_big(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -93,12 +151,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r2)
 ;   vpdi %v4, %v2, %v2, 4
 ;   verllg %v6, %v4, 32
 ;   verllf %v24, %v6, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r2)
+;   vpdi %v4, %v2, %v2, 4
+;   verllg %v6, %v4, 0x20
+;   verllf %v24, %v6, 0x10
+;   br %r14
 
 function %load_i32x4_big(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -106,11 +173,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r2)
 ;   vpdi %v4, %v2, %v2, 4
 ;   verllg %v24, %v4, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r2)
+;   vpdi %v4, %v2, %v2, 4
+;   verllg %v24, %v4, 0x20
+;   br %r14
 
 function %load_i64x2_big(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -118,10 +193,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r2)
 ;   vpdi %v24, %v2, %v2, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r2)
+;   vpdi %v24, %v2, %v2, 4
+;   br %r14
 
 function %load_f32x4_big(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -129,11 +211,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r2)
 ;   vpdi %v4, %v2, %v2, 4
 ;   verllg %v24, %v4, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r2)
+;   vpdi %v4, %v2, %v2, 4
+;   verllg %v24, %v4, 0x20
+;   br %r14
 
 function %load_f64x2_big(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -141,10 +231,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v2, 0(%r2)
 ;   vpdi %v24, %v2, %v2, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v2, 0(%r2)
+;   vpdi %v24, %v2, %v2, 4
+;   br %r14
 
 function %store_i8x16_big(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -152,12 +249,21 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_i16x8_big(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -165,12 +271,21 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
 ;   verllf %v7, %v5, 16
 ;   vst %v7, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   verllf %v7, %v5, 0x10
+;   vst %v7, 0(%r2)
+;   br %r14
 
 function %store_i32x4_big(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -178,11 +293,19 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %store_i64x2_big(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -190,10 +313,17 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   vst %v3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   vst %v3, 0(%r2)
+;   br %r14
 
 function %store_f32x4_big(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -201,11 +331,19 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
 ;   vst %v5, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   vst %v5, 0(%r2)
+;   br %r14
 
 function %store_f64x2_big(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -213,10 +351,17 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   vst %v3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   vst %v3, 0(%r2)
+;   br %r14
 
 function %uload8x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -224,11 +369,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuplhb %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuplhb %v24, %v4
+;   br %r14
 
 function %uload16x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -236,11 +389,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuplhh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuplhh %v24, %v4
+;   br %r14
 
 function %uload32x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -248,11 +409,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuplhf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuplhf %v24, %v4
+;   br %r14
 
 function %sload8x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -260,11 +429,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuphb %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuphb %v24, %v4
+;   br %r14
 
 function %sload16x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -272,11 +449,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuphh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuphh %v24, %v4
+;   br %r14
 
 function %sload32x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -284,11 +469,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   vuphf %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   vuphf %v24, %v4
+;   br %r14
 
 function %load_i8x16_little(i64) -> i8x16 wasmtime_system_v {
 block0(v0: i64):
@@ -296,11 +489,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_i16x8_little(i64) -> i16x8 wasmtime_system_v {
 block0(v0: i64):
@@ -308,11 +509,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_i32x4_little(i64) -> i32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -320,11 +529,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_i64x2_little(i64) -> i64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -332,11 +549,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_f32x4_little(i64) -> f32x4 wasmtime_system_v {
 block0(v0: i64):
@@ -344,11 +569,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_f64x2_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -356,11 +589,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %load_f64x2_sum_little(i64, i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64, v1: i64):
@@ -369,11 +610,19 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r3,%r2)
 ;   lrvg %r3, 8(%r3,%r2)
 ;   vlvgp %v24, %r3, %r5
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r3, %r2)
+;   lrvg %r3, 8(%r3, %r2)
+;   vlvgp %v24, %r3, %r5
+;   br %r14
 
 function %load_f64x2_off_little(i64) -> f64x2 wasmtime_system_v {
 block0(v0: i64):
@@ -381,11 +630,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 128(%r2)
 ;   lrvg %r2, 136(%r2)
 ;   vlvgp %v24, %r2, %r4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0x80(%r2)
+;   lrvg %r2, 0x88(%r2)
+;   vlvgp %v24, %r2, %r4
+;   br %r14
 
 function %store_i8x16_little(i8x16, i64) wasmtime_system_v {
 block0(v0: i8x16, v1: i64):
@@ -393,12 +650,21 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_i16x8_little(i16x8, i64) wasmtime_system_v {
 block0(v0: i16x8, v1: i64):
@@ -406,12 +672,21 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_i32x4_little(i32x4, i64) wasmtime_system_v {
 block0(v0: i32x4, v1: i64):
@@ -419,12 +694,21 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_i64x2_little(i64x2, i64) wasmtime_system_v {
 block0(v0: i64x2, v1: i64):
@@ -432,12 +716,21 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_f32x4_little(f32x4, i64) wasmtime_system_v {
 block0(v0: f32x4, v1: i64):
@@ -445,12 +738,21 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_f64x2_little(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -458,12 +760,21 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_f64x2_sum_little(f64x2, i64, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64, v2: i64):
@@ -472,12 +783,21 @@ block0(v0: f64x2, v1: i64, v2: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r4, %v24, 0
 ;   strvg %r5, 0(%r3,%r2)
 ;   strvg %r4, 8(%r3,%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r4, %v24, 0
+;   strvg %r5, 0(%r3, %r2)
+;   strvg %r4, 8(%r3, %r2)
+;   br %r14
 
 function %store_f64x2_off_little(f64x2, i64) wasmtime_system_v {
 block0(v0: f64x2, v1: i64):
@@ -485,10 +805,19 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vlgvg %r5, %v24, 1
 ;   vlgvg %r3, %v24, 0
 ;   strvg %r5, 128(%r2)
 ;   strvg %r3, 136(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vlgvg %r5, %v24, 1
+;   vlgvg %r3, %v24, 0
+;   strvg %r5, 0x80(%r2)
+;   strvg %r3, 0x88(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem.clif b/cranelift/filetests/filetests/isa/s390x/vecmem.clif
index 2dc80cf69d..3896ea8465 100644
--- a/cranelift/filetests/filetests/isa/s390x/vecmem.clif
+++ b/cranelift/filetests/filetests/isa/s390x/vecmem.clif
@@ -7,10 +7,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -18,10 +25,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhh %v24, %v2
+;   br %r14
 
 function %uload32x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -29,10 +43,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhf %v24, %v2
+;   br %r14
 
 function %sload8x8_big(i64) -> i16x8 {
 block0(v0: i64):
@@ -40,10 +61,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -51,10 +79,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphh %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphh %v24, %v2
+;   br %r14
 
 function %sload32x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -62,10 +97,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphf %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphf %v24, %v2
+;   br %r14
 
 function %load_i8x16_big(i64) -> i8x16 {
 block0(v0: i64):
@@ -73,9 +115,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i16x8_big(i64) -> i16x8 {
 block0(v0: i64):
@@ -83,9 +131,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i32x4_big(i64) -> i32x4 {
 block0(v0: i64):
@@ -93,9 +147,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i64x2_big(i64) -> i64x2 {
 block0(v0: i64):
@@ -103,9 +163,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i128_big(i64) -> i128 {
 block0(v0: i64):
@@ -113,10 +179,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v3, 0(%r3)
 ;   vst %v3, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v3, 0(%r3)
+;   vst %v3, 0(%r2)
+;   br %r14
 
 function %load_f32x4_big(i64) -> f32x4 {
 block0(v0: i64):
@@ -124,9 +197,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_f64x2_big(i64) -> f64x2 {
 block0(v0: i64):
@@ -134,9 +213,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %store_i8x16_big(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -144,9 +229,15 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i16x8_big(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -154,9 +245,15 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i32x4_big(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -164,9 +261,15 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i64x2_big(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -174,9 +277,15 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i128_big(i128, i64) {
 block0(v0: i128, v1: i64):
@@ -184,10 +293,17 @@ block0(v0: i128, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vst %v1, 0(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vst %v1, 0(%r3)
+;   br %r14
 
 function %store_f32x4_big(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -195,9 +311,15 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_f64x2_big(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -205,9 +327,15 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %uload8x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -215,10 +343,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuplhb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuplhb %v24, %v2
+;   br %r14
 
 function %uload16x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -226,11 +361,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllh %v4, %v2, 8
 ;   vuplhh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllh %v4, %v2, 8
+;   vuplhh %v24, %v4
+;   br %r14
 
 function %uload32x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -238,12 +381,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   verllg %v6, %v4, 32
 ;   vuplhf %v24, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   verllg %v6, %v4, 0x20
+;   vuplhf %v24, %v6
+;   br %r14
 
 function %sload8x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -251,10 +403,17 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   vuphb %v24, %v2
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   vuphb %v24, %v2
+;   br %r14
 
 function %sload16x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -262,11 +421,19 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   ld %f2, 0(%r2)
 ;   verllh %v4, %v2, 8
 ;   vuphh %v24, %v4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ld %f2, 0(%r2)
+;   verllh %v4, %v2, 8
+;   vuphh %v24, %v4
+;   br %r14
 
 function %sload32x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -274,12 +441,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   ldgr %f4, %r4
 ;   verllg %v6, %v4, 32
 ;   vuphf %v24, %v6
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   ldgr %f4, %r4
+;   verllg %v6, %v4, 0x20
+;   vuphf %v24, %v6
+;   br %r14
 
 function %load_i8x16_little(i64) -> i8x16 {
 block0(v0: i64):
@@ -287,9 +463,15 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   vl %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v24, 0(%r2)
+;   br %r14
 
 function %load_i16x8_little(i64) -> i16x8 {
 block0(v0: i64):
@@ -297,6 +479,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
@@ -305,6 +488,16 @@ block0(v0: i64):
 ;   verllg %v18, %v16, 32
 ;   verllf %v24, %v18, 16
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v16, %v6, %v6, 4
+;   verllg %v18, %v16, 0x20
+;   verllf %v24, %v18, 0x10
+;   br %r14
 
 function %load_i32x4_little(i64) -> i32x4 {
 block0(v0: i64):
@@ -312,6 +505,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
@@ -319,6 +513,15 @@ block0(v0: i64):
 ;   vpdi %v16, %v6, %v6, 4
 ;   verllg %v24, %v16, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v16, %v6, %v6, 4
+;   verllg %v24, %v16, 0x20
+;   br %r14
 
 function %load_i64x2_little(i64) -> i64x2 {
 block0(v0: i64):
@@ -326,12 +529,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v6, %r2, %r4
 ;   vpdi %v24, %v6, %v6, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v24, %v6, %v6, 4
+;   br %r14
 
 function %load_i128_little(i64) -> i128 {
 block0(v0: i64):
@@ -339,12 +551,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r3)
 ;   lrvg %r3, 8(%r3)
 ;   vlvgp %v7, %r3, %r5
 ;   vst %v7, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r3)
+;   lrvg %r3, 8(%r3)
+;   vlvgp %v7, %r3, %r5
+;   vst %v7, 0(%r2)
+;   br %r14
 
 function %load_f32x4_little(i64) -> f32x4 {
 block0(v0: i64):
@@ -352,6 +573,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
@@ -359,6 +581,15 @@ block0(v0: i64):
 ;   vpdi %v16, %v6, %v6, 4
 ;   verllg %v24, %v16, 32
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v16, %v6, %v6, 4
+;   verllg %v24, %v16, 0x20
+;   br %r14
 
 function %load_f64x2_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -366,12 +597,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 0(%r2)
 ;   lrvg %r2, 8(%r2)
 ;   vlvgp %v6, %r2, %r4
 ;   vpdi %v24, %v6, %v6, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0(%r2)
+;   lrvg %r2, 8(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v24, %v6, %v6, 4
+;   br %r14
 
 function %load_f64x2_sum_little(i64, i64) -> f64x2 {
 block0(v0: i64, v1: i64):
@@ -380,12 +620,21 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r5, 0(%r3,%r2)
 ;   lrvg %r3, 8(%r3,%r2)
 ;   vlvgp %v7, %r3, %r5
 ;   vpdi %v24, %v7, %v7, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r5, 0(%r3, %r2)
+;   lrvg %r3, 8(%r3, %r2)
+;   vlvgp %v7, %r3, %r5
+;   vpdi %v24, %v7, %v7, 4
+;   br %r14
 
 function %load_f64x2_off_little(i64) -> f64x2 {
 block0(v0: i64):
@@ -393,12 +642,21 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ; block0:
 ;   lrvg %r4, 128(%r2)
 ;   lrvg %r2, 136(%r2)
 ;   vlvgp %v6, %r2, %r4
 ;   vpdi %v24, %v6, %v6, 4
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   lrvg %r4, 0x80(%r2)
+;   lrvg %r2, 0x88(%r2)
+;   vlvgp %v6, %r2, %r4
+;   vpdi %v24, %v6, %v6, 4
+;   br %r14
 
 function %store_i8x16_little(i8x16, i64) {
 block0(v0: i8x16, v1: i64):
@@ -406,9 +664,15 @@ block0(v0: i8x16, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vst %v24, 0(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vst %v24, 0(%r2)
+;   br %r14
 
 function %store_i16x8_little(i16x8, i64) {
 block0(v0: i16x8, v1: i64):
@@ -416,6 +680,7 @@ block0(v0: i16x8, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
@@ -425,6 +690,17 @@ block0(v0: i16x8, v1: i64):
 ;   strvg %r3, 0(%r2)
 ;   strvg %r5, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   verllf %v7, %v5, 0x10
+;   vlgvg %r3, %v7, 1
+;   lgdr %r5, %f7
+;   strvg %r3, 0(%r2)
+;   strvg %r5, 8(%r2)
+;   br %r14
 
 function %store_i32x4_little(i32x4, i64) {
 block0(v0: i32x4, v1: i64):
@@ -432,6 +708,7 @@ block0(v0: i32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
@@ -440,6 +717,16 @@ block0(v0: i32x4, v1: i64):
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   vlgvg %r5, %v5, 1
+;   lgdr %r3, %f5
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_i64x2_little(i64x2, i64) {
 block0(v0: i64x2, v1: i64):
@@ -447,6 +734,7 @@ block0(v0: i64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   vlgvg %r3, %v3, 1
@@ -454,6 +742,15 @@ block0(v0: i64x2, v1: i64):
 ;   strvg %r3, 0(%r2)
 ;   strvg %r5, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   vlgvg %r3, %v3, 1
+;   lgdr %r5, %f3
+;   strvg %r3, 0(%r2)
+;   strvg %r5, 8(%r2)
+;   br %r14
 
 function %store_i128_little(i128, i64) {
 block0(v0: i128, v1: i64):
@@ -461,6 +758,7 @@ block0(v0: i128, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vl %v1, 0(%r2)
 ;   vlgvg %r2, %v1, 1
@@ -468,6 +766,15 @@ block0(v0: i128, v1: i64):
 ;   strvg %r2, 0(%r3)
 ;   strvg %r4, 8(%r3)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vl %v1, 0(%r2)
+;   vlgvg %r2, %v1, 1
+;   lgdr %r4, %f1
+;   strvg %r2, 0(%r3)
+;   strvg %r4, 8(%r3)
+;   br %r14
 
 function %store_f32x4_little(f32x4, i64) {
 block0(v0: f32x4, v1: i64):
@@ -475,6 +782,7 @@ block0(v0: f32x4, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   verllg %v5, %v3, 32
@@ -483,6 +791,16 @@ block0(v0: f32x4, v1: i64):
 ;   strvg %r5, 0(%r2)
 ;   strvg %r3, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   verllg %v5, %v3, 0x20
+;   vlgvg %r5, %v5, 1
+;   lgdr %r3, %f5
+;   strvg %r5, 0(%r2)
+;   strvg %r3, 8(%r2)
+;   br %r14
 
 function %store_f64x2_little(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -490,6 +808,7 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   vlgvg %r3, %v3, 1
@@ -497,6 +816,15 @@ block0(v0: f64x2, v1: i64):
 ;   strvg %r3, 0(%r2)
 ;   strvg %r5, 8(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   vlgvg %r3, %v3, 1
+;   lgdr %r5, %f3
+;   strvg %r3, 0(%r2)
+;   strvg %r5, 8(%r2)
+;   br %r14
 
 function %store_f64x2_sum_little(f64x2, i64, i64) {
 block0(v0: f64x2, v1: i64, v2: i64):
@@ -505,6 +833,7 @@ block0(v0: f64x2, v1: i64, v2: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v4, %v24, %v24, 4
 ;   vlgvg %r5, %v4, 1
@@ -512,6 +841,15 @@ block0(v0: f64x2, v1: i64, v2: i64):
 ;   strvg %r5, 0(%r3,%r2)
 ;   strvg %r4, 8(%r3,%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v4, %v24, %v24, 4
+;   vlgvg %r5, %v4, 1
+;   lgdr %r4, %f4
+;   strvg %r5, 0(%r3, %r2)
+;   strvg %r4, 8(%r3, %r2)
+;   br %r14
 
 function %store_f64x2_off_little(f64x2, i64) {
 block0(v0: f64x2, v1: i64):
@@ -519,6 +857,7 @@ block0(v0: f64x2, v1: i64):
   return
 }
 
+; VCode:
 ; block0:
 ;   vpdi %v3, %v24, %v24, 4
 ;   vlgvg %r3, %v3, 1
@@ -526,4 +865,13 @@ block0(v0: f64x2, v1: i64):
 ;   strvg %r3, 128(%r2)
 ;   strvg %r5, 136(%r2)
 ;   br %r14
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   vpdi %v3, %v24, %v24, 4
+;   vlgvg %r3, %v3, 1
+;   lgdr %r5, %f3
+;   strvg %r3, 0x80(%r2)
+;   strvg %r5, 0x88(%r2)
+;   br %r14
 
diff --git a/cranelift/filetests/filetests/isa/x64/amode-opt.clif b/cranelift/filetests/filetests/isa/x64/amode-opt.clif
index be955ae566..a842be4514 100644
--- a/cranelift/filetests/filetests/isa/x64/amode-opt.clif
+++ b/cranelift/filetests/filetests/isa/x64/amode-opt.clif
@@ -8,6 +8,7 @@ block0(v0: i64, v1: i64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rdi, %rsi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_add_imm(i64) -> i64 {
 block0(v0: i64):
@@ -24,6 +34,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -31,6 +42,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x2a(%rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_add_imm_order(i64) -> i64 {
 block0(v0: i64):
@@ -40,6 +60,7 @@ block0(v0: i64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -47,6 +68,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x2a(%rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_add_uext_imm(i64) -> i64 {
 block0(v0: i64):
@@ -57,6 +87,7 @@ block0(v0: i64):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,6 +95,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x2a(%rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_reg_reg_imm(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -74,6 +114,7 @@ block0(v0: i64, v1: i64):
     return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -81,6 +122,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x140(%rdi, %rsi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_reg_reg_imm_negative(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -91,6 +141,7 @@ block0(v0: i64, v1: i64):
     return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -98,6 +149,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq -1(%rdi, %rsi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_reg_reg_imm_scaled(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -109,6 +169,7 @@ block0(v0: i64, v1: i64):
     return v6
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -116,7 +177,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
-
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq -1(%rdi, %rsi, 8), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_reg_reg_imm_uext_scaled(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -129,6 +198,7 @@ block0(v0: i64, v1: i32):
     return v7
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -137,6 +207,16 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl %esi, %ecx
+;   movq -1(%rdi, %rcx, 8), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %amode_reg_reg_imm_uext_scaled_add(i64, i32, i32) -> i64 {
 block0(v0: i64, v1: i32, v2: i32):
@@ -150,6 +230,7 @@ block0(v0: i64, v1: i32, v2: i32):
     return v9
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -159,4 +240,15 @@ block0(v0: i64, v1: i32, v2: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %r8
+;   addl %edx, %r8d
+;   movq -1(%rdi, %r8, 4), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/band_not_bmi1.clif b/cranelift/filetests/filetests/isa/x64/band_not_bmi1.clif
index 96dc33ef33..2c93ffb4cd 100644
--- a/cranelift/filetests/filetests/isa/x64/band_not_bmi1.clif
+++ b/cranelift/filetests/filetests/isa/x64/band_not_bmi1.clif
@@ -8,6 +8,7 @@ block0(v0: i8, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,15 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andnl %edi, %esi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %reversed_operands(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -23,6 +33,7 @@ block0(v0: i8, v1: i8):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +41,13 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andnl %esi, %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/basic.clif b/cranelift/filetests/filetests/isa/x64/basic.clif
index ad20bcc4f0..9af3478b52 100644
--- a/cranelift/filetests/filetests/isa/x64/basic.clif
+++ b/cranelift/filetests/filetests/isa/x64/basic.clif
@@ -7,6 +7,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,4 +16,14 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addl %esi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/bitcast.clif b/cranelift/filetests/filetests/isa/x64/bitcast.clif
index 97418b56a6..cf804009b1 100644
--- a/cranelift/filetests/filetests/isa/x64/bitcast.clif
+++ b/cranelift/filetests/filetests/isa/x64/bitcast.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movd %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32) -> f32 {
 block0(v0: i32):
@@ -21,6 +31,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movd %edi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(f64) -> i64 {
 block0(v0: f64):
@@ -35,6 +55,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %xmm0, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64) -> f64 {
 block0(v0: i64):
@@ -49,6 +79,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,4 +87,13 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/bmask.clif b/cranelift/filetests/filetests/isa/x64/bmask.clif
index 9ac3e81af3..6e3504fd34 100644
--- a/cranelift/filetests/filetests/isa/x64/bmask.clif
+++ b/cranelift/filetests/filetests/isa/x64/bmask.clif
@@ -9,6 +9,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -19,6 +20,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   movq %rdi, %rax
+;   sbbq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i64_i32(i64) -> i32 {
 block0(v0: i64):
@@ -26,6 +39,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -36,6 +50,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i64_i16(i64) -> i16 {
 block0(v0: i64):
@@ -43,6 +69,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -53,6 +80,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i64_i8(i64) -> i8 {
 block0(v0: i64):
@@ -60,6 +99,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -70,6 +110,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i32_i64(i32) -> i64 {
 block0(v0: i32):
@@ -77,6 +129,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -87,6 +140,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   movq %rdi, %rax
+;   sbbq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i32_i32(i32) -> i32 {
 block0(v0: i32):
@@ -94,6 +159,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -104,6 +170,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i32_i16(i32) -> i16 {
 block0(v0: i32):
@@ -111,6 +189,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -121,6 +200,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i32_i8(i32) -> i8 {
 block0(v0: i32):
@@ -128,6 +219,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -138,6 +230,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i16_i64(i16) -> i64 {
 block0(v0: i16):
@@ -145,6 +249,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -155,6 +260,18 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   movq %rdi, %rax
+;   sbbq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i16_i32(i16) -> i32 {
 block0(v0: i16):
@@ -162,6 +279,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -172,6 +290,18 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i16_i16(i16) -> i16 {
 block0(v0: i16):
@@ -179,6 +309,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -189,6 +320,18 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i16_i8(i16) -> i8 {
 block0(v0: i16):
@@ -196,6 +339,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -206,6 +350,18 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i8_i64(i8) -> i64 {
 block0(v0: i8):
@@ -213,6 +369,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -223,6 +380,18 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   movq %rdi, %rax
+;   sbbq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i8_i32(i8) -> i32 {
 block0(v0: i8):
@@ -230,6 +399,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -240,6 +410,18 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i8_i16(i8) -> i16 {
 block0(v0: i8):
@@ -247,6 +429,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -257,6 +440,18 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i8_i8(i8) -> i8 {
 block0(v0: i8):
@@ -264,6 +459,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -274,6 +470,18 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   movq %rdi, %rax
+;   sbbl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i128_i128(i128) -> i128 {
 block0(v0: i128):
@@ -281,6 +489,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -293,6 +502,20 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rdx
+;   orq %rsi, %rdx
+;   movq %rdx, %r8
+;   negq %r8
+;   sbbq %rdx, %rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i128_i64(i128) -> i64 {
 block0(v0: i128):
@@ -300,6 +523,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -311,6 +535,19 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   orq %rsi, %rax
+;   movq %rax, %r8
+;   negq %r8
+;   sbbq %rax, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i128_i32(i128) -> i32 {
 block0(v0: i128):
@@ -318,6 +555,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -329,6 +567,19 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   orq %rsi, %rax
+;   movq %rax, %r8
+;   negq %r8
+;   sbbl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i128_i16(i128) -> i16 {
 block0(v0: i128):
@@ -336,6 +587,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -347,6 +599,19 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   orq %rsi, %rax
+;   movq %rax, %r8
+;   negq %r8
+;   sbbl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i128_i8(i128) -> i8 {
 block0(v0: i128):
@@ -354,6 +619,7 @@ block0(v0: i128):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -365,6 +631,19 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   orq %rsi, %rax
+;   movq %rax, %r8
+;   negq %r8
+;   sbbl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i64_i128(i64) -> i128 {
 block0(v0: i64):
@@ -372,6 +651,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -383,6 +663,19 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   movq %rdi, %rdx
+;   sbbq %rdi, %rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i32_i128(i32) -> i128 {
 block0(v0: i32):
@@ -390,6 +683,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -401,6 +695,19 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   movq %rdi, %rdx
+;   sbbq %rdi, %rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i16_i128(i16) -> i128 {
 block0(v0: i16):
@@ -408,6 +715,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -419,6 +727,19 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   movq %rdi, %rdx
+;   sbbq %rdi, %rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bmask_i8_i128(i8) -> i128 {
 block0(v0: i8):
@@ -426,6 +747,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -437,4 +759,17 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   movq %rdi, %rdx
+;   sbbq %rdi, %rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/branches.clif b/cranelift/filetests/filetests/isa/x64/branches.clif
index d2dc7d9698..22b6635364 100644
--- a/cranelift/filetests/filetests/isa/x64/branches.clif
+++ b/cranelift/filetests/filetests/isa/x64/branches.clif
@@ -15,6 +15,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,6 +31,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   jne 0x16
+; block1: ; offset 0xc
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x16
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -45,6 +63,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -60,6 +79,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   jne 0x16
+; block1: ; offset 0xc
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x16
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -75,6 +111,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -90,6 +127,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   jne 0x16
+; block1: ; offset 0xc
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x16
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(f32, f32) -> i32 {
 block0(v0: f32, v1: f32):
@@ -105,6 +159,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -121,6 +176,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm1, %xmm0
+;   jp 0x1d
+;   jne 0x1d
+; block1: ; offset 0x13
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x1d
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32, f32) -> i8 {
 block0(v0: f32, v1: f32):
@@ -134,6 +207,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -150,6 +224,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm1, %xmm0
+;   jp 0x1a
+;   jne 0x1a
+; block1: ; offset 0x13
+;   xorl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x1a
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32, f32) -> i8 {
 block0(v0: f32, v1: f32):
@@ -163,6 +255,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -179,6 +272,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm1, %xmm0
+;   jp 0x13
+;   je 0x1a
+; block1: ; offset 0x13
+;   xorl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x1a
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i32) -> i8 {
 block0(v0: i32):
@@ -193,6 +304,7 @@ block2:
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -212,6 +324,34 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl $2, %edi
+;   jae 0x34
+;   movl %edi, %r9d
+;   movl $0, %r8d
+;   cmovaeq %r8, %r9
+;   leaq 0xb(%rip), %r8
+;   movslq (%r8, %r9, 4), %r9
+;   addq %r9, %r8
+;   jmpq *%r8
+;   orb %al, (%rax)
+;   addb %al, (%rax)
+;   adcb (%rax), %al
+;   addb %al, (%rax)
+; block1: ; offset 0x34
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x3e
+;   xorl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i64) -> i8 {
 block0(v0: i64):
@@ -226,6 +366,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -241,6 +382,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpq $0, %rdi
+;   jge 0x18
+; block1: ; offset 0xe
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x18
+;   xorl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i32) -> i8 {
 block0(v0: i32):
@@ -255,6 +413,7 @@ block2:
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -270,6 +429,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl $0, %edi
+;   jge 0x17
+; block1: ; offset 0xd
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x17
+;   xorl %eax, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %fflags(f32) {
 block200(v0: f32):
@@ -291,6 +467,7 @@ block202:
     trap heap_oob
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -314,7 +491,27 @@ block202:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
-
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x42500000, %edx
+;   movd %edx, %xmm6
+;   ucomiss %xmm6, %xmm0
+;   jp 0x1c
+;   je 0x33
+; block1: ; offset 0x1c
+;   movl $0x42500000, %r11d
+;   movd %r11d, %xmm10
+;   ucomiss %xmm10, %xmm0
+;   jp 0x33
+; block2: ; offset 0x31
+;   ud2 ; trap: heap_oob
+; block3: ; offset 0x33
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %br_i8_icmp(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -331,6 +528,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -346,6 +544,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   jne 0x16
+; block1: ; offset 0xc
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x16
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %br_i8_fcmp(f32, f32) -> i32 {
 block0(v0: f32, v1: f32):
@@ -362,6 +577,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -378,6 +594,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm1, %xmm0
+;   jp 0x1d
+;   jne 0x1d
+; block1: ; offset 0x13
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x1d
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %brif_i8_icmp(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -394,6 +628,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -409,6 +644,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   jne 0x16
+; block1: ; offset 0xc
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x16
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %brif_i8_fcmp(f32, f32) -> i32 {
 block0(v0: f32, v1: f32):
@@ -425,6 +677,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -441,3 +694,22 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm1, %xmm0
+;   jp 0x1d
+;   jne 0x1d
+; block1: ; offset 0x13
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x1d
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/bswap.clif b/cranelift/filetests/filetests/isa/x64/bswap.clif
index 67235452a6..65d73157af 100644
--- a/cranelift/filetests/filetests/isa/x64/bswap.clif
+++ b/cranelift/filetests/filetests/isa/x64/bswap.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   bswapq %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -22,6 +33,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,6 +42,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   bswapl %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16) -> i16 {
 block0(v0: i16):
@@ -37,6 +59,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -45,4 +68,14 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   rolw $8, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/call-conv.clif b/cranelift/filetests/filetests/isa/x64/call-conv.clif
index 3653f23329..351c6ca283 100644
--- a/cranelift/filetests/filetests/isa/x64/call-conv.clif
+++ b/cranelift/filetests/filetests/isa/x64/call-conv.clif
@@ -9,6 +9,7 @@ block0(v0: i32):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -21,6 +22,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rcx
+;   subq $0x20, %rsp
+;   callq *%rcx
+;   addq $0x20, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %two_args(i32, f32) system_v {
     ;; system_v has params in %rdi, %xmm0, fascall in %rcx, %xmm1
@@ -32,6 +45,7 @@ block0(v0: i32, v1: f32):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +62,22 @@ block0(v0: i32, v1: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm6
+;   subq $0x20, %rsp
+;   movq %rdi, %rcx
+;   movdqa %xmm6, %xmm1
+;   callq *%rdi
+;   addq $0x20, %rsp
+;   movdqa %xmm6, %xmm0
+;   callq *%rdi
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %fastcall_to_systemv(i32) windows_fastcall {
     ;; fastcall preserves xmm6+, rbx, rbp, rdi, rsi, r12-r15
@@ -58,6 +88,7 @@ block0(v0: i32):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $176, %rsp
@@ -91,6 +122,41 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0xb0, %rsp
+;   movq %rsi, (%rsp)
+;   movq %rdi, 8(%rsp)
+;   movdqu %xmm6, 0x10(%rsp)
+;   movdqu %xmm7, 0x20(%rsp)
+;   movdqu %xmm8, 0x30(%rsp)
+;   movdqu %xmm9, 0x40(%rsp)
+;   movdqu %xmm10, 0x50(%rsp)
+;   movdqu %xmm11, 0x60(%rsp)
+;   movdqu %xmm12, 0x70(%rsp)
+;   movdqu %xmm13, 0x80(%rsp)
+;   movdqu %xmm14, 0x90(%rsp)
+;   movdqu %xmm15, 0xa0(%rsp)
+; block0: ; offset 0x61
+;   callq *%rcx
+;   movq (%rsp), %rsi
+;   movq 8(%rsp), %rdi
+;   movdqu 0x10(%rsp), %xmm6
+;   movdqu 0x20(%rsp), %xmm7
+;   movdqu 0x30(%rsp), %xmm8
+;   movdqu 0x40(%rsp), %xmm9
+;   movdqu 0x50(%rsp), %xmm10
+;   movdqu 0x60(%rsp), %xmm11
+;   movdqu 0x70(%rsp), %xmm12
+;   movdqu 0x80(%rsp), %xmm13
+;   movdqu 0x90(%rsp), %xmm14
+;   movdqu 0xa0(%rsp), %xmm15
+;   addq $0xb0, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %many_args(
     ;; rdi, rsi, rdx, rcx, r8, r9,
@@ -122,6 +188,7 @@ block0(
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -159,6 +226,43 @@ block0(
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rcx, %rax
+;   movq %rdx, %rcx
+;   movq %rsi, %rdx
+;   movq %rdi, %rsi
+;   movq %rax, %rdi
+;   movq 0x10(%rbp), %r10
+;   movq 0x18(%rbp), %r11
+;   movss 0x20(%rbp), %xmm9
+;   movsd 0x28(%rbp), %xmm8
+;   subq $0x90, %rsp
+;   movq %r8, 0x20(%rsp)
+;   movq %r9, 0x28(%rsp)
+;   movsd %xmm0, 0x30(%rsp)
+;   movsd %xmm1, 0x38(%rsp)
+;   movsd %xmm2, 0x40(%rsp)
+;   movsd %xmm3, 0x48(%rsp)
+;   movsd %xmm4, 0x50(%rsp)
+;   movsd %xmm5, 0x58(%rsp)
+;   movsd %xmm6, 0x60(%rsp)
+;   movsd %xmm7, 0x68(%rsp)
+;   movq %r10, 0x70(%rsp)
+;   movl %r11d, 0x78(%rsp)
+;   movss %xmm9, 0x80(%rsp)
+;   movsd %xmm8, 0x88(%rsp)
+;   movq %rdi, %r9
+;   movq %rcx, %r8
+;   movq %rsi, %rcx
+;   callq *%rcx
+;   addq $0x90, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %many_ints(i64, i64, i64, i64, i64) system_v {
     ;; rdi => rcx
@@ -172,6 +276,7 @@ block0(v0: i64, v1:i64, v2:i64, v3:i64, v4:i64):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -189,6 +294,23 @@ block0(v0: i64, v1:i64, v2:i64, v3:i64, v4:i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %r11
+;   movq %rcx, %r9
+;   movq %rsi, %rdx
+;   movq %rdi, %rcx
+;   subq $0x30, %rsp
+;   movq %r8, 0x20(%rsp)
+;   movq %r11, %r8
+;   callq *%rcx
+;   addq $0x30, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %many_args2(i32, f32, i64, f64, i32, i32, i32, f32, f64, f32, f64) system_v {
     sig0 = (i32, f32, i64, f64, i32, i32, i32, f32, f64, f32, f64) windows_fastcall
@@ -197,6 +319,7 @@ block0(v0: i32, v1: f32, v2: i64, v3: f64, v4: i32, v5: i32, v6: i32, v7: f32, v
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -222,6 +345,31 @@ block0(v0: i32, v1: f32, v2: i64, v3: f64, v4: i32, v5: i32, v6: i32, v7: f32, v
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %r9
+;   movq %rdi, %rsi
+;   movdqa %xmm1, %xmm12
+;   movdqa %xmm0, %xmm1
+;   subq $0x60, %rsp
+;   movl %edx, 0x20(%rsp)
+;   movl %ecx, 0x28(%rsp)
+;   movl %r8d, 0x30(%rsp)
+;   movss %xmm2, 0x38(%rsp)
+;   movsd %xmm3, 0x40(%rsp)
+;   movss %xmm4, 0x48(%rsp)
+;   movsd %xmm5, 0x50(%rsp)
+;   movq %rsi, %rcx
+;   movq %r9, %r8
+;   movdqa %xmm12, %xmm3
+;   callq *%rcx
+;   addq $0x60, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix1(i32) wasmtime_system_v {
     sig0 = (i32) system_v
@@ -230,6 +378,7 @@ block0(v0: i32):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -237,6 +386,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   callq *%rdi
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix2(i32) system_v {
     sig0 = (i32) wasmtime_system_v
@@ -245,6 +403,7 @@ block0(v0: i32):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -252,6 +411,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   callq *%rdi
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix2() -> i32, i32 system_v {
     sig0 = () -> i32, i32 wasmtime_system_v
@@ -261,6 +429,7 @@ block0:
     return v0, v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -275,6 +444,20 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $1, %esi
+;   subq $0x10, %rsp
+;   leaq (%rsp), %rdi
+;   callq *%rsi
+;   movq (%rsp), %rdx
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix3() -> i32, i32 wasmtime_system_v {
     sig0 = () -> i32, i32 system_v
@@ -284,6 +467,7 @@ block0:
     return v0, v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -299,6 +483,23 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %rbx, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdi, %rbx
+;   movl $1, %eax
+;   callq *%rax
+;   movq %rbx, %rdi
+;   movl %edx, (%rdi)
+;   movq (%rsp), %rbx
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix4() -> i32, i64, i32 wasmtime_system_v {
     sig0 = () -> i32, i64, i32 system_v
@@ -308,6 +509,7 @@ block0:
     return v0, v1, v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -330,6 +532,28 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r13, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdi, %r13
+;   movl $1, %eax
+;   subq $0x10, %rsp
+;   leaq (%rsp), %rdi
+;   callq *%rax
+;   movq (%rsp), %rdi
+;   addq $0x10, %rsp
+;   movq %r13, %r9
+;   movq %rdx, (%r9)
+;   movl %edi, 8(%r9)
+;   movq (%rsp), %r13
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix5() -> f32, i64, i32, f32 wasmtime_system_v {
     sig0 = () -> f32, i64, i32, f32 system_v
@@ -339,6 +563,7 @@ block0:
     return v0, v1, v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -356,6 +581,25 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r13, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdi, %r13
+;   movl $1, %eax
+;   callq *%rax
+;   movq %r13, %rdi
+;   movq %rax, (%rdi)
+;   movl %edx, 8(%rdi)
+;   movss %xmm1, 0xc(%rdi)
+;   movq (%rsp), %r13
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %wasmtime_mix6(f32, i64, i32, f32) -> f32, i64, i32, f32 wasmtime_system_v {
     sig0 = (f32, i64, i32, f32) -> f32, i64, i32, f32 system_v
@@ -365,6 +609,7 @@ block0(v0: f32, v1: i64, v2: i32, v3: f32):
     return v5, v6, v7, v8
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -382,4 +627,23 @@ block0(v0: f32, v1: i64, v2: i32, v3: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r12, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdx, %r12
+;   movl $1, %r9d
+;   callq *%r9
+;   movq %r12, %r8
+;   movq %rax, (%r8)
+;   movl %edx, 8(%r8)
+;   movss %xmm1, 0xc(%r8)
+;   movq (%rsp), %r12
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif b/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif
index f45525d33e..e3c28f1aa9 100644
--- a/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %CeilF32 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -22,6 +33,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +42,14 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %CeilF64 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/ceil.clif b/cranelift/filetests/filetests/isa/x64/ceil.clif
index 743f0e70a9..f16eb297a1 100644
--- a/cranelift/filetests/filetests/isa/x64/ceil.clif
+++ b/cranelift/filetests/filetests/isa/x64/ceil.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundss $2, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -21,6 +31,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundsd $2, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -35,6 +55,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundps $2, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -49,6 +79,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,4 +87,13 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundpd $2, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/clz-lzcnt.clif b/cranelift/filetests/filetests/isa/x64/clz-lzcnt.clif
index 38a42e95b4..6f6cf79d8d 100644
--- a/cranelift/filetests/filetests/isa/x64/clz-lzcnt.clif
+++ b/cranelift/filetests/filetests/isa/x64/clz-lzcnt.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   lzcntq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %clz(i32) -> i32 {
 block0(v0: i32):
@@ -21,6 +31,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,4 +39,13 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   lzcntl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif b/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif
index 50cb04ebed..8ed9d5b84e 100644
--- a/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif
+++ b/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif
@@ -10,6 +10,7 @@ block0(v0: i64, v1: i64):
     return v4, v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -23,6 +24,21 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rsi), %r9 ; trap: heap_oob
+;   cmpq %r9, %rdi
+;   sete %r10b
+;   movzbq %r10b, %rax
+;   cmpq %r9, %rdi
+;   movq %rsi, %rdx
+;   cmoveq %rdi, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(f64, i64) -> i64, f64 {
 block0(v0: f64, v1: i64):
@@ -33,6 +49,7 @@ block0(v0: f64, v1: i64):
     return v4, v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -49,4 +66,24 @@ block0(v0: f64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsd (%rdi), %xmm9 ; trap: heap_oob
+;   ucomisd %xmm9, %xmm0
+;   setnp %dil
+;   sete %al
+;   andl %eax, %edi
+;   movzbq %dil, %rax
+;   ucomisd %xmm0, %xmm9
+;   movdqa %xmm0, %xmm2
+;   je 0x2f
+;   movsd %xmm2, %xmm0
+;   jnp 0x39
+;   movsd %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/conditional-values.clif b/cranelift/filetests/filetests/isa/x64/conditional-values.clif
index fa2aa0cd71..82f6c3bee8 100644
--- a/cranelift/filetests/filetests/isa/x64/conditional-values.clif
+++ b/cranelift/filetests/filetests/isa/x64/conditional-values.clif
@@ -7,6 +7,7 @@ block0(v0: i8, v1: i32, v2: i32):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i8, v1: i32, v2: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   testb %dil, %dil
+;   movq %rdx, %rax
+;   cmovnel %esi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i8) -> i32 {
 block0(v0: i8):
@@ -28,6 +40,7 @@ block2:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -43,6 +56,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   testb %dil, %dil
+;   je 0x17
+; block1: ; offset 0xd
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x17
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i8) -> i32 {
 block0(v0: i8):
@@ -55,6 +85,7 @@ block2:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -70,6 +101,23 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   testb %dil, %dil
+;   je 0x17
+; block1: ; offset 0xd
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x17
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64) -> i32 {
 block0(v0: i64):
@@ -85,6 +133,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -101,6 +150,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl (%rdi), %edx ; trap: heap_oob
+;   cmpl $1, %edx
+;   jne 0x19
+; block1: ; offset 0xf
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x19
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64) -> i32 {
 block0(v0: i64):
@@ -116,6 +183,7 @@ block2:
   return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -132,6 +200,24 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl (%rdi), %edx ; trap: heap_oob
+;   cmpl $1, %edx
+;   jne 0x19
+; block1: ; offset 0xf
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x19
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_x_slt_0_i64(i64) -> i8 {
 block0(v0: i64):
@@ -140,6 +226,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -148,6 +235,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrq $0x3f, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_x_slt_0_i32f4(i32) -> i8 {
 block0(v0: i32):
@@ -156,6 +253,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -164,6 +262,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrl $0x1f, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_0_sgt_x_i64(i64) -> i8 {
 block0(v0: i64):
@@ -172,6 +280,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -180,6 +289,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrq $0x3f, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_0_sgt_x_i32f4(i32) -> i8 {
 block0(v0: i32):
@@ -188,6 +307,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -196,6 +316,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrl $0x1f, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_0_sle_x_i64(i64) -> i8 {
 block0(v0: i64):
@@ -204,6 +334,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -213,6 +344,17 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   notq %rax
+;   shrq $0x3f, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_0_sle_x_i32f4(i32) -> i8 {
 block0(v0: i32):
@@ -221,6 +363,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -230,6 +373,17 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   notq %rax
+;   shrl $0x1f, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_x_sge_x_i64(i64) -> i8 {
 block0(v0: i64):
@@ -238,6 +392,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -247,6 +402,17 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   notq %rax
+;   shrq $0x3f, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %test_x_sge_x_i32f4(i32) -> i8 {
 block0(v0: i32):
@@ -255,6 +421,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -264,4 +431,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   notq %rax
+;   shrl $0x1f, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/ctz-bmi1.clif b/cranelift/filetests/filetests/isa/x64/ctz-bmi1.clif
index e0ff8122bb..d41e68cb2c 100644
--- a/cranelift/filetests/filetests/isa/x64/ctz-bmi1.clif
+++ b/cranelift/filetests/filetests/isa/x64/ctz-bmi1.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   tzcntq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ctz(i32) -> i32 {
 block0(v0: i32):
@@ -21,6 +31,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,4 +39,13 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   tzcntl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/div-checks.clif b/cranelift/filetests/filetests/isa/x64/div-checks.clif
index 573e9794ff..173c01beaa 100644
--- a/cranelift/filetests/filetests/isa/x64/div-checks.clif
+++ b/cranelift/filetests/filetests/isa/x64/div-checks.clif
@@ -14,6 +14,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -24,6 +25,26 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpb $0, %sil
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpb $0xff, %sil
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cbtw
+;   idivb %sil ; trap: int_divz
+;   shrq $8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -32,6 +53,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +64,26 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpw $0, %si
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpw $-1, %si
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cwtd
+;   idivw %si ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -50,6 +92,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -60,6 +103,26 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpl $0, %esi
+;   jne 0x14
+;   ud2 ; trap: int_divz
+;   cmpl $-1, %esi
+;   jne 0x27
+;   movl $0, %eax
+;   jmp 0x2a
+;   cltd
+;   idivl %esi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -68,6 +131,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -78,4 +142,24 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpq $0, %rsi
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpq $-1, %rsi
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cqto
+;   idivq %rsi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/extractlane.clif b/cranelift/filetests/filetests/isa/x64/extractlane.clif
index 448e61abea..9459a09d34 100644
--- a/cranelift/filetests/filetests/isa/x64/extractlane.clif
+++ b/cranelift/filetests/filetests/isa/x64/extractlane.clif
@@ -7,6 +7,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pextrb $1, %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16x8) -> i16 {
 block0(v0: i16x8):
@@ -21,6 +31,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pextrw $1, %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32x4) -> i32 {
 block0(v0: i32x4):
@@ -35,6 +55,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pextrd $1, %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64x2) -> i64 {
 block0(v0: i64x2):
@@ -49,6 +79,7 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,6 +87,15 @@ block0(v0: i64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pextrq $1, %xmm0, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(f32x4) -> f32 {
 block0(v0: f32x4):
@@ -63,6 +103,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -70,6 +111,15 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(f64x2) -> f64 {
 block0(v0: f64x2):
@@ -77,6 +127,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -84,4 +135,13 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0xee, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fabs.clif b/cranelift/filetests/filetests/isa/x64/fabs.clif
index 88c7909590..5ef0e0d3be 100644
--- a/cranelift/filetests/filetests/isa/x64/fabs.clif
+++ b/cranelift/filetests/filetests/isa/x64/fabs.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x7fffffff, %eax
+;   movd %eax, %xmm4
+;   andps %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -23,6 +35,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x7fffffffffffffff, %rax
+;   movq %rax, %xmm4
+;   andpd %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -39,6 +63,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +73,17 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm3, %xmm3
+;   psrld $1, %xmm3
+;   andps %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -55,6 +91,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,4 +101,15 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm3, %xmm3
+;   psrlq $1, %xmm3
+;   andpd %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fastcall.clif b/cranelift/filetests/filetests/isa/x64/fastcall.clif
index 0f6f7828ed..f6c97c1cef 100644
--- a/cranelift/filetests/filetests/isa/x64/fastcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/fastcall.clif
@@ -8,6 +8,7 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64):
   return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -17,12 +18,22 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rcx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i64, i64, i64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: i64, v3: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -32,12 +43,22 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i64, i64, i64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: i64, v3: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -47,12 +68,22 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64, i64, i64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: i64, v3: i64):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -62,12 +93,22 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %r9, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64, f64, i64) -> f64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: f64, v3: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -77,12 +118,22 @@ block0(v0: i64, v1: i64, v2: f64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i64, i64, f64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: f64, v3: i64):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -92,6 +143,15 @@ block0(v0: i64, v1: i64, v2: f64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %r9, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i64, i64, i64, i64, i64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64):
@@ -108,6 +168,7 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64):
 ;; TODO(#2704): fix regalloc's register priority ordering!
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -118,12 +179,23 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x30(%rbp), %r8
+;   movq 0x38(%rbp), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i128, i64, i128, i128) -> i128 windows_fastcall {
 block0(v0: i128, v1: i64, v2: i128, v3: i128):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -135,6 +207,17 @@ block0(v0: i128, v1: i64, v2: i128, v3: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq 0x30(%rbp), %r8
+;   movq 0x38(%rbp), %rax
+;   movq 0x40(%rbp), %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f8(i64) -> i64 windows_fastcall {
   sig0 = (i64, i64, f64, f64, i64, i64) -> i64 windows_fastcall
@@ -146,6 +229,7 @@ block0(v0: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -166,6 +250,24 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtsi2sdq %rcx, %xmm3
+;   subq $0x30, %rsp
+;   movq %rcx, 0x20(%rsp)
+;   movq %rcx, 0x28(%rsp)
+;   movq %rcx, %rdx
+;   movabsq $0, %r11 ; reloc_external Abs8 %g 0
+;   movq %rdx, %rcx
+;   movdqa %xmm3, %xmm2
+;   callq *%r11
+;   addq $0x30, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f9(i64) -> f64 windows_fastcall {
 block0(v0: i64):
@@ -217,6 +319,7 @@ block0(v0: i64):
   return v39
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   unwind PushFrameRegs { offset_upward_to_caller_sp: 16 }
 ;   movq    %rsp, %rbp
@@ -308,4 +411,85 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x100, %rsp
+;   movdqu %xmm6, 0x60(%rsp)
+;   movdqu %xmm7, 0x70(%rsp)
+;   movdqu %xmm8, 0x80(%rsp)
+;   movdqu %xmm9, 0x90(%rsp)
+;   movdqu %xmm10, 0xa0(%rsp)
+;   movdqu %xmm11, 0xb0(%rsp)
+;   movdqu %xmm12, 0xc0(%rsp)
+;   movdqu %xmm13, 0xd0(%rsp)
+;   movdqu %xmm14, 0xe0(%rsp)
+;   movdqu %xmm15, 0xf0(%rsp)
+; block0: ; offset 0x67
+;   movsd (%rcx), %xmm0 ; trap: heap_oob
+;   movsd 8(%rcx), %xmm10 ; trap: heap_oob
+;   movdqu %xmm10, 0x50(%rsp)
+;   movsd 0x10(%rcx), %xmm2 ; trap: heap_oob
+;   movdqu %xmm2, (%rsp)
+;   movsd 0x18(%rcx), %xmm14 ; trap: heap_oob
+;   movdqu %xmm14, 0x40(%rsp)
+;   movsd 0x20(%rcx), %xmm13 ; trap: heap_oob
+;   movsd 0x28(%rcx), %xmm15 ; trap: heap_oob
+;   movdqu %xmm15, 0x30(%rsp)
+;   movsd 0x30(%rcx), %xmm7 ; trap: heap_oob
+;   movsd 0x38(%rcx), %xmm5 ; trap: heap_oob
+;   movdqu %xmm5, 0x20(%rsp)
+;   movsd 0x40(%rcx), %xmm12 ; trap: heap_oob
+;   movsd 0x48(%rcx), %xmm4 ; trap: heap_oob
+;   movdqu %xmm4, 0x10(%rsp)
+;   movsd 0x50(%rcx), %xmm9 ; trap: heap_oob
+;   movsd 0x58(%rcx), %xmm4 ; trap: heap_oob
+;   movsd 0x60(%rcx), %xmm3 ; trap: heap_oob
+;   movsd 0x68(%rcx), %xmm8 ; trap: heap_oob
+;   movsd 0x70(%rcx), %xmm11 ; trap: heap_oob
+;   movsd 0x78(%rcx), %xmm10 ; trap: heap_oob
+;   movsd 0x80(%rcx), %xmm6 ; trap: heap_oob
+;   movsd 0x88(%rcx), %xmm14 ; trap: heap_oob
+;   movsd 0x90(%rcx), %xmm1 ; trap: heap_oob
+;   movsd 0x98(%rcx), %xmm15 ; trap: heap_oob
+;   movdqu 0x50(%rsp), %xmm2
+;   addsd %xmm2, %xmm0
+;   movdqu (%rsp), %xmm2
+;   movdqu 0x40(%rsp), %xmm5
+;   addsd %xmm5, %xmm2
+;   movdqu 0x30(%rsp), %xmm5
+;   addsd %xmm5, %xmm13
+;   movdqu 0x20(%rsp), %xmm5
+;   addsd %xmm5, %xmm7
+;   movdqu 0x10(%rsp), %xmm5
+;   addsd %xmm5, %xmm12
+;   addsd %xmm4, %xmm9
+;   addsd %xmm8, %xmm3
+;   addsd %xmm10, %xmm11
+;   addsd %xmm14, %xmm6
+;   addsd %xmm15, %xmm1
+;   addsd %xmm2, %xmm0
+;   addsd %xmm7, %xmm13
+;   addsd %xmm9, %xmm12
+;   addsd %xmm11, %xmm3
+;   addsd %xmm1, %xmm6
+;   addsd %xmm13, %xmm0
+;   addsd %xmm3, %xmm12
+;   addsd %xmm12, %xmm0
+;   addsd %xmm6, %xmm0
+;   movdqu 0x60(%rsp), %xmm6
+;   movdqu 0x70(%rsp), %xmm7
+;   movdqu 0x80(%rsp), %xmm8
+;   movdqu 0x90(%rsp), %xmm9
+;   movdqu 0xa0(%rsp), %xmm10
+;   movdqu 0xb0(%rsp), %xmm11
+;   movdqu 0xc0(%rsp), %xmm12
+;   movdqu 0xd0(%rsp), %xmm13
+;   movdqu 0xe0(%rsp), %xmm14
+;   movdqu 0xf0(%rsp), %xmm15
+;   addq $0x100, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fcopysign.clif b/cranelift/filetests/filetests/isa/x64/fcopysign.clif
index 344159440e..243dc5612a 100644
--- a/cranelift/filetests/filetests/isa/x64/fcopysign.clif
+++ b/cranelift/filetests/filetests/isa/x64/fcopysign.clif
@@ -7,6 +7,7 @@ block0(v0: f32, v1: f32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -20,6 +21,21 @@ block0(v0: f32, v1: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x80000000, %ecx
+;   movd %ecx, %xmm7
+;   movdqa %xmm0, %xmm10
+;   movdqa %xmm7, %xmm0
+;   andnps %xmm10, %xmm0
+;   andps %xmm1, %xmm7
+;   orps %xmm7, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(f64, f64) -> f64 {
 block0(v0: f64, v1: f64):
@@ -27,6 +43,7 @@ block0(v0: f64, v1: f64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -40,4 +57,19 @@ block0(v0: f64, v1: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $9223372036854775808, %rcx
+;   movq %rcx, %xmm7
+;   movdqa %xmm0, %xmm10
+;   movdqa %xmm7, %xmm0
+;   andnpd %xmm10, %xmm0
+;   andpd %xmm1, %xmm7
+;   orpd %xmm7, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fcvt-simd.clif b/cranelift/filetests/filetests/isa/x64/fcvt-simd.clif
index 8ac1b0d94c..5f38389e65 100644
--- a/cranelift/filetests/filetests/isa/x64/fcvt-simd.clif
+++ b/cranelift/filetests/filetests/isa/x64/fcvt-simd.clif
@@ -8,6 +8,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,4 +16,13 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   vcvtudq2ps %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fcvt.clif b/cranelift/filetests/filetests/isa/x64/fcvt.clif
index 87b5e21a16..b6ca34f51e 100644
--- a/cranelift/filetests/filetests/isa/x64/fcvt.clif
+++ b/cranelift/filetests/filetests/isa/x64/fcvt.clif
@@ -7,6 +7,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsbl %dil, %eax
+;   cvtsi2ssl %eax, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16) -> f32 {
 block0(v0: i16):
@@ -22,6 +33,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,6 +42,16 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movswl %di, %eax
+;   cvtsi2ssl %eax, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32) -> f32 {
 block0(v0: i32):
@@ -37,6 +59,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -44,6 +67,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtsi2ssl %edi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64) -> f32 {
 block0(v0: i64):
@@ -51,6 +83,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -58,6 +91,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtsi2ssq %rdi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i8) -> f64 {
 block0(v0: i8):
@@ -65,6 +107,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -73,6 +116,16 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsbl %dil, %eax
+;   cvtsi2sdl %eax, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i16) -> f64 {
 block0(v0: i16):
@@ -80,6 +133,7 @@ block0(v0: i16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -88,6 +142,16 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movswl %di, %eax
+;   cvtsi2sdl %eax, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i32) -> f64 {
 block0(v0: i32):
@@ -95,6 +159,7 @@ block0(v0: i32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -102,6 +167,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtsi2sdl %edi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f8(i64) -> f64 {
 block0(v0: i64):
@@ -109,6 +183,7 @@ block0(v0: i64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -116,6 +191,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtsi2sdq %rdi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f9(i32x4) -> f64x2 {
 block0(v0: i32x4):
@@ -123,6 +207,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -130,6 +215,15 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvtdq2pd %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f10(i8, i16, i32, i64) -> f32 {
 block0(v0: i8, v1: i16, v2: i32, v3: i64):
@@ -143,6 +237,7 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
   return v10
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -159,6 +254,34 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dil, %r9
+;   cvtsi2ssq %r9, %xmm0
+;   movzwq %si, %r9
+;   cvtsi2ssq %r9, %xmm1
+;   movl %edx, %r9d
+;   cvtsi2ssq %r9, %xmm2
+;   cmpq $0, %rcx
+;   jl 0x32
+;   cvtsi2ssq %rcx, %xmm14
+;   jmp 0x4d
+;   movq %rcx, %r9
+;   shrq $1, %r9
+;   movq %rcx, %r10
+;   andq $1, %r10
+;   orq %r9, %r10
+;   cvtsi2ssq %r10, %xmm14
+;   addss %xmm14, %xmm14
+;   addss %xmm1, %xmm0
+;   addss %xmm2, %xmm0
+;   addss %xmm14, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f11(i32x4) -> f64x2 {
 block0(v0: i32x4):
@@ -167,6 +290,7 @@ block0(v0: i32x4):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -177,6 +301,32 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x14(%rip), %xmm2
+;   unpcklps %xmm2, %xmm0
+;   movdqu 0x19(%rip), %xmm6
+;   subpd %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   xorb %al, (%rbx)
+;   addb %dh, (%rax)
+;   addb %al, (%r8)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   xorb %al, (%rbx)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %dh, (%rax)
 
 function %f12(i32x4) -> f32x4 {
 block0(v0: i32x4):
@@ -184,6 +334,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -200,6 +351,24 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm3
+;   pslld $0x10, %xmm3
+;   psrld $0x10, %xmm3
+;   movdqa %xmm0, %xmm9
+;   psubd %xmm3, %xmm9
+;   cvtdq2ps %xmm3, %xmm8
+;   psrld $1, %xmm9
+;   cvtdq2ps %xmm9, %xmm0
+;   addps %xmm0, %xmm0
+;   addps %xmm8, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f13(f32) -> i32 {
 block0(v0: f32):
@@ -207,6 +376,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -214,6 +384,31 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x4f000000, %r8d
+;   movd %r8d, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x2f
+;   jnp 0x20
+;   ud2 ; trap: bad_toint
+;   cvttss2si %xmm0, %eax
+;   cmpl $0, %eax
+;   jge 0x4b
+;   ud2 ; trap: int_ovf
+;   movaps %xmm0, %xmm4
+;   subss %xmm3, %xmm4
+;   cvttss2si %xmm4, %eax
+;   cmpl $0, %eax
+;   jge 0x45
+;   ud2 ; trap: int_ovf
+;   addl $0x80000000, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f14(f32) -> i64 {
 block0(v0: f32):
@@ -221,6 +416,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -228,6 +424,32 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x5f000000, %r8d
+;   movd %r8d, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x31
+;   jnp 0x20
+;   ud2 ; trap: bad_toint
+;   cvttss2si %xmm0, %rax
+;   cmpq $0, %rax
+;   jge 0x56
+;   ud2 ; trap: int_ovf
+;   movaps %xmm0, %xmm4
+;   subss %xmm3, %xmm4
+;   cvttss2si %xmm4, %rax
+;   cmpq $0, %rax
+;   jge 0x49
+;   ud2 ; trap: int_ovf
+;   movabsq $9223372036854775808, %r8
+;   addq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f15(f64) -> i32 {
 block0(v0: f64):
@@ -235,6 +457,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -242,6 +465,31 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x41e0000000000000, %r8
+;   movq %r8, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   jae 0x34
+;   jnp 0x25
+;   ud2 ; trap: bad_toint
+;   cvttsd2si %xmm0, %eax
+;   cmpl $0, %eax
+;   jge 0x50
+;   ud2 ; trap: int_ovf
+;   movaps %xmm0, %xmm4
+;   subsd %xmm3, %xmm4
+;   cvttsd2si %xmm4, %eax
+;   cmpl $0, %eax
+;   jge 0x4a
+;   ud2 ; trap: int_ovf
+;   addl $0x80000000, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f16(f64) -> i64 {
 block0(v0: f64):
@@ -249,6 +497,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -256,6 +505,32 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x43e0000000000000, %r8
+;   movq %r8, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   jae 0x36
+;   jnp 0x25
+;   ud2 ; trap: bad_toint
+;   cvttsd2si %xmm0, %rax
+;   cmpq $0, %rax
+;   jge 0x5b
+;   ud2 ; trap: int_ovf
+;   movaps %xmm0, %xmm4
+;   subsd %xmm3, %xmm4
+;   cvttsd2si %xmm4, %rax
+;   cmpq $0, %rax
+;   jge 0x4e
+;   ud2 ; trap: int_ovf
+;   movabsq $9223372036854775808, %r8
+;   addq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f17(f32) -> i32 {
 block0(v0: f32):
@@ -263,6 +538,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -270,6 +546,34 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x4f000000, %r8d
+;   movd %r8d, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x39
+;   jnp 0x25
+;   xorl %eax, %eax
+;   jmp 0x5d
+;   cvttss2si %xmm0, %eax
+;   cmpl $0, %eax
+;   jge 0x5d
+;   xorl %eax, %eax
+;   jmp 0x5d
+;   movaps %xmm0, %xmm4
+;   subss %xmm3, %xmm4
+;   cvttss2si %xmm4, %eax
+;   cmpl $0, %eax
+;   jge 0x57
+;   movl $0xffffffff, %eax
+;   jmp 0x5d
+;   addl $0x80000000, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f18(f32) -> i64 {
 block0(v0: f32):
@@ -277,6 +581,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -284,6 +589,35 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x5f000000, %r8d
+;   movd %r8d, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x3d
+;   jnp 0x26
+;   xorq %rax, %rax
+;   jmp 0x6c
+;   cvttss2si %xmm0, %rax
+;   cmpq $0, %rax
+;   jge 0x6c
+;   xorq %rax, %rax
+;   jmp 0x6c
+;   movaps %xmm0, %xmm4
+;   subss %xmm3, %xmm4
+;   cvttss2si %xmm4, %rax
+;   cmpq $0, %rax
+;   jge 0x5f
+;   movq $18446744073709551615, %rax
+;   jmp 0x6c
+;   movabsq $9223372036854775808, %r8
+;   addq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f19(f64) -> i32 {
 block0(v0: f64):
@@ -291,6 +625,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -298,6 +633,34 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x41e0000000000000, %r8
+;   movq %r8, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   jae 0x3e
+;   jnp 0x2a
+;   xorl %eax, %eax
+;   jmp 0x62
+;   cvttsd2si %xmm0, %eax
+;   cmpl $0, %eax
+;   jge 0x62
+;   xorl %eax, %eax
+;   jmp 0x62
+;   movaps %xmm0, %xmm4
+;   subsd %xmm3, %xmm4
+;   cvttsd2si %xmm4, %eax
+;   cmpl $0, %eax
+;   jge 0x5c
+;   movl $0xffffffff, %eax
+;   jmp 0x62
+;   addl $0x80000000, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f20(f64) -> i64 {
 block0(v0: f64):
@@ -305,6 +668,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -312,6 +676,35 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x43e0000000000000, %r8
+;   movq %r8, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   jae 0x42
+;   jnp 0x2b
+;   xorq %rax, %rax
+;   jmp 0x71
+;   cvttsd2si %xmm0, %rax
+;   cmpq $0, %rax
+;   jge 0x71
+;   xorq %rax, %rax
+;   jmp 0x71
+;   movaps %xmm0, %xmm4
+;   subsd %xmm3, %xmm4
+;   cvttsd2si %xmm4, %rax
+;   cmpq $0, %rax
+;   jge 0x64
+;   movq $18446744073709551615, %rax
+;   jmp 0x71
+;   movabsq $9223372036854775808, %r8
+;   addq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f21(f32) -> i32 {
 block0(v0: f32):
@@ -319,6 +712,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -326,6 +720,29 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttss2si %xmm0, %eax
+;   cmpl $1, %eax
+;   jno 0x3f
+;   ucomiss %xmm0, %xmm0
+;   jnp 0x1c
+;   ud2 ; trap: bad_toint
+;   movl $0xcf000000, %edx
+;   movd %edx, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x30
+;   ud2 ; trap: int_ovf
+;   xorpd %xmm3, %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jae 0x3f
+;   ud2 ; trap: int_ovf
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f22(f32) -> i64 {
 block0(v0: f32):
@@ -333,6 +750,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -340,6 +758,29 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttss2si %xmm0, %rax
+;   cmpq $1, %rax
+;   jno 0x41
+;   ucomiss %xmm0, %xmm0
+;   jnp 0x1e
+;   ud2 ; trap: bad_toint
+;   movl $0xdf000000, %edx
+;   movd %edx, %xmm3
+;   ucomiss %xmm3, %xmm0
+;   jae 0x32
+;   ud2 ; trap: int_ovf
+;   xorpd %xmm3, %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jae 0x41
+;   ud2 ; trap: int_ovf
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f23(f64) -> i32 {
 block0(v0: f64):
@@ -347,6 +788,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -354,6 +796,29 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttsd2si %xmm0, %eax
+;   cmpl $1, %eax
+;   jno 0x48
+;   ucomisd %xmm0, %xmm0
+;   jnp 0x1d
+;   ud2 ; trap: bad_toint
+;   movabsq $13970166044105375744, %rdx
+;   movq %rdx, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   ja 0x38
+;   ud2 ; trap: int_ovf
+;   xorpd %xmm3, %xmm3
+;   ucomisd %xmm0, %xmm3
+;   jae 0x48
+;   ud2 ; trap: int_ovf
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f24(f64) -> i64 {
 block0(v0: f64):
@@ -361,6 +826,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -368,6 +834,29 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttsd2si %xmm0, %rax
+;   cmpq $1, %rax
+;   jno 0x4a
+;   ucomisd %xmm0, %xmm0
+;   jnp 0x1f
+;   ud2 ; trap: bad_toint
+;   movabsq $14114281232179134464, %rdx
+;   movq %rdx, %xmm3
+;   ucomisd %xmm3, %xmm0
+;   jae 0x3a
+;   ud2 ; trap: int_ovf
+;   xorpd %xmm3, %xmm3
+;   ucomisd %xmm0, %xmm3
+;   jae 0x4a
+;   ud2 ; trap: int_ovf
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f25(f32) -> i32 {
 block0(v0: f32):
@@ -375,6 +864,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -382,6 +872,25 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttss2si %xmm0, %eax
+;   cmpl $1, %eax
+;   jno 0x33
+;   ucomiss %xmm0, %xmm0
+;   jnp 0x21
+;   xorl %eax, %eax
+;   jmp 0x33
+;   xorpd %xmm3, %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jae 0x33
+;   movl $0x7fffffff, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f26(f32) -> i64 {
 block0(v0: f32):
@@ -389,6 +898,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -396,6 +906,25 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttss2si %xmm0, %rax
+;   cmpq $1, %rax
+;   jno 0x3b
+;   ucomiss %xmm0, %xmm0
+;   jnp 0x24
+;   xorq %rax, %rax
+;   jmp 0x3b
+;   xorpd %xmm3, %xmm3
+;   ucomiss %xmm0, %xmm3
+;   jae 0x3b
+;   movabsq $0x7fffffffffffffff, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f27(f64) -> i32 {
 block0(v0: f64):
@@ -403,6 +932,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -410,6 +940,25 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttsd2si %xmm0, %eax
+;   cmpl $1, %eax
+;   jno 0x35
+;   ucomisd %xmm0, %xmm0
+;   jnp 0x22
+;   xorl %eax, %eax
+;   jmp 0x35
+;   xorpd %xmm3, %xmm3
+;   ucomisd %xmm0, %xmm3
+;   jae 0x35
+;   movl $0x7fffffff, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f28(f64) -> i64 {
 block0(v0: f64):
@@ -417,6 +966,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -424,6 +974,25 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cvttsd2si %xmm0, %rax
+;   cmpq $1, %rax
+;   jno 0x3d
+;   ucomisd %xmm0, %xmm0
+;   jnp 0x25
+;   xorq %rax, %rax
+;   jmp 0x3d
+;   xorpd %xmm3, %xmm3
+;   ucomisd %xmm0, %xmm3
+;   jae 0x3d
+;   movabsq $0x7fffffffffffffff, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f29(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -431,6 +1000,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -451,6 +1021,28 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pxor %xmm2, %xmm2
+;   movdqa %xmm0, %xmm9
+;   maxps %xmm2, %xmm9
+;   pcmpeqd %xmm7, %xmm7
+;   psrld $1, %xmm7
+;   cvtdq2ps %xmm7, %xmm13
+;   cvttps2dq %xmm9, %xmm12
+;   subps %xmm13, %xmm9
+;   cmpleps %xmm9, %xmm13
+;   cvttps2dq %xmm9, %xmm0
+;   pxor %xmm13, %xmm0
+;   pxor %xmm6, %xmm6
+;   pmaxsd %xmm6, %xmm0
+;   paddd %xmm12, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f30(f32x4) -> i32x4 {
 block0(v0: f32x4):
@@ -458,6 +1050,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -474,4 +1067,22 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm4
+;   cmpeqps %xmm0, %xmm4
+;   movdqa %xmm0, %xmm5
+;   andps %xmm4, %xmm5
+;   pxor %xmm5, %xmm4
+;   cvttps2dq %xmm5, %xmm8
+;   movdqa %xmm8, %xmm0
+;   pand %xmm4, %xmm0
+;   psrad $0x1f, %xmm0
+;   pxor %xmm8, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/floating-point.clif b/cranelift/filetests/filetests/isa/x64/floating-point.clif
index b0ec687594..02ce7b853e 100644
--- a/cranelift/filetests/filetests/isa/x64/floating-point.clif
+++ b/cranelift/filetests/filetests/isa/x64/floating-point.clif
@@ -7,6 +7,7 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x7fffffffffffffff, %rax
+;   movq %rax, %xmm4
+;   andpd %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f(i64) -> f64 {
 block0(v0: i64):
@@ -24,6 +36,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -34,4 +47,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsd (%rdi), %xmm0 ; trap: heap_oob
+;   movabsq $0x7fffffffffffffff, %rcx
+;   movq %rcx, %xmm5
+;   andpd %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/floor-libcall.clif b/cranelift/filetests/filetests/isa/x64/floor-libcall.clif
index 6cc482baa6..4753232aab 100644
--- a/cranelift/filetests/filetests/isa/x64/floor-libcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/floor-libcall.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %FloorF32 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -22,6 +33,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +42,14 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %FloorF64 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/floor.clif b/cranelift/filetests/filetests/isa/x64/floor.clif
index e27004f6f2..173a92197d 100644
--- a/cranelift/filetests/filetests/isa/x64/floor.clif
+++ b/cranelift/filetests/filetests/isa/x64/floor.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundss $1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -21,6 +31,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundsd $1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -35,6 +55,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundps $1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -49,6 +79,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,4 +87,13 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundpd $1, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fma-call.clif b/cranelift/filetests/filetests/isa/x64/fma-call.clif
index d6ef54022c..3ab3b3a805 100644
--- a/cranelift/filetests/filetests/isa/x64/fma-call.clif
+++ b/cranelift/filetests/filetests/isa/x64/fma-call.clif
@@ -7,6 +7,7 @@ block0(v0: f32, v1: f32, v2: f32):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: f32, v1: f32, v2: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %r8 ; reloc_external Abs8 %FmaF32 0
+;   callq *%r8
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %fma_f64(f64, f64, f64) -> f64 {
 block0(v0: f64, v1: f64, v2: f64):
@@ -22,6 +33,7 @@ block0(v0: f64, v1: f64, v2: f64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +42,14 @@ block0(v0: f64, v1: f64, v2: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %r8 ; reloc_external Abs8 %FmaF64 0
+;   callq *%r8
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fma-inst.clif b/cranelift/filetests/filetests/isa/x64/fma-inst.clif
index dd8b40081a..aa90421a28 100644
--- a/cranelift/filetests/filetests/isa/x64/fma-inst.clif
+++ b/cranelift/filetests/filetests/isa/x64/fma-inst.clif
@@ -7,6 +7,7 @@ block0(v0: f32, v1: f32, v2: f32):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32, v1: f32, v2: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   vfmadd213ss %xmm2, %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %fma_f64(f64, f64, f64) -> f64 {
 block0(v0: f64, v1: f64, v2: f64):
@@ -21,6 +31,7 @@ block0(v0: f64, v1: f64, v2: f64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,4 +39,13 @@ block0(v0: f64, v1: f64, v2: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   vfmadd213sd %xmm2, %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fneg.clif b/cranelift/filetests/filetests/isa/x64/fneg.clif
index 7af500eb4f..90da792850 100644
--- a/cranelift/filetests/filetests/isa/x64/fneg.clif
+++ b/cranelift/filetests/filetests/isa/x64/fneg.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x80000000, %eax
+;   movd %eax, %xmm4
+;   xorps %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -23,6 +35,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $9223372036854775808, %rax
+;   movq %rax, %xmm4
+;   xorpd %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -39,6 +63,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +73,17 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm3, %xmm3
+;   pslld $0x1f, %xmm3
+;   xorps %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -55,6 +91,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,4 +101,15 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm3, %xmm3
+;   psllq $0x3f, %xmm3
+;   xorpd %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif b/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif
index a443691eeb..b129c8bf83 100644
--- a/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif
+++ b/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif
@@ -8,6 +8,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,15 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rbp, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sp() -> i64 {
 block0:
@@ -22,6 +32,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -29,6 +40,15 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsp, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %return_address() -> i64 {
 block0:
@@ -36,6 +56,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -44,4 +65,14 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rbp, %rsi
+;   movq 8(%rsi), %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/i128.clif b/cranelift/filetests/filetests/isa/x64/i128.clif
index 37d05b2b8c..62346303ea 100644
--- a/cranelift/filetests/filetests/isa/x64/i128.clif
+++ b/cranelift/filetests/filetests/isa/x64/i128.clif
@@ -8,6 +8,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -18,6 +19,18 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addq %rdx, %rax
+;   movq %rsi, %rdx
+;   adcq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -25,6 +38,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -35,6 +49,18 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   subq %rdx, %rax
+;   movq %rsi, %rdx
+;   sbbq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -42,6 +68,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -52,6 +79,18 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   andq %rdx, %rax
+;   movq %rsi, %rdx
+;   andq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -59,6 +98,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -69,6 +109,18 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   orq %rdx, %rax
+;   movq %rsi, %rdx
+;   orq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -76,6 +128,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -86,6 +139,18 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorq %rdx, %rax
+;   movq %rsi, %rdx
+;   xorq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i128) -> i128 {
 block0(v0: i128):
@@ -93,6 +158,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -103,6 +169,18 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   notq %rax
+;   movq %rsi, %rdx
+;   notq %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -110,6 +188,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -129,6 +208,27 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rax
+;   movq %rdi, %rdx
+;   imulq %rcx, %rdx
+;   movq %rax, %rcx
+;   movq %rdi, %rax
+;   movq %rsi, %r10
+;   imulq %rcx, %r10
+;   addq %r10, %rdx
+;   movq %rdx, %r9
+;   mulq %rcx
+;   movq %rdx, %rcx
+;   movq %r9, %rdx
+;   addq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i64, i64) -> i128 {
 block0(v0: i64, v1: i64):
@@ -136,6 +236,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -144,6 +245,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rdx
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f8(i128) -> i64, i64 {
 block0(v0: i128):
@@ -151,6 +262,7 @@ block0(v0: i128):
     return v1, v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -159,6 +271,16 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rdx
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f9(i128, i128) -> i8 {
 block0(v0: i128, v1: i128):
@@ -184,6 +306,7 @@ block0(v0: i128, v1: i128):
     return v20
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $64, %rsp
@@ -299,6 +422,123 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x40, %rsp
+;   movq %rbx, 0x10(%rsp)
+;   movq %r12, 0x18(%rsp)
+;   movq %r13, 0x20(%rsp)
+;   movq %r14, 0x28(%rsp)
+;   movq %r15, 0x30(%rsp)
+; block0: ; offset 0x21
+;   cmpq %rdx, %rdi
+;   sete %r9b
+;   cmpq %rcx, %rsi
+;   sete %r10b
+;   andq %r10, %r9
+;   testq $1, %r9
+;   setne %al
+;   cmpq %rdx, %rdi
+;   setne %r8b
+;   cmpq %rcx, %rsi
+;   setne %r9b
+;   orq %r9, %r8
+;   testq $1, %r8
+;   setne %r9b
+;   movq %r9, (%rsp)
+;   cmpq %rcx, %rsi
+;   setl %r8b
+;   sete %r10b
+;   cmpq %rdx, %rdi
+;   setb %r11b
+;   andq %r11, %r10
+;   orq %r10, %r8
+;   testq $1, %r8
+;   setne %r10b
+;   cmpq %rcx, %rsi
+;   setl %r11b
+;   sete %r8b
+;   cmpq %rdx, %rdi
+;   setbe %r15b
+;   andq %r15, %r8
+;   orq %r8, %r11
+;   testq $1, %r11
+;   setne %r8b
+;   cmpq %rcx, %rsi
+;   setg %r11b
+;   sete %r12b
+;   cmpq %rdx, %rdi
+;   seta %r13b
+;   andq %r13, %r12
+;   orq %r12, %r11
+;   testq $1, %r11
+;   setne %r11b
+;   cmpq %rcx, %rsi
+;   setg %r15b
+;   sete %bl
+;   cmpq %rdx, %rdi
+;   setae %r12b
+;   andq %r12, %rbx
+;   orq %rbx, %r15
+;   testq $1, %r15
+;   setne %r13b
+;   cmpq %rcx, %rsi
+;   setb %r14b
+;   sete %r15b
+;   cmpq %rdx, %rdi
+;   setb %bl
+;   andq %rbx, %r15
+;   orq %r15, %r14
+;   testq $1, %r14
+;   setne %r14b
+;   cmpq %rcx, %rsi
+;   setb %bl
+;   sete %r12b
+;   cmpq %rdx, %rdi
+;   setbe %r15b
+;   andq %r15, %r12
+;   orq %r12, %rbx
+;   testq $1, %rbx
+;   setne %r15b
+;   cmpq %rcx, %rsi
+;   seta %bl
+;   sete %r12b
+;   cmpq %rdx, %rdi
+;   seta %r9b
+;   andq %r9, %r12
+;   orq %r12, %rbx
+;   testq $1, %rbx
+;   setne %bl
+;   cmpq %rcx, %rsi
+;   seta %sil
+;   sete %cl
+;   cmpq %rdx, %rdi
+;   setae %dil
+;   andq %rdi, %rcx
+;   orq %rcx, %rsi
+;   testq $1, %rsi
+;   setne %sil
+;   movq (%rsp), %rcx
+;   andl %ecx, %eax
+;   andl %r8d, %r10d
+;   andl %r13d, %r11d
+;   andl %r15d, %r14d
+;   andl %esi, %ebx
+;   andl %r10d, %eax
+;   andl %r14d, %r11d
+;   andl %r11d, %eax
+;   andl %ebx, %eax
+;   movq 0x10(%rsp), %rbx
+;   movq 0x18(%rsp), %r12
+;   movq 0x20(%rsp), %r13
+;   movq 0x28(%rsp), %r14
+;   movq 0x30(%rsp), %r15
+;   addq $0x40, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f10(i128) -> i32 {
 block0(v0: i128):
@@ -313,6 +553,7 @@ block2:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -332,6 +573,27 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpq $0, %rdi
+;   sete %r9b
+;   cmpq $0, %rsi
+;   sete %sil
+;   testb %r9b, %sil
+;   jne 0x27
+; block1: ; offset 0x1d
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x27
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f11(i128) -> i32 {
 block0(v0: i128):
@@ -346,6 +608,7 @@ block2:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -365,6 +628,27 @@ block2:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpq $0, %rdi
+;   sete %r9b
+;   cmpq $0, %rsi
+;   sete %sil
+;   testb %r9b, %sil
+;   jne 0x27
+; block1: ; offset 0x1d
+;   movl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x27
+;   movl $2, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f12(i64) -> i128 {
 block0(v0: i64):
@@ -372,6 +656,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -380,6 +665,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f13(i64) -> i128 {
 block0(v0: i64):
@@ -387,6 +682,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -396,6 +692,17 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rdx
+;   sarq $0x3f, %rdx
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f14(i8) -> i128 {
 block0(v0: i8):
@@ -403,6 +710,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -412,6 +720,17 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsbq %dil, %rax
+;   movq %rax, %rdx
+;   sarq $0x3f, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f15(i8) -> i128 {
 block0(v0: i8):
@@ -419,6 +738,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -427,6 +747,16 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dil, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f16(i128) -> i64 {
 block0(v0: i128):
@@ -434,6 +764,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -441,6 +772,15 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f17(i128) -> i8 {
 block0(v0: i128):
@@ -448,6 +788,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -455,6 +796,15 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f18(i8) -> i128 {
 block0(v0: i8):
@@ -462,6 +812,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -470,6 +821,16 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dil, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f19(i128) -> i128 {
 block0(v0: i128):
@@ -477,6 +838,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -525,6 +887,56 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrq $1, %rax
+;   movabsq $0x7777777777777777, %r8
+;   andq %r8, %rax
+;   movq %rdi, %r9
+;   subq %rax, %r9
+;   shrq $1, %rax
+;   andq %r8, %rax
+;   subq %rax, %r9
+;   shrq $1, %rax
+;   andq %r8, %rax
+;   subq %rax, %r9
+;   movq %r9, %rax
+;   shrq $4, %rax
+;   addq %r9, %rax
+;   movabsq $0xf0f0f0f0f0f0f0f, %rdi
+;   andq %rdi, %rax
+;   movabsq $0x101010101010101, %rdx
+;   imulq %rdx, %rax
+;   shrq $0x38, %rax
+;   movq %rsi, %rdi
+;   shrq $1, %rdi
+;   movabsq $0x7777777777777777, %rcx
+;   andq %rcx, %rdi
+;   movq %rsi, %rdx
+;   subq %rdi, %rdx
+;   shrq $1, %rdi
+;   andq %rcx, %rdi
+;   subq %rdi, %rdx
+;   shrq $1, %rdi
+;   andq %rcx, %rdi
+;   subq %rdi, %rdx
+;   movq %rdx, %rsi
+;   shrq $4, %rsi
+;   addq %rdx, %rsi
+;   movabsq $0xf0f0f0f0f0f0f0f, %r10
+;   andq %r10, %rsi
+;   movabsq $0x101010101010101, %rcx
+;   imulq %rcx, %rsi
+;   shrq $0x38, %rsi
+;   addq %rsi, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f20(i128) -> i128 {
 block0(v0: i128):
@@ -532,6 +944,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -622,6 +1035,98 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0x5555555555555555, %rcx
+;   movq %rsi, %rdx
+;   andq %rcx, %rdx
+;   movq %rsi, %r11
+;   shrq $1, %r11
+;   andq %rcx, %r11
+;   shlq $1, %rdx
+;   orq %r11, %rdx
+;   movabsq $0x3333333333333333, %r9
+;   movq %rdx, %r10
+;   andq %r9, %r10
+;   shrq $2, %rdx
+;   andq %r9, %rdx
+;   shlq $2, %r10
+;   orq %rdx, %r10
+;   movabsq $0xf0f0f0f0f0f0f0f, %rsi
+;   movq %r10, %rax
+;   andq %rsi, %rax
+;   shrq $4, %r10
+;   andq %rsi, %r10
+;   shlq $4, %rax
+;   orq %r10, %rax
+;   movabsq $0xff00ff00ff00ff, %rcx
+;   movq %rax, %rdx
+;   andq %rcx, %rdx
+;   shrq $8, %rax
+;   andq %rcx, %rax
+;   shlq $8, %rdx
+;   orq %rax, %rdx
+;   movabsq $0xffff0000ffff, %r10
+;   movq %rdx, %r9
+;   andq %r10, %r9
+;   shrq $0x10, %rdx
+;   andq %r10, %rdx
+;   shlq $0x10, %r9
+;   orq %rdx, %r9
+;   movabsq $0xffffffff, %rsi
+;   movq %r9, %rax
+;   andq %rsi, %rax
+;   shrq $0x20, %r9
+;   shlq $0x20, %rax
+;   orq %r9, %rax
+;   movabsq $0x5555555555555555, %rdx
+;   movq %rdi, %rcx
+;   andq %rdx, %rcx
+;   movq %rdi, %r9
+;   shrq $1, %r9
+;   andq %rdx, %r9
+;   shlq $1, %rcx
+;   orq %r9, %rcx
+;   movabsq $0x3333333333333333, %rdx
+;   movq %rcx, %r8
+;   andq %rdx, %r8
+;   shrq $2, %rcx
+;   andq %rdx, %rcx
+;   shlq $2, %r8
+;   orq %rcx, %r8
+;   movabsq $0xf0f0f0f0f0f0f0f, %r10
+;   movq %r8, %r11
+;   andq %r10, %r11
+;   shrq $4, %r8
+;   andq %r10, %r8
+;   shlq $4, %r11
+;   orq %r8, %r11
+;   movabsq $0xff00ff00ff00ff, %rdi
+;   movq %r11, %rcx
+;   andq %rdi, %rcx
+;   shrq $8, %r11
+;   andq %rdi, %r11
+;   shlq $8, %rcx
+;   orq %r11, %rcx
+;   movabsq $0xffff0000ffff, %rdx
+;   movq %rcx, %r8
+;   andq %rdx, %r8
+;   shrq $0x10, %rcx
+;   andq %rdx, %rcx
+;   shlq $0x10, %r8
+;   orq %rcx, %r8
+;   movabsq $0xffffffff, %r10
+;   movq %r8, %rdx
+;   andq %r10, %rdx
+;   shrq $0x20, %r8
+;   shlq $0x20, %rdx
+;   orq %r8, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f21(i128, i64) {
 block0(v0: i128, v1: i64):
@@ -629,6 +1134,7 @@ block0(v0: i128, v1: i64):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -637,6 +1143,16 @@ block0(v0: i128, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, (%rdx) ; trap: heap_oob
+;   movq %rsi, 8(%rdx) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f22(i64) -> i128 {
 block0(v0: i64):
@@ -644,6 +1160,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -652,6 +1169,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rdi), %rax ; trap: heap_oob
+;   movq 8(%rdi), %rdx ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f23(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -672,6 +1199,7 @@ block2(v8: i128):
     return v11
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -697,6 +1225,33 @@ block2(v8: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorq %rax, %rax
+;   xorq %r9, %r9
+;   testb %dl, %dl
+;   je 0x29
+; block1: ; offset 0x12
+;   movl $1, %r8d
+;   xorq %r10, %r10
+;   addq %r8, %rax
+;   movq %r9, %rdx
+;   adcq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x29
+;   movq %r9, %rdx
+;   movl $2, %r9d
+;   xorq %r11, %r11
+;   addq %r9, %rax
+;   adcq %r11, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f24(i128, i128, i64, i128, i128, i128) -> i128 {
 
@@ -710,6 +1265,7 @@ block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128):
     return v11
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $32, %rsp
@@ -750,6 +1306,48 @@ block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x20, %rsp
+;   movq %rbx, (%rsp)
+;   movq %r12, 8(%rsp)
+;   movq %r14, 0x10(%rsp)
+;   movq %r15, 0x18(%rsp)
+; block0: ; offset 0x1b
+;   movq %r8, %r14
+;   movq %rcx, %rbx
+;   movq %rdx, %rcx
+;   movq 0x10(%rbp), %r15
+;   movq 0x18(%rbp), %rax
+;   movq 0x20(%rbp), %rdx
+;   movq 0x28(%rbp), %r11
+;   movq 0x30(%rbp), %r10
+;   movq %rdi, %r8
+;   addq %rcx, %r8
+;   movq %rbx, %rdi
+;   movq %rsi, %rcx
+;   adcq %rdi, %rcx
+;   xorq %rdi, %rdi
+;   movq %r14, %r12
+;   movq %r9, %rsi
+;   addq %r12, %rsi
+;   adcq %rdi, %r15
+;   addq %r11, %rax
+;   adcq %r10, %rdx
+;   addq %rsi, %r8
+;   adcq %r15, %rcx
+;   addq %r8, %rax
+;   adcq %rcx, %rdx
+;   movq (%rsp), %rbx
+;   movq 8(%rsp), %r12
+;   movq 0x10(%rsp), %r14
+;   movq 0x18(%rsp), %r15
+;   addq $0x20, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f25(i128) -> i128, i128, i128, i64, i128, i128 {
 block0(v0: i128):
@@ -757,6 +1355,7 @@ block0(v0: i128):
     return v0, v0, v0, v1, v0, v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -774,6 +1373,25 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, (%rdx)
+;   movq %rsi, 8(%rdx)
+;   movq %rdi, 0x10(%rdx)
+;   movq %rsi, 0x18(%rdx)
+;   movq %rdi, 0x20(%rdx)
+;   movq %rdi, 0x28(%rdx)
+;   movq %rsi, 0x30(%rdx)
+;   movq %rdi, 0x38(%rdx)
+;   movq %rdi, %rax
+;   movq %rsi, 0x40(%rdx)
+;   movq %rsi, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f26(i128, i128) -> i128, i128 {
     fn0 = %g(i128, i128) -> i128, i128
@@ -782,6 +1400,7 @@ block0(v0: i128, v1: i128):
     return v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -805,6 +1424,29 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r13, (%rsp)
+; block0: ; offset 0xc
+;   movq %r8, %r13
+;   subq $0x10, %rsp
+;   leaq (%rsp), %r8
+;   movabsq $0, %r9 ; reloc_external Abs8 %g 0
+;   callq *%r9
+;   movq (%rsp), %r8
+;   movq 8(%rsp), %r9
+;   addq $0x10, %rsp
+;   movq %r13, %rcx
+;   movq %r8, (%rcx)
+;   movq %r9, 8(%rcx)
+;   movq (%rsp), %r13
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f27(i128) -> i128 {
 block0(v0: i128):
@@ -812,6 +1454,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -833,6 +1476,29 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %r8
+;   movq $18446744073709551615, %rcx
+;   bsrq %rsi, %r9
+;   cmoveq %rcx, %r9
+;   movl $0x3f, %edi
+;   subq %r9, %rdi
+;   movq $18446744073709551615, %rdx
+;   bsrq %r8, %r10
+;   cmoveq %rdx, %r10
+;   movl $0x3f, %eax
+;   subq %r10, %rax
+;   addq $0x40, %rax
+;   cmpq $0x40, %rdi
+;   cmovneq %rdi, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f28(i128) -> i128 {
 block0(v0: i128):
@@ -840,6 +1506,7 @@ block0(v0: i128):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -856,6 +1523,24 @@ block0(v0: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0x40, %ecx
+;   bsfq %rdi, %rax
+;   cmoveq %rcx, %rax
+;   movl $0x40, %edi
+;   bsfq %rsi, %rdx
+;   cmoveq %rdi, %rdx
+;   addq $0x40, %rdx
+;   cmpq $0x40, %rax
+;   cmoveq %rdx, %rax
+;   xorq %rdx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f29(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -863,6 +1548,7 @@ block0(v0: i8, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -873,6 +1559,18 @@ block0(v0: i8, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f30(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -880,6 +1578,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -904,6 +1603,32 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   movq %rcx, %r10
+;   movl $0x40, %ecx
+;   movq %r10, %r8
+;   subq %r8, %rcx
+;   movq %rdi, %r10
+;   shrq %cl, %r10
+;   xorq %rax, %rax
+;   testq $0x7f, %r8
+;   cmoveq %rax, %r10
+;   orq %r11, %r10
+;   testq $0x40, %r8
+;   cmoveq %rdx, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f31(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -911,6 +1636,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -935,6 +1661,32 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r10
+;   shrq %cl, %r10
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r11
+;   orq %r8, %r11
+;   testq $0x40, %rdi
+;   movq %r10, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f32(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -942,6 +1694,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -968,6 +1721,34 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r10
+;   sarq %cl, %r10
+;   movl $0x40, %ecx
+;   movq %rdx, %rax
+;   subq %rax, %rcx
+;   movq %rsi, %r9
+;   shlq %cl, %r9
+;   xorq %r11, %r11
+;   testq $0x7f, %rax
+;   cmoveq %r11, %r9
+;   orq %r9, %r8
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rax
+;   movq %r10, %rax
+;   cmoveq %r8, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f33(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -975,6 +1756,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -1021,6 +1803,54 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   movq %rcx, %r8
+;   movl $0x40, %ecx
+;   subq %r8, %rcx
+;   movq %rdi, %r10
+;   shrq %cl, %r10
+;   xorq %rax, %rax
+;   testq $0x7f, %r8
+;   cmoveq %rax, %r10
+;   orq %r11, %r10
+;   testq $0x40, %r8
+;   cmoveq %rdx, %rax
+;   cmoveq %r10, %rdx
+;   movl $0x80, %ecx
+;   movq %r8, %r10
+;   subq %r10, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r9
+;   shrq %cl, %r9
+;   movq %rcx, %r10
+;   movl $0x40, %ecx
+;   movq %r10, %r11
+;   subq %r11, %rcx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   xorq %rsi, %rsi
+;   testq $0x7f, %r11
+;   cmoveq %rsi, %r10
+;   orq %r8, %r10
+;   testq $0x40, %r11
+;   movq %r9, %r8
+;   cmoveq %r10, %r8
+;   cmoveq %r9, %rsi
+;   orq %r8, %rax
+;   orq %rsi, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f34(i128, i128) -> i128 {
 block0(v0: i128, v1: i128):
@@ -1028,6 +1858,7 @@ block0(v0: i128, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -1075,4 +1906,53 @@ block0(v0: i128, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r10
+;   shrq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rax
+;   subq %rax, %rcx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rax
+;   cmoveq %rdx, %r11
+;   orq %r8, %r11
+;   testq $0x40, %rax
+;   movq %r10, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r10, %rdx
+;   movl $0x80, %ecx
+;   movq %r9, %r10
+;   subq %r10, %rcx
+;   movq %rdi, %r8
+;   shlq %cl, %r8
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rsi
+;   subq %rsi, %rcx
+;   movq %rdi, %r9
+;   shrq %cl, %r9
+;   xorq %r11, %r11
+;   testq $0x7f, %rsi
+;   cmoveq %r11, %r9
+;   orq %r10, %r9
+;   testq $0x40, %rsi
+;   cmoveq %r8, %r11
+;   cmoveq %r9, %r8
+;   orq %r11, %rax
+;   orq %r8, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/iabs.clif b/cranelift/filetests/filetests/isa/x64/iabs.clif
index 3c8b7f0bf9..02bea8d040 100644
--- a/cranelift/filetests/filetests/isa/x64/iabs.clif
+++ b/cranelift/filetests/filetests/isa/x64/iabs.clif
@@ -7,6 +7,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negb %al
+;   cmovsl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16) -> i16 {
 block0(v0: i16):
@@ -23,6 +35,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negw %ax
+;   cmovsl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32) -> i32 {
 block0(v0: i32):
@@ -39,6 +63,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +73,17 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negl %eax
+;   cmovsl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -55,6 +91,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,4 +101,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   negq %rax
+;   cmovsq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/immediates.clif b/cranelift/filetests/filetests/isa/x64/immediates.clif
index 9d394aed61..9283cd8bce 100644
--- a/cranelift/filetests/filetests/isa/x64/immediates.clif
+++ b/cranelift/filetests/filetests/isa/x64/immediates.clif
@@ -15,6 +15,7 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,4 +33,31 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %r9
+;   addq 0x32(%rip), %r9
+;   movq %r9, (%rsi) ; trap: heap_oob
+;   movq %rdi, %r10
+;   subq 0x25(%rip), %r10
+;   movq %r10, (%rsi) ; trap: heap_oob
+;   movq %rdi, %r11
+;   andq 0x18(%rip), %r11
+;   movq %r11, (%rsi) ; trap: heap_oob
+;   orq 0xe(%rip), %rdi
+;   movq %rdi, (%rsi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   int3
+;   int3
+;   fstp %st(5)
+;   outb %al, %dx
+;   outb %al, %dx
 
diff --git a/cranelift/filetests/filetests/isa/x64/inline-probestack-large.clif b/cranelift/filetests/filetests/isa/x64/inline-probestack-large.clif
index b5b592c653..57785bb04c 100644
--- a/cranelift/filetests/filetests/isa/x64/inline-probestack-large.clif
+++ b/cranelift/filetests/filetests/isa/x64/inline-probestack-large.clif
@@ -16,6 +16,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $8192, %rsp
@@ -25,6 +26,17 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x2000, %rsp
+; block0: ; offset 0xb
+;   leaq (%rsp), %rax
+;   addq $0x2000, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %unrolled() -> i64 system_v {
 ss0 = explicit_slot 196608
@@ -34,6 +46,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   movl    %esp, -65536(%rsp)
@@ -46,6 +59,20 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   movl %esp, -0x10000(%rsp)
+;   movl %esp, -0x20000(%rsp)
+;   movl %esp, -0x30000(%rsp)
+;   subq $0x30000, %rsp
+; block0: ; offset 0x20
+;   leaq (%rsp), %rax
+;   addq $0x30000, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %large() -> i64 system_v {
 ss0 = explicit_slot 2097152
@@ -55,6 +82,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   stack_probe_loop %r11, frame_size=2097152, guard_size=65536
@@ -65,3 +93,22 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   movq %rsp, %r11
+;   subq $0x200000, %r11
+;   subq $0x10000, %rsp
+;   movl %esp, (%rsp)
+;   cmpq %rsp, %r11
+;   jne 0xe
+;   addq $0x200000, %rsp
+;   subq $0x200000, %rsp
+; block0: ; offset 0x2f
+;   leaq (%rsp), %rax
+;   addq $0x200000, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/inline-probestack.clif b/cranelift/filetests/filetests/isa/x64/inline-probestack.clif
index aa37bede6f..ddb042ea2e 100644
--- a/cranelift/filetests/filetests/isa/x64/inline-probestack.clif
+++ b/cranelift/filetests/filetests/isa/x64/inline-probestack.clif
@@ -15,6 +15,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $2048, %rsp
@@ -24,6 +25,17 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x800, %rsp
+; block0: ; offset 0xb
+;   leaq (%rsp), %rax
+;   addq $0x800, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %unrolled() -> i64 system_v {
 ss0 = explicit_slot 12288
@@ -33,6 +45,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   movl    %esp, -4096(%rsp)
@@ -45,6 +58,20 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   movl %esp, -0x1000(%rsp)
+;   movl %esp, -0x2000(%rsp)
+;   movl %esp, -0x3000(%rsp)
+;   subq $0x3000, %rsp
+; block0: ; offset 0x20
+;   leaq (%rsp), %rax
+;   addq $0x3000, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %large() -> i64 system_v {
 ss0 = explicit_slot 100000
@@ -54,6 +81,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   stack_probe_loop %r11, frame_size=100000, guard_size=4096
@@ -64,3 +92,22 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   movq %rsp, %r11
+;   subq $0x19000, %r11
+;   subq $0x1000, %rsp
+;   movl %esp, (%rsp)
+;   cmpq %rsp, %r11
+;   jne 0xe
+;   addq $0x19000, %rsp
+;   subq $0x186a0, %rsp
+; block0: ; offset 0x2f
+;   leaq (%rsp), %rax
+;   addq $0x186a0, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
diff --git a/cranelift/filetests/filetests/isa/x64/ishl.clif b/cranelift/filetests/filetests/isa/x64/ishl.clif
index f162592975..04aa692a9b 100644
--- a/cranelift/filetests/filetests/isa/x64/ishl.clif
+++ b/cranelift/filetests/filetests/isa/x64/ishl.clif
@@ -14,6 +14,7 @@ block0(v0: i128, v1: i8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -38,6 +39,32 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dl, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %r8
+;   subq %r8, %rcx
+;   movq %rdi, %r10
+;   shrq %cl, %r10
+;   xorq %rax, %rax
+;   testq $0x7f, %r8
+;   cmoveq %rax, %r10
+;   orq %r11, %r10
+;   testq $0x40, %r8
+;   cmoveq %rdx, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i128_i64(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -45,6 +72,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -69,6 +97,32 @@ block0(v0: i128, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rsi
+;   subq %rsi, %rcx
+;   movq %rdi, %r9
+;   shrq %cl, %r9
+;   xorq %rax, %rax
+;   testq $0x7f, %rsi
+;   cmoveq %rax, %r9
+;   orq %r10, %r9
+;   testq $0x40, %rsi
+;   cmoveq %rdx, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i128_i32(i128, i32) -> i128 {
 block0(v0: i128, v1: i32):
@@ -76,6 +130,7 @@ block0(v0: i128, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -100,6 +155,32 @@ block0(v0: i128, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rsi
+;   subq %rsi, %rcx
+;   movq %rdi, %r9
+;   shrq %cl, %r9
+;   xorq %rax, %rax
+;   testq $0x7f, %rsi
+;   cmoveq %rax, %r9
+;   orq %r10, %r9
+;   testq $0x40, %rsi
+;   cmoveq %rdx, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i128_i16(i128, i16) -> i128 {
 block0(v0: i128, v1: i16):
@@ -107,6 +188,7 @@ block0(v0: i128, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -131,6 +213,32 @@ block0(v0: i128, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rsi
+;   subq %rsi, %rcx
+;   movq %rdi, %r9
+;   shrq %cl, %r9
+;   xorq %rax, %rax
+;   testq $0x7f, %rsi
+;   cmoveq %rax, %r9
+;   orq %r10, %r9
+;   testq $0x40, %rsi
+;   cmoveq %rdx, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -138,6 +246,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -162,6 +271,32 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %rdx
+;   shlq %cl, %rdx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rsi
+;   subq %rsi, %rcx
+;   movq %rdi, %r9
+;   shrq %cl, %r9
+;   xorq %rax, %rax
+;   testq $0x7f, %rsi
+;   cmoveq %rax, %r9
+;   orq %r10, %r9
+;   testq $0x40, %rsi
+;   cmoveq %rdx, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_i128(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -169,6 +304,7 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -178,6 +314,17 @@ block0(v0: i64, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shlq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_i128(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -185,6 +332,7 @@ block0(v0: i32, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -194,6 +342,17 @@ block0(v0: i32, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shll %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_i128(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -201,6 +360,7 @@ block0(v0: i16, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -211,6 +371,18 @@ block0(v0: i16, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shlw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_i128(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -218,6 +390,7 @@ block0(v0: i8, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -228,6 +401,18 @@ block0(v0: i8, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -235,6 +420,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -244,6 +430,17 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shlq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_i32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -251,6 +448,7 @@ block0(v0: i64, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -260,6 +458,17 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shlq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_i16(i64, i16) -> i64 {
 block0(v0: i64, v1: i16):
@@ -267,6 +476,7 @@ block0(v0: i64, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -276,6 +486,17 @@ block0(v0: i64, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shlq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_i8(i64, i8) -> i64 {
 block0(v0: i64, v1: i8):
@@ -283,6 +504,7 @@ block0(v0: i64, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -292,6 +514,17 @@ block0(v0: i64, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shlq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_i64(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -299,6 +532,7 @@ block0(v0: i32, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -308,6 +542,17 @@ block0(v0: i32, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shll %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -315,6 +560,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -324,6 +570,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shll %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_i16(i32, i16) -> i32 {
 block0(v0: i32, v1: i16):
@@ -331,6 +588,7 @@ block0(v0: i32, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -340,6 +598,17 @@ block0(v0: i32, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shll %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_i8(i32, i8) -> i32 {
 block0(v0: i32, v1: i8):
@@ -347,6 +616,7 @@ block0(v0: i32, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -356,6 +626,17 @@ block0(v0: i32, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shll %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_i64(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -363,6 +644,7 @@ block0(v0: i16, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -373,6 +655,18 @@ block0(v0: i16, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shlw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_i32(i16, i32) -> i16 {
 block0(v0: i16, v1: i32):
@@ -380,6 +674,7 @@ block0(v0: i16, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -390,6 +685,18 @@ block0(v0: i16, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shlw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -397,6 +704,7 @@ block0(v0: i16, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -407,6 +715,18 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shlw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_i8(i16, i8) -> i16 {
 block0(v0: i16, v1: i8):
@@ -414,6 +734,7 @@ block0(v0: i16, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -424,6 +745,18 @@ block0(v0: i16, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shlw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_i64(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -431,6 +764,7 @@ block0(v0: i8, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -441,6 +775,18 @@ block0(v0: i8, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_i32(i8, i32) -> i8 {
 block0(v0: i8, v1: i32):
@@ -448,6 +794,7 @@ block0(v0: i8, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -458,6 +805,18 @@ block0(v0: i8, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_i16(i8, i16) -> i8 {
 block0(v0: i8, v1: i16):
@@ -465,6 +824,7 @@ block0(v0: i8, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -475,6 +835,18 @@ block0(v0: i8, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -482,6 +854,7 @@ block0(v0: i8, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -492,6 +865,18 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shlb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i64_const(i64) -> i64 {
 block0(v0: i64):
@@ -499,6 +884,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -507,6 +893,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shlq $1, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i32_const(i32) -> i32 {
 block0(v0: i32):
@@ -514,6 +910,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -522,6 +919,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shll $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i16_const(i16) -> i16 {
 block0(v0: i16):
@@ -529,6 +936,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -537,6 +945,16 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shlw $1, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8_const(i8) -> i8 {
 block0(v0: i8):
@@ -544,6 +962,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -552,4 +971,14 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shlb $1, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/leaf.clif b/cranelift/filetests/filetests/isa/x64/leaf.clif
index b51148f972..b90c34b535 100644
--- a/cranelift/filetests/filetests/isa/x64/leaf.clif
+++ b/cranelift/filetests/filetests/isa/x64/leaf.clif
@@ -10,6 +10,7 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,4 +18,13 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/leaf_with_preserve_frame_pointers.clif b/cranelift/filetests/filetests/isa/x64/leaf_with_preserve_frame_pointers.clif
index f7aa76b742..c1ae3e7ed4 100644
--- a/cranelift/filetests/filetests/isa/x64/leaf_with_preserve_frame_pointers.clif
+++ b/cranelift/filetests/filetests/isa/x64/leaf_with_preserve_frame_pointers.clif
@@ -10,6 +10,7 @@ block0(v0: i64):
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,4 +18,13 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/load-op-store.clif b/cranelift/filetests/filetests/isa/x64/load-op-store.clif
index 54312e48ae..7fe8e95859 100644
--- a/cranelift/filetests/filetests/isa/x64/load-op-store.clif
+++ b/cranelift/filetests/filetests/isa/x64/load-op-store.clif
@@ -9,6 +9,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   addl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -25,6 +35,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +43,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   addl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -41,6 +61,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +69,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   subl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -57,6 +87,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,6 +95,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -73,6 +113,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -80,6 +121,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -89,6 +139,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -96,6 +147,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   orl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -105,6 +165,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -112,6 +173,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   orl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -121,6 +191,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -128,6 +199,15 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f8(i64, i32) {
 block0(v0: i64, v1: i32):
@@ -137,6 +217,7 @@ block0(v0: i64, v1: i32):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -144,4 +225,13 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorl %esi, 0x20(%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/load-op.clif b/cranelift/filetests/filetests/isa/x64/load-op.clif
index 030a0f1881..1ee29c3148 100644
--- a/cranelift/filetests/filetests/isa/x64/load-op.clif
+++ b/cranelift/filetests/filetests/isa/x64/load-op.clif
@@ -8,6 +8,7 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,16 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rax
+;   addl (%rdi), %eax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %add_from_mem_u32_2(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
@@ -24,6 +35,7 @@ block0(v0: i64, v1: i32):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +44,16 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rax
+;   addl (%rdi), %eax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %add_from_mem_u64_1(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -40,6 +62,7 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +71,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rax
+;   addq (%rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %add_from_mem_u64_2(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -56,6 +89,7 @@ block0(v0: i64, v1: i64):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,6 +98,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rax
+;   addq (%rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %add_from_mem_not_narrow(i64, i8) -> i8 {
 block0(v0: i64, v1: i8):
@@ -72,6 +116,7 @@ block0(v0: i64, v1: i8):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -80,6 +125,16 @@ block0(v0: i64, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq (%rdi), %rax ; trap: heap_oob
+;   addl %esi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %no_merge_if_lookback_use(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -90,6 +145,7 @@ block0(v0: i64, v1: i64):
   return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -101,6 +157,19 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rdi), %r8 ; trap: heap_oob
+;   movq %r8, %r9
+;   addq %rdi, %r9
+;   movq %r9, (%rsi) ; trap: heap_oob
+;   movq (%r8, %rdi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %merge_scalar_to_vector(i64) -> i32x4 {
 block0(v0: i64):
@@ -112,6 +181,7 @@ block1:
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -121,6 +191,16 @@ block1:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movss (%rdi), %xmm0 ; trap: heap_oob
+; block1: ; offset 0x8
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %cmp_mem(i64) -> i64 {
 block0(v0: i64):
@@ -130,6 +210,7 @@ block0(v0: i64):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -139,4 +220,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpq (%rdi), %rdi ; trap: heap_oob
+;   sete %dl
+;   movzbq %dl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/move-elision.clif b/cranelift/filetests/filetests/isa/x64/move-elision.clif
index f879653384..48cea6f7af 100644
--- a/cranelift/filetests/filetests/isa/x64/move-elision.clif
+++ b/cranelift/filetests/filetests/isa/x64/move-elision.clif
@@ -13,10 +13,19 @@ block0(v0: i32x4):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/narrowing.clif b/cranelift/filetests/filetests/isa/x64/narrowing.clif
index 62646deba8..2357bcb4c1 100644
--- a/cranelift/filetests/filetests/isa/x64/narrowing.clif
+++ b/cranelift/filetests/filetests/isa/x64/narrowing.clif
@@ -7,6 +7,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   packsswb %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -21,6 +31,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   packssdw %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(f64x2) -> i32x4 {
 block0(v0: f64x2):
@@ -37,6 +57,7 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -50,6 +71,25 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm4
+;   cmpeqpd %xmm0, %xmm4
+;   movupd 0x1b(%rip), %xmm5
+;   andps %xmm5, %xmm4
+;   movdqa %xmm0, %xmm8
+;   minpd %xmm4, %xmm8
+;   cvttpd2dq %xmm8, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   sarb $0xff, %bh
 
 function %f4(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):
@@ -57,6 +97,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,6 +105,15 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   packuswb %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i32x4, i32x4) -> i16x8 {
 block0(v0: i32x4, v1: i32x4):
@@ -71,6 +121,7 @@ block0(v0: i32x4, v1: i32x4):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -78,4 +129,13 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   packusdw %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif b/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif
index f4c656ab6b..8a5f0d9e1c 100644
--- a/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %NearestF32 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -22,6 +33,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +42,14 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %NearestF64 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/nearest.clif b/cranelift/filetests/filetests/isa/x64/nearest.clif
index 46ec50cf1f..b3e2a625ce 100644
--- a/cranelift/filetests/filetests/isa/x64/nearest.clif
+++ b/cranelift/filetests/filetests/isa/x64/nearest.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundss $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -21,6 +31,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundsd $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -35,6 +55,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundps $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -49,6 +79,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,4 +87,13 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundpd $0, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/pinned-reg.clif b/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
index 6588f16261..5f86e3abba 100644
--- a/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
+++ b/cranelift/filetests/filetests/isa/x64/pinned-reg.clif
@@ -10,6 +10,7 @@ block0:
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -19,6 +20,17 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %r15, %rsi
+;   addq $1, %rsi
+;   movq %rsi, %r15
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1() windows_fastcall {
 block0:
@@ -28,6 +40,7 @@ block0:
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -41,4 +54,19 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %rsi, (%rsp)
+; block0: ; offset 0xc
+;   movq %r15, %rsi
+;   addq $1, %rsi
+;   movq %rsi, %r15
+;   movq (%rsp), %rsi
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/popcnt-use-popcnt.clif b/cranelift/filetests/filetests/isa/x64/popcnt-use-popcnt.clif
index 09309733a9..f3fc404705 100644
--- a/cranelift/filetests/filetests/isa/x64/popcnt-use-popcnt.clif
+++ b/cranelift/filetests/filetests/isa/x64/popcnt-use-popcnt.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   popcntq %rdi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %popcnt(i32) -> i32 {
 block0(v0: i32):
@@ -21,6 +31,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,4 +39,13 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   popcntl %edi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/popcnt.clif b/cranelift/filetests/filetests/isa/x64/popcnt.clif
index 491be3077b..ee14b91573 100644
--- a/cranelift/filetests/filetests/isa/x64/popcnt.clif
+++ b/cranelift/filetests/filetests/isa/x64/popcnt.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -33,6 +34,34 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rcx
+;   shrq $1, %rdi
+;   movq %rcx, %r8
+;   movabsq $0x7777777777777777, %rdx
+;   andq %rdx, %rdi
+;   subq %rdi, %r8
+;   shrq $1, %rdi
+;   andq %rdx, %rdi
+;   subq %rdi, %r8
+;   shrq $1, %rdi
+;   andq %rdx, %rdi
+;   subq %rdi, %r8
+;   movq %r8, %rax
+;   shrq $4, %rax
+;   addq %r8, %rax
+;   movabsq $0xf0f0f0f0f0f0f0f, %r11
+;   andq %r11, %rax
+;   movabsq $0x101010101010101, %rcx
+;   imulq %rcx, %rax
+;   shrq $0x38, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %popcnt64load(i64) -> i64 {
 block0(v0: i64):
@@ -41,6 +70,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -67,6 +97,34 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq (%rdi), %rdx ; trap: heap_oob
+;   movq %rdx, %rcx
+;   shrq $1, %rcx
+;   movabsq $0x7777777777777777, %r8
+;   andq %r8, %rcx
+;   subq %rcx, %rdx
+;   shrq $1, %rcx
+;   andq %r8, %rcx
+;   subq %rcx, %rdx
+;   shrq $1, %rcx
+;   andq %r8, %rcx
+;   subq %rcx, %rdx
+;   movq %rdx, %rax
+;   shrq $4, %rax
+;   addq %rdx, %rax
+;   movabsq $0xf0f0f0f0f0f0f0f, %rsi
+;   andq %rsi, %rax
+;   movabsq $0x101010101010101, %rdx
+;   imulq %rdx, %rax
+;   shrq $0x38, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %popcnt32(i32) -> i32 {
 block0(v0: i32):
@@ -74,6 +132,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -98,6 +157,32 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrl $1, %edi
+;   movl $0x77777777, %edx
+;   andl %edx, %edi
+;   movq %rax, %r8
+;   subl %edi, %r8d
+;   shrl $1, %edi
+;   andl %edx, %edi
+;   subl %edi, %r8d
+;   shrl $1, %edi
+;   andl %edx, %edi
+;   subl %edi, %r8d
+;   movq %r8, %rax
+;   shrl $4, %eax
+;   addl %r8d, %eax
+;   andl $0xf0f0f0f, %eax
+;   imull $0x1010101, %eax, %eax
+;   shrl $0x18, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %popcnt32load(i64) -> i32 {
 block0(v0: i64):
@@ -106,6 +191,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -130,4 +216,30 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl (%rdi), %edx ; trap: heap_oob
+;   movq %rdx, %rcx
+;   shrl $1, %ecx
+;   movl $0x77777777, %r8d
+;   andl %r8d, %ecx
+;   subl %ecx, %edx
+;   shrl $1, %ecx
+;   andl %r8d, %ecx
+;   subl %ecx, %edx
+;   shrl $1, %ecx
+;   andl %r8d, %ecx
+;   subl %ecx, %edx
+;   movq %rdx, %rax
+;   shrl $4, %eax
+;   addl %edx, %eax
+;   andl $0xf0f0f0f, %eax
+;   imull $0x1010101, %eax, %eax
+;   shrl $0x18, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/probestack.clif b/cranelift/filetests/filetests/isa/x64/probestack.clif
index d00509e318..dcf3db1324 100644
--- a/cranelift/filetests/filetests/isa/x64/probestack.clif
+++ b/cranelift/filetests/filetests/isa/x64/probestack.clif
@@ -10,6 +10,7 @@ block0:
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   movl    $100000, %eax
@@ -21,4 +22,17 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   movl $0x186a0, %eax
+;   callq 0xe ; reloc_external CallPCRel4 %Probestack -4
+;   subq $0x186a0, %rsp
+; block0: ; offset 0x15
+;   leaq (%rsp), %rax
+;   addq $0x186a0, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/sdiv.clif b/cranelift/filetests/filetests/isa/x64/sdiv.clif
index 543d7b82a3..6307bc90bd 100644
--- a/cranelift/filetests/filetests/isa/x64/sdiv.clif
+++ b/cranelift/filetests/filetests/isa/x64/sdiv.clif
@@ -7,6 +7,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   cbtw
+;   idivb %sil ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -23,6 +35,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   cwtd
+;   idivw %si ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -39,6 +63,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,6 +73,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   cltd
+;   idivl %esi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -55,6 +91,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -64,4 +101,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   cqto
+;   idivq %rsi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/select-i128.clif b/cranelift/filetests/filetests/isa/x64/select-i128.clif
index 33d1a371ee..e95dd22e3f 100644
--- a/cranelift/filetests/filetests/isa/x64/select-i128.clif
+++ b/cranelift/filetests/filetests/isa/x64/select-i128.clif
@@ -10,6 +10,7 @@ block0(v0: i32, v1: i128, v2: i128):
     return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -22,6 +23,20 @@ block0(v0: i32, v1: i128, v2: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl $0x2a, %edi
+;   movq %rcx, %rax
+;   cmoveq %rsi, %rax
+;   movq %rdx, %rdi
+;   movq %r8, %rdx
+;   cmoveq %rdi, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(f32, i128, i128) -> i128 {
 block0(v0: f32, v1: i128, v2: i128):
@@ -30,6 +45,7 @@ block0(v0: f32, v1: i128, v2: i128):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -43,4 +59,19 @@ block0(v0: f32, v1: i128, v2: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm0, %xmm0
+;   movq %rdi, %rax
+;   cmovneq %rdx, %rax
+;   cmovpq %rdx, %rax
+;   movq %rsi, %rdx
+;   cmovneq %rcx, %rdx
+;   cmovpq %rcx, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/select.clif b/cranelift/filetests/filetests/isa/x64/select.clif
index fab8ec38d8..18ca1fb446 100644
--- a/cranelift/filetests/filetests/isa/x64/select.clif
+++ b/cranelift/filetests/filetests/isa/x64/select.clif
@@ -9,6 +9,7 @@ block0(v0: i32, v1: i32, v2: i64, v3: i64):
     return v6
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -18,7 +19,17 @@ block0(v0: i32, v1: i32, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
-
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpl %esi, %edi
+;   movq %rcx, %rax
+;   cmoveq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f0(f32, f32, i64, i64) -> i64 {
 block0(v0: f32, v1: f32, v2: i64, v3: i64):
@@ -28,6 +39,7 @@ block0(v0: f32, v1: f32, v2: i64, v3: i64):
     return v6
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -38,4 +50,16 @@ block0(v0: f32, v1: f32, v2: i64, v3: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ucomiss %xmm0, %xmm1
+;   movq %rdi, %rax
+;   cmovneq %rsi, %rax
+;   cmovpq %rsi, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/sextend.clif b/cranelift/filetests/filetests/isa/x64/sextend.clif
index 6b56614e86..814594dcdb 100644
--- a/cranelift/filetests/filetests/isa/x64/sextend.clif
+++ b/cranelift/filetests/filetests/isa/x64/sextend.clif
@@ -7,6 +7,7 @@ block0(v0: i8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,4 +15,13 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movsbq %dil, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif b/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif
index c596618c7c..665c0bb8d9 100644
--- a/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif
+++ b/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif
@@ -9,6 +9,7 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -19,6 +20,26 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   movdqu 0x10(%rip), %xmm0
+;   movdqa %xmm5, %xmm6
+;   vpermi2b %xmm1, %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
 function %shuffle_out_of_bounds(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -29,6 +50,7 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -41,6 +63,31 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm7
+;   movdqu 0x30(%rip), %xmm0
+;   movdqu 0x18(%rip), %xmm6
+;   movdqa %xmm7, %xmm9
+;   vpermi2b %xmm1, %xmm9, %xmm6
+;   andps %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   cmpb $0xff, %bh
 
 function %f3(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -48,6 +95,7 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -58,4 +106,20 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   movdqu 0x10(%rip), %xmm0
+;   movdqa %xmm5, %xmm6
+;   vpermi2b %xmm1, %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rbx)
+;   addb %bl, (%rdi)
+;   sbbb (%rsi, %rax), %al
+;   orb $0xb, %al
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif b/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif
index 25f77c2189..39b6e08436 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif
@@ -9,6 +9,7 @@ block0(v0: i8x16, v1: i8x16):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -22,6 +23,21 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm4
+;   pcmpeqb %xmm1, %xmm4
+;   movdqa %xmm0, %xmm7
+;   movdqa %xmm4, %xmm0
+;   movdqa %xmm1, %xmm4
+;   pblendvb %xmm0, %xmm7, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %mask_from_fcmp(f32x4, f32x4, i32x4, i32x4) -> i32x4  {
 block0(v0: f32x4, v1: f32x4, v2: i32x4, v3: i32x4):
@@ -30,6 +46,7 @@ block0(v0: f32x4, v1: f32x4, v2: i32x4, v3: i32x4):
     return v5
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -40,6 +57,18 @@ block0(v0: f32x4, v1: f32x4, v2: i32x4, v3: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   cmpeqps %xmm1, %xmm0
+;   movdqa %xmm3, %xmm6
+;   pblendvb %xmm0, %xmm2, %xmm6
+;   movdqa %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %mask_casted(i8x16, i8x16, i32x4) -> i8x16 {
 block0(v0: i8x16, v1: i8x16, v2: i32x4):
@@ -48,6 +77,7 @@ block0(v0: i8x16, v1: i8x16, v2: i32x4):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -59,6 +89,19 @@ block0(v0: i8x16, v1: i8x16, v2: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm4
+;   pand %xmm2, %xmm4
+;   movdqa %xmm2, %xmm0
+;   pandn %xmm1, %xmm0
+;   por %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %good_const_mask_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -67,6 +110,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -79,6 +123,33 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   movdqu 0x20(%rip), %xmm0
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm1, %xmm4
+;   pblendvb %xmm0, %xmm6, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   incl (%rax)
+;   addb %bh, %bh
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   incl (%rax)
+;   addb %al, (%rax)
+;   addb %bh, %bh
 
 function %good_const_mask_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -87,6 +158,7 @@ block0(v0: i16x8, v1: i16x8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -99,6 +171,30 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   movdqu 0x20(%rip), %xmm0
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm1, %xmm4
+;   pblendvb %xmm0, %xmm6, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %bh, %bh
+;   addb %al, (%rax)
+;   incl (%rax)
+;   addb %al, (%rax)
 
 function %bad_const_mask(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -107,6 +203,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -119,4 +216,30 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm8
+;   movdqu 0x1f(%rip), %xmm0
+;   movdqa %xmm8, %xmm4
+;   pand %xmm0, %xmm4
+;   pandn %xmm1, %xmm0
+;   por %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %dh, %al
+;   addb %al, (%rax)
+;   incl (%rax)
+;   addb %al, (%rax)
+;   addb %bh, %bh
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif
index 5554a5069f..f9d020d878 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif
@@ -8,6 +8,7 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,15 @@ block0(v0: f32x4, v1: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andps %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %band_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -22,6 +32,7 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -29,6 +40,15 @@ block0(v0: f64x2, v1: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   andpd %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %band_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -36,6 +56,7 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -43,6 +64,15 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pand %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bor_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -50,6 +80,7 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -57,6 +88,15 @@ block0(v0: f32x4, v1: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   orps %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bor_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -64,6 +104,7 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -71,6 +112,15 @@ block0(v0: f64x2, v1: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   orpd %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -78,6 +128,7 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -85,6 +136,15 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   por %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bxor_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4):
@@ -92,6 +152,7 @@ block0(v0: f32x4, v1: f32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -99,6 +160,15 @@ block0(v0: f32x4, v1: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorps %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bxor_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
@@ -106,6 +176,7 @@ block0(v0: f64x2, v1: f64x2):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -113,6 +184,15 @@ block0(v0: f64x2, v1: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorpd %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %bxor_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -120,6 +200,7 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -127,6 +208,15 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pxor %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8, v2: i16x8):
@@ -134,6 +224,7 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -143,6 +234,17 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm2, %xmm4
+;   pblendvb %xmm0, %xmm1, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %vselect_f32x4(i32x4, f32x4, f32x4) -> f32x4 {
 block0(v0: i32x4, v1: f32x4, v2: f32x4):
@@ -150,6 +252,7 @@ block0(v0: i32x4, v1: f32x4, v2: f32x4):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -159,6 +262,17 @@ block0(v0: i32x4, v1: f32x4, v2: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm2, %xmm4
+;   blendvps %xmm0, %xmm1, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %vselect_f64x2(i64x2, f64x2, f64x2) -> f64x2 {
 block0(v0: i64x2, v1: f64x2, v2: f64x2):
@@ -166,6 +280,7 @@ block0(v0: i64x2, v1: f64x2, v2: f64x2):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -175,6 +290,17 @@ block0(v0: i64x2, v1: f64x2, v2: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm2, %xmm4
+;   blendvpd %xmm0, %xmm1, %xmm4
+;   movdqa %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ishl_i8x16(i32) -> i8x16 {
 block0(v0: i32):
@@ -183,6 +309,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -198,6 +325,27 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0xb4(%rip), %xmm0
+;   movq %rdi, %r10
+;   andq $7, %r10
+;   movd %r10d, %xmm5
+;   psllw %xmm5, %xmm0
+;   leaq 0x1d(%rip), %rsi
+;   shlq $4, %r10
+;   movdqu (%rsi, %r10), %xmm13
+;   pand %xmm13, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
 function %ushr_i8x16_imm() -> i8x16 {
 block0:
@@ -207,6 +355,7 @@ block0:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -222,6 +371,26 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0xb4(%rip), %xmm0
+;   movl $1, %r9d
+;   andq $7, %r9
+;   movd %r9d, %xmm5
+;   psrlw %xmm5, %xmm0
+;   leaq 0x1a(%rip), %rsi
+;   shlq $4, %r9
+;   movdqu (%rsi, %r9), %xmm13
+;   pand %xmm13, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %bh, %bh
 
 function %sshr_i8x16(i32) -> i8x16 {
 block0(v0: i32):
@@ -230,6 +399,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -247,6 +417,28 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x33(%rip), %xmm8
+;   movq %rdi, %r9
+;   andq $7, %r9
+;   movdqa %xmm8, %xmm0
+;   punpcklbw %xmm8, %xmm0
+;   punpckhbw %xmm8, %xmm8
+;   addl $8, %r9d
+;   movd %r9d, %xmm11
+;   psraw %xmm11, %xmm0
+;   psraw %xmm11, %xmm8
+;   packsswb %xmm8, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rcx)
+;   addb (%rbx), %al
+;   addb $5, %al
 
 function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
 block0(v0: i8x16, v1: i32):
@@ -254,6 +446,7 @@ block0(v0: i8x16, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -273,6 +466,27 @@ block0(v0: i8x16, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $3, %r10d
+;   andq $7, %r10
+;   movdqa %xmm0, %xmm13
+;   punpcklbw %xmm0, %xmm13
+;   movdqa %xmm13, %xmm12
+;   movdqa %xmm0, %xmm13
+;   punpckhbw %xmm0, %xmm13
+;   addl $8, %r10d
+;   movd %r10d, %xmm14
+;   movdqa %xmm12, %xmm0
+;   psraw %xmm14, %xmm0
+;   psraw %xmm14, %xmm13
+;   packsswb %xmm13, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64x2(i64x2, i32) -> i64x2 {
 block0(v0: i64x2, v1: i32):
@@ -280,6 +494,7 @@ block0(v0: i64x2, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -294,4 +509,19 @@ block0(v0: i64x2, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pextrq $0, %xmm0, %r8
+;   pextrq $1, %xmm0, %r10
+;   movq %rdi, %rcx
+;   sarq %cl, %r8
+;   sarq %cl, %r10
+;   pinsrq $0, %r8, %xmm0
+;   pinsrq $1, %r10, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
index 5357180789..66402bda54 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
@@ -8,6 +8,7 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,6 +18,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm1, %xmm0
+;   pcmpeqd %xmm5, %xmm5
+;   pxor %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
@@ -24,6 +36,7 @@ block0(v0: i32x4, v1: i32x4):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -34,6 +47,18 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmaxud %xmm1, %xmm0
+;   pcmpeqd %xmm1, %xmm0
+;   pcmpeqd %xmm7, %xmm7
+;   pxor %xmm7, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %icmp_sge_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
@@ -41,6 +66,7 @@ block0(v0: i16x8, v1: i16x8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -50,6 +76,17 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm3
+;   pmaxsw %xmm1, %xmm3
+;   pcmpeqw %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %icmp_uge_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -57,6 +94,7 @@ block0(v0: i8x16, v1: i8x16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -66,4 +104,15 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm3
+;   pmaxub %xmm1, %xmm3
+;   pcmpeqb %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
index 70250c3280..fe8925c816 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
@@ -12,6 +12,7 @@ block0:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -25,6 +26,50 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x64(%rip), %xmm0
+;   movdqu 0x4c(%rip), %xmm4
+;   movdqu 0x24(%rip), %xmm2
+;   pshufb %xmm2, %xmm0
+;   movdqu 0x27(%rip), %xmm6
+;   pshufb %xmm6, %xmm4
+;   por %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb $0x80, -0x7f7f7f80(%rax)
+;   addb $0x80, -0x7f7f7f80(%rax)
+;   addb $0, 0x101(%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
 function %shuffle_same_ssa_value() -> i8x16 {
 block0:
@@ -33,6 +78,7 @@ block0:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +88,33 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x24(%rip), %xmm0
+;   movdqu 0xc(%rip), %xmm1
+;   pshufb %xmm1, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rcx, %rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
 
 function %swizzle() -> i8x16 {
 block0:
@@ -51,6 +124,7 @@ block0:
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -62,6 +136,33 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x34(%rip), %xmm0
+;   movdqu 0x2c(%rip), %xmm2
+;   movdqu 0x14(%rip), %xmm3
+;   paddusb %xmm3, %xmm2
+;   pshufb %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   jo 0xa2
+;   jo 0xa4
+;   jo 0xa6
+;   jo 0xa8
+;   jo 0xaa
+;   jo 0xac
+;   jo 0xae
+;   jo 0xb0
+;   addb %al, (%rcx)
+;   addb (%rbx), %al
+;   addb $5, %al
 
 function %splat_i8(i8) -> i8x16 {
 block0(v0: i8):
@@ -69,6 +170,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -79,6 +181,17 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pinsrb $0, %edi, %xmm0
+;   pxor %xmm6, %xmm6
+;   pshufb %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %splat_i16() -> i16x8 {
 block0:
@@ -87,6 +200,7 @@ block0:
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -98,6 +212,18 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0xffffffff, %esi
+;   pinsrw $0, %esi, %xmm4
+;   pinsrw $1, %esi, %xmm4
+;   pshufd $0, %xmm4, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %splat_i32(i32) -> i32x4 {
 block0(v0: i32):
@@ -105,6 +231,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -114,6 +241,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pinsrd $0, %edi, %xmm3
+;   pshufd $0, %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %splat_f64(f64) -> f64x2 {
 block0(v0: f64):
@@ -121,6 +258,7 @@ block0(v0: f64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -132,6 +270,18 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   movdqa %xmm5, %xmm6
+;   movsd %xmm6, %xmm0
+;   movlhps %xmm6, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %load32_zero_coalesced(i64) -> i32x4 {
 block0(v0: i64):
@@ -140,6 +290,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -147,6 +298,15 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movss (%rdi), %xmm0 ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %load32_zero_int(i32) -> i32x4 {
 block0(v0: i32):
@@ -154,6 +314,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -161,6 +322,15 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movd %edi, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %load32_zero_float(f32) -> f32x4 {
 block0(v0: f32):
@@ -168,10 +338,19 @@ block0(v0: f32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif
index 1bffe9ac28..520ae43e2d 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif
@@ -8,6 +8,7 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,16 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pcmpeqd %xmm2, %xmm2
+;   pxor %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %vany_true_i32x4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -23,6 +34,7 @@ block0(v0: i32x4):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -31,6 +43,16 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ptest %xmm0, %xmm0
+;   setne %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %vall_true_i64x2(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -38,6 +60,7 @@ block0(v0: i64x2):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -49,4 +72,17 @@ block0(v0: i64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pxor %xmm2, %xmm2
+;   movdqa %xmm0, %xmm4
+;   pcmpeqq %xmm2, %xmm4
+;   ptest %xmm4, %xmm4
+;   sete %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif b/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif
index f69921386d..a195d97549 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif
@@ -9,6 +9,7 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -19,6 +20,27 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm4
+;   movdqu 0x10(%rip), %xmm0
+;   movdqa %xmm4, %xmm5
+;   pmaddubsw %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
 
 function %fn2(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -28,6 +50,7 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -36,6 +59,29 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x14(%rip), %xmm2
+;   pmaddwd %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
+;   addb %al, (%rcx)
 
 function %fn3(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -45,6 +91,7 @@ block0(v0: i8x16):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -53,6 +100,29 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x14(%rip), %xmm2
+;   pmaddubsw %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
+;   addl %eax, (%rcx)
 
 function %fn4(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -62,6 +132,7 @@ block0(v0: i16x8):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -74,4 +145,38 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x24(%rip), %xmm2
+;   pxor %xmm2, %xmm0
+;   movdqu 0x28(%rip), %xmm6
+;   pmaddwd %xmm6, %xmm0
+;   movdqu 0x2b(%rip), %xmm10
+;   paddd %xmm10, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb $0x80, (%rax)
+;   addb %al, -0x7fff8000(%rax)
+;   addb %al, -0x7fff8000(%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addl %eax, (%rax)
+;   addb %al, (%rax)
+;   addl %eax, (%rax)
+;   addb %al, (%rax)
+;   addl %eax, (%rax)
+;   addb %al, (%rax)
+;   addl %eax, (%rax)
+;   addb %al, (%rax)
+;   addl %eax, (%rax)
 
diff --git a/cranelift/filetests/filetests/isa/x64/simd-widen-mul.clif b/cranelift/filetests/filetests/isa/x64/simd-widen-mul.clif
index daa5ad5ef3..2b4969847a 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-widen-mul.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-widen-mul.clif
@@ -12,6 +12,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -25,6 +26,21 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm3
+;   palignr $8, %xmm0, %xmm3
+;   pmovsxbw %xmm3, %xmm0
+;   movdqa %xmm1, %xmm7
+;   palignr $8, %xmm1, %xmm7
+;   pmovsxbw %xmm7, %xmm9
+;   pmullw %xmm9, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_swiden_hi_i16x8(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -34,6 +50,7 @@ block0(v0: i16x8, v1: i16x8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -47,6 +64,21 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   pmullw %xmm1, %xmm5
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm0, %xmm5
+;   pmulhw %xmm1, %xmm5
+;   movdqa %xmm6, %xmm0
+;   punpckhwd %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_swiden_hi_i32x4(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -56,6 +88,7 @@ block0(v0: i32x4, v1: i32x4):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -65,6 +98,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0xfa, %xmm0, %xmm0
+;   pshufd $0xfa, %xmm1, %xmm5
+;   pmuldq %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_swiden_low_i8x16(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -74,6 +118,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -83,6 +128,17 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovsxbw %xmm0, %xmm0
+;   pmovsxbw %xmm1, %xmm5
+;   pmullw %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_swiden_low_i16x8(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -92,6 +148,7 @@ block0(v0: i16x8, v1: i16x8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -105,6 +162,21 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   pmullw %xmm1, %xmm5
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm0, %xmm5
+;   pmulhw %xmm1, %xmm5
+;   movdqa %xmm6, %xmm0
+;   punpcklwd %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_swiden_low_i32x4(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -114,6 +186,7 @@ block0(v0: i32x4, v1: i32x4):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -123,6 +196,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0x50, %xmm0, %xmm0
+;   pshufd $0x50, %xmm1, %xmm5
+;   pmuldq %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_hi_i8x16(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -132,6 +216,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -145,6 +230,21 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm3
+;   palignr $8, %xmm0, %xmm3
+;   pmovzxbw %xmm3, %xmm0
+;   movdqa %xmm1, %xmm7
+;   palignr $8, %xmm1, %xmm7
+;   pmovzxbw %xmm7, %xmm9
+;   pmullw %xmm9, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_hi_i16x8(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -154,6 +254,7 @@ block0(v0: i16x8, v1: i16x8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -167,6 +268,21 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   pmullw %xmm1, %xmm5
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm0, %xmm5
+;   pmulhuw %xmm1, %xmm5
+;   movdqa %xmm6, %xmm0
+;   punpckhwd %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_hi_i32x4(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -176,6 +292,7 @@ block0(v0: i32x4, v1: i32x4):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -185,6 +302,17 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0xfa, %xmm0, %xmm0
+;   pshufd $0xfa, %xmm1, %xmm5
+;   pmuludq %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_low_i8x16(i8x16, i8x16) -> i16x8 {
 block0(v0: i8x16, v1: i8x16):
@@ -194,6 +322,7 @@ block0(v0: i8x16, v1: i8x16):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -203,6 +332,17 @@ block0(v0: i8x16, v1: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovzxbw %xmm0, %xmm0
+;   pmovzxbw %xmm1, %xmm5
+;   pmullw %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_low_i16x8(i16x8, i16x8) -> i32x4 {
 block0(v0: i16x8, v1: i16x8):
@@ -212,6 +352,7 @@ block0(v0: i16x8, v1: i16x8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -225,6 +366,21 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm5
+;   pmullw %xmm1, %xmm5
+;   movdqa %xmm5, %xmm6
+;   movdqa %xmm0, %xmm5
+;   pmulhuw %xmm1, %xmm5
+;   movdqa %xmm6, %xmm0
+;   punpcklwd %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %imul_uwiden_low_i32x4(i32x4, i32x4) -> i64x2 {
 block0(v0: i32x4, v1: i32x4):
@@ -234,6 +390,7 @@ block0(v0: i32x4, v1: i32x4):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -243,4 +400,15 @@ block0(v0: i32x4, v1: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0x50, %xmm0, %xmm0
+;   pshufd $0x50, %xmm1, %xmm5
+;   pmuludq %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/smulhi.clif b/cranelift/filetests/filetests/isa/x64/smulhi.clif
index 0958ce301b..e456a6732c 100644
--- a/cranelift/filetests/filetests/isa/x64/smulhi.clif
+++ b/cranelift/filetests/filetests/isa/x64/smulhi.clif
@@ -7,6 +7,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   imulw %si
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -23,6 +35,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   imull %esi
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -39,6 +63,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,4 +73,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   imulq %rsi
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif b/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif
index 83469f9644..b5f0c25904 100644
--- a/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif
+++ b/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif
@@ -7,6 +7,7 @@ block0(v0: i16x8, v1: i16x8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,4 +18,19 @@ block0(v0: i16x8, v1: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x14(%rip), %xmm5
+;   pmulhrsw %xmm1, %xmm0
+;   pcmpeqw %xmm0, %xmm5
+;   pxor %xmm5, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, -0x7fff8000(%rax)
+;   addb %al, -0x7fff8000(%rax)
 
diff --git a/cranelift/filetests/filetests/isa/x64/srem.clif b/cranelift/filetests/filetests/isa/x64/srem.clif
index 131d7ac89f..38123c09d8 100644
--- a/cranelift/filetests/filetests/isa/x64/srem.clif
+++ b/cranelift/filetests/filetests/isa/x64/srem.clif
@@ -7,6 +7,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,6 +18,26 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpb $0, %sil
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpb $0xff, %sil
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cbtw
+;   idivb %sil ; trap: int_divz
+;   shrq $8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -24,6 +45,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -34,6 +56,26 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpw $0, %si
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpw $-1, %si
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cwtd
+;   idivw %si ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -41,6 +83,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -51,6 +94,26 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpl $0, %esi
+;   jne 0x14
+;   ud2 ; trap: int_divz
+;   cmpl $-1, %esi
+;   jne 0x27
+;   movl $0, %eax
+;   jmp 0x2a
+;   cltd
+;   idivl %esi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -58,6 +121,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -68,4 +132,24 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   xorl %edx, %edx
+;   cmpq $0, %rsi
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpq $-1, %rsi
+;   jne 0x29
+;   movl $0, %eax
+;   jmp 0x2e
+;   cqto
+;   idivq %rsi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/sshr.clif b/cranelift/filetests/filetests/isa/x64/sshr.clif
index 8f66e59472..b6df919ac3 100644
--- a/cranelift/filetests/filetests/isa/x64/sshr.clif
+++ b/cranelift/filetests/filetests/isa/x64/sshr.clif
@@ -13,6 +13,7 @@ block0(v0: i128, v1: i8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -40,6 +41,35 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dl, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r10
+;   sarq %cl, %r10
+;   movq %rcx, %r11
+;   movl $0x40, %ecx
+;   movq %r11, %rax
+;   subq %rax, %rcx
+;   movq %rsi, %r9
+;   shlq %cl, %r9
+;   xorq %r11, %r11
+;   testq $0x7f, %rax
+;   cmoveq %r11, %r9
+;   orq %r9, %r8
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rax
+;   movq %r10, %rax
+;   cmoveq %r8, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i128_i64(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -47,6 +77,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -73,6 +104,34 @@ block0(v0: i128, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r11
+;   shrq %cl, %r11
+;   movq %rsi, %r9
+;   sarq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r8
+;   shlq %cl, %r8
+;   xorq %r10, %r10
+;   testq $0x7f, %rdi
+;   cmoveq %r10, %r8
+;   orq %r8, %r11
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i128_i32(i128, i32) -> i128 {
 block0(v0: i128, v1: i32):
@@ -80,6 +139,7 @@ block0(v0: i128, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -106,6 +166,34 @@ block0(v0: i128, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r11
+;   shrq %cl, %r11
+;   movq %rsi, %r9
+;   sarq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r8
+;   shlq %cl, %r8
+;   xorq %r10, %r10
+;   testq $0x7f, %rdi
+;   cmoveq %r10, %r8
+;   orq %r8, %r11
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i128_i16(i128, i16) -> i128 {
 block0(v0: i128, v1: i16):
@@ -113,6 +201,7 @@ block0(v0: i128, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -139,6 +228,34 @@ block0(v0: i128, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r11
+;   shrq %cl, %r11
+;   movq %rsi, %r9
+;   sarq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r8
+;   shlq %cl, %r8
+;   xorq %r10, %r10
+;   testq $0x7f, %rdi
+;   cmoveq %r10, %r8
+;   orq %r8, %r11
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -146,6 +263,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -172,6 +290,34 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r11
+;   shrq %cl, %r11
+;   movq %rsi, %r9
+;   sarq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r8
+;   shlq %cl, %r8
+;   xorq %r10, %r10
+;   testq $0x7f, %rdi
+;   cmoveq %r10, %r8
+;   orq %r8, %r11
+;   movq %rsi, %rdx
+;   sarq $0x3f, %rdx
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_i128(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -179,6 +325,7 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -188,6 +335,17 @@ block0(v0: i64, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_i128(i32, i128) -> i32 {
 block0(v0: i32, v1: i128):
@@ -195,6 +353,7 @@ block0(v0: i32, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -204,6 +363,17 @@ block0(v0: i32, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_i128(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -211,6 +381,7 @@ block0(v0: i16, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -221,6 +392,18 @@ block0(v0: i16, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   sarw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_i128(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -228,6 +411,7 @@ block0(v0: i8, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -238,6 +422,18 @@ block0(v0: i8, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   sarb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -245,6 +441,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -254,6 +451,17 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_i32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -261,6 +469,7 @@ block0(v0: i64, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -270,6 +479,17 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_i16(i64, i16) -> i64 {
 block0(v0: i64, v1: i16):
@@ -277,6 +497,7 @@ block0(v0: i64, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -286,6 +507,17 @@ block0(v0: i64, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_i8(i64, i8) -> i64 {
 block0(v0: i64, v1: i8):
@@ -293,6 +525,7 @@ block0(v0: i64, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -302,6 +535,17 @@ block0(v0: i64, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_i64(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -309,6 +553,7 @@ block0(v0: i32, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -318,6 +563,17 @@ block0(v0: i32, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -325,6 +581,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -334,6 +591,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_i16(i32, i16) -> i32 {
 block0(v0: i32, v1: i16):
@@ -341,6 +609,7 @@ block0(v0: i32, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -350,6 +619,17 @@ block0(v0: i32, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_i8(i32, i8) -> i32 {
 block0(v0: i32, v1: i8):
@@ -357,6 +637,7 @@ block0(v0: i32, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -366,6 +647,17 @@ block0(v0: i32, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   sarl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_i64(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -373,6 +665,7 @@ block0(v0: i16, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -383,6 +676,18 @@ block0(v0: i16, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   sarw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_i32(i16, i32) -> i16 {
 block0(v0: i16, v1: i32):
@@ -390,6 +695,7 @@ block0(v0: i16, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -400,6 +706,18 @@ block0(v0: i16, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   sarw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -407,6 +725,7 @@ block0(v0: i16, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -417,6 +736,18 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   sarw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_i8(i16, i8) -> i16 {
 block0(v0: i16, v1: i8):
@@ -424,6 +755,7 @@ block0(v0: i16, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -434,6 +766,18 @@ block0(v0: i16, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   sarw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_i64(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -441,6 +785,7 @@ block0(v0: i8, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -451,6 +796,18 @@ block0(v0: i8, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   sarb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_i32(i8, i32) -> i8 {
 block0(v0: i8, v1: i32):
@@ -458,6 +815,7 @@ block0(v0: i8, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -468,6 +826,18 @@ block0(v0: i8, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   sarb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_i16(i8, i16) -> i8 {
 block0(v0: i8, v1: i16):
@@ -475,6 +845,7 @@ block0(v0: i8, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -485,6 +856,18 @@ block0(v0: i8, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   sarb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -492,6 +875,7 @@ block0(v0: i8, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -502,6 +886,18 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   sarb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i64_const(i64) -> i64 {
 block0(v0: i64):
@@ -509,6 +905,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -517,6 +914,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   sarq $1, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i32_const(i32) -> i32 {
 block0(v0: i32):
@@ -524,6 +931,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -532,6 +940,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   sarl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i16_const(i16) -> i16 {
 block0(v0: i16):
@@ -539,6 +957,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -547,6 +966,16 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   sarw $1, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %sshr_i8_const(i8) -> i8 {
 block0(v0: i8):
@@ -554,6 +983,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -562,4 +992,14 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   sarb $1, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/struct-arg.clif b/cranelift/filetests/filetests/isa/x64/struct-arg.clif
index 6d3f7160b2..5766f116f3 100644
--- a/cranelift/filetests/filetests/isa/x64/struct-arg.clif
+++ b/cranelift/filetests/filetests/isa/x64/struct-arg.clif
@@ -7,6 +7,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   leaq 0x10(%rbp), %rsi
+;   movzbq (%rsi), %rax ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function u0:1(i64 sarg(64), i64) -> i8 system_v {
 block0(v0: i64, v1: i64):
@@ -24,6 +35,7 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -34,6 +46,18 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   leaq 0x10(%rbp), %rcx
+;   movzbq (%rdi), %rax ; trap: heap_oob
+;   movzbq (%rcx), %r9 ; trap: heap_oob
+;   addl %r9d, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function u0:2(i64) -> i8 system_v {
 fn1 = colocated u0:0(i64 sarg(64)) -> i8 system_v
@@ -43,6 +67,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -59,6 +84,22 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rsi
+;   subq $0x40, %rsp
+;   leaq (%rsp), %rdi
+;   movl $0x40, %edx
+;   movabsq $0, %r11 ; reloc_external Abs8 %Memcpy 0
+;   callq *%r11
+;   callq 0x26 ; reloc_external CallPCRel4 u0:0 -4
+;   addq $0x40, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function u0:3(i64, i64) -> i8 system_v {
 fn1 = colocated u0:0(i64, i64 sarg(64)) -> i8 system_v
@@ -68,6 +109,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -89,6 +131,27 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r13, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdi, %r13
+;   subq $0x40, %rsp
+;   leaq (%rsp), %rdi
+;   movl $0x40, %edx
+;   movabsq $0, %rax ; reloc_external Abs8 %Memcpy 0
+;   callq *%rax
+;   movq %r13, %rdi
+;   callq 0x30 ; reloc_external CallPCRel4 u0:0 -4
+;   addq $0x40, %rsp
+;   movq (%rsp), %r13
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function u0:4(i64 sarg(128), i64 sarg(64)) -> i8 system_v {
 block0(v0: i64, v1: i64):
@@ -98,6 +161,7 @@ block0(v0: i64, v1: i64):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -109,6 +173,19 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   leaq 0x10(%rbp), %rsi
+;   leaq 0x90(%rbp), %rcx
+;   movzbq (%rsi), %rax ; trap: heap_oob
+;   movzbq (%rcx), %r9 ; trap: heap_oob
+;   addl %r9d, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function u0:5(i64, i64, i64) -> i8 system_v {
 fn1 = colocated u0:0(i64, i64 sarg(128), i64 sarg(64)) -> i8 system_v
@@ -118,6 +195,7 @@ block0(v0: i64, v1: i64, v2: i64):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -147,4 +225,33 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r12, (%rsp)
+;   movq %r14, 8(%rsp)
+; block0: ; offset 0x11
+;   movq %rdx, %r14
+;   movq %rdi, %r12
+;   subq $0xc0, %rsp
+;   leaq (%rsp), %rdi
+;   movl $0x80, %edx
+;   movabsq $0, %rax ; reloc_external Abs8 %Memcpy 0
+;   callq *%rax
+;   leaq 0x80(%rsp), %rdi
+;   movl $0x40, %edx
+;   movabsq $0, %r11 ; reloc_external Abs8 %Memcpy 0
+;   movq %r14, %rsi
+;   callq *%r11
+;   movq %r12, %rdi
+;   callq 0x58 ; reloc_external CallPCRel4 u0:0 -4
+;   addq $0xc0, %rsp
+;   movq (%rsp), %r12
+;   movq 8(%rsp), %r14
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/struct-ret.clif b/cranelift/filetests/filetests/isa/x64/struct-ret.clif
index c5e6f68817..cfeb4fcd10 100644
--- a/cranelift/filetests/filetests/isa/x64/struct-ret.clif
+++ b/cranelift/filetests/filetests/isa/x64/struct-ret.clif
@@ -8,6 +8,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,7 +18,17 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
-
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0x2a, %edx
+;   movq %rdx, (%rdi) ; trap: heap_oob
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i64, i64) -> i64 {
     fn0 = %f2(i64 sret) -> i64
@@ -27,6 +38,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -37,6 +49,18 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rdi
+;   movabsq $0, %rdx ; reloc_external Abs8 %f2 0
+;   callq *%rdx
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64 sret) {
     fn0 = %f4(i64 sret)
@@ -46,6 +70,7 @@ block0(v0: i64):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ;   subq    %rsp, $16, %rsp
@@ -60,4 +85,20 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+;   subq $0x10, %rsp
+;   movq %r15, (%rsp)
+; block0: ; offset 0xc
+;   movq %rdi, %r15
+;   movabsq $0, %rdx ; reloc_external Abs8 %f4 0
+;   callq *%rdx
+;   movq %r15, %rax
+;   movq (%rsp), %r15
+;   addq $0x10, %rsp
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/symbols.clif b/cranelift/filetests/filetests/isa/x64/symbols.clif
index 821cf072a7..ceb423d175 100644
--- a/cranelift/filetests/filetests/isa/x64/symbols.clif
+++ b/cranelift/filetests/filetests/isa/x64/symbols.clif
@@ -9,6 +9,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,15 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rax ; reloc_external Abs8 %func0 0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %symbol_value() -> i64 {
     gv0 = symbol %global0
@@ -25,6 +35,7 @@ block0:
     return v0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,4 +43,13 @@ block0:
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rax ; reloc_external Abs8 %global0 0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/table.clif b/cranelift/filetests/filetests/isa/x64/table.clif
index ea908e9935..bd769a6cd7 100644
--- a/cranelift/filetests/filetests/isa/x64/table.clif
+++ b/cranelift/filetests/filetests/isa/x64/table.clif
@@ -16,6 +16,7 @@ block0(v0: i32, v1: r64, v2: i64):
     return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -35,4 +36,25 @@ block0(v0: i32, v1: r64, v2: i64):
 ;   ret
 ; block1:
 ;   ud2 table_oob
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl 8(%rdx), %r11d
+;   cmpl %r11d, %edi
+;   jae 0x2b
+; block1: ; offset 0x11
+;   movl %edi, %ecx
+;   movq (%rdx), %rax
+;   movq %rax, %rdx
+;   addq %rcx, %rdx
+;   cmpl %r11d, %edi
+;   cmovaeq %rax, %rdx
+;   movq %rsi, (%rdx)
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+; block2: ; offset 0x2b
+;   ud2 ; trap: table_oob
 
diff --git a/cranelift/filetests/filetests/isa/x64/tls_coff.clif b/cranelift/filetests/filetests/isa/x64/tls_coff.clif
index 95421d8c78..05e583d151 100644
--- a/cranelift/filetests/filetests/isa/x64/tls_coff.clif
+++ b/cranelift/filetests/filetests/isa/x64/tls_coff.clif
@@ -11,6 +11,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -18,4 +19,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl (%rip), %eax ; reloc_external PCRel4 %CoffTlsIndex -4
+;   movq %gs:0x58, %rcx
+;   movq (%rcx, %rax, 8), %rax
+;   leaq (%rax), %rax ; reloc_external SecRel u1:0 0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/tls_elf.clif b/cranelift/filetests/filetests/isa/x64/tls_elf.clif
index cbee527f99..6449740f56 100644
--- a/cranelift/filetests/filetests/isa/x64/tls_elf.clif
+++ b/cranelift/filetests/filetests/isa/x64/tls_elf.clif
@@ -10,6 +10,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,4 +18,14 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   leaq (%rip), %rdi ; reloc_external ElfX86_64TlsGd u1:0 -4
+;   callq 0x14 ; reloc_external CallPLTRel4 %ElfTlsGetAddr -4
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/traps.clif b/cranelift/filetests/filetests/isa/x64/traps.clif
index b314f8884a..243935119d 100644
--- a/cranelift/filetests/filetests/isa/x64/traps.clif
+++ b/cranelift/filetests/filetests/isa/x64/traps.clif
@@ -6,11 +6,17 @@ block0:
   trap user0
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
 ;   ud2 user0
-
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   ud2 ; trap: user0
 
 function %trap_iadd_ifcout(i64, i64) {
 block0(v0: i64, v1: i64):
@@ -18,6 +24,7 @@ block0(v0: i64, v1: i64):
   return
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -27,4 +34,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rcx
+;   addq %rsi, %rcx
+;   jae 0x12
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif b/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif
index d547627d89..f422e0522d 100644
--- a/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif
+++ b/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %TruncF32 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -22,6 +33,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -30,4 +42,14 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movabsq $0, %rcx ; reloc_external Abs8 %TruncF64 0
+;   callq *%rcx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/trunc.clif b/cranelift/filetests/filetests/isa/x64/trunc.clif
index fbf9cf0948..3cbaeb9488 100644
--- a/cranelift/filetests/filetests/isa/x64/trunc.clif
+++ b/cranelift/filetests/filetests/isa/x64/trunc.clif
@@ -7,6 +7,7 @@ block0(v0: f32):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: f32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundss $3, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(f64) -> f64 {
 block0(v0: f64):
@@ -21,6 +31,7 @@ block0(v0: f64):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: f64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundsd $3, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f32x4) -> f32x4 {
 block0(v0: f32x4):
@@ -35,6 +55,7 @@ block0(v0: f32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: f32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundps $3, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(f64x2) -> f64x2 {
 block0(v0: f64x2):
@@ -49,6 +79,7 @@ block0(v0: f64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -56,4 +87,13 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   roundpd $3, %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/x64/uadd_overflow_trap.clif
index 390a580184..094af916fa 100644
--- a/cranelift/filetests/filetests/isa/x64/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/x64/uadd_overflow_trap.clif
@@ -8,6 +8,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,6 +18,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addl $0x7f, %eax
+;   jae 0x12
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f1(i32) -> i32 {
 block0(v0: i32):
@@ -25,6 +38,7 @@ block0(v0: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -34,6 +48,18 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addl $0x7f, %eax
+;   jae 0x12
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -41,6 +67,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -50,6 +77,18 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addl %esi, %eax
+;   jae 0x11
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -58,6 +97,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -67,6 +107,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addq $0x7f, %rax
+;   jae 0x13
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64) -> i64 {
 block0(v0: i64):
@@ -75,6 +127,7 @@ block0(v0: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -84,6 +137,18 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addq $0x7f, %rax
+;   jae 0x13
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -91,6 +156,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -100,4 +166,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addq %rsi, %rax
+;   jae 0x12
+;   ud2 ; trap: user0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/udiv.clif b/cranelift/filetests/filetests/isa/x64/udiv.clif
index 71ad6b75ed..ecd7bf622c 100644
--- a/cranelift/filetests/filetests/isa/x64/udiv.clif
+++ b/cranelift/filetests/filetests/isa/x64/udiv.clif
@@ -7,6 +7,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -15,6 +16,16 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbl %dil, %eax
+;   divb %sil ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -22,6 +33,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -31,6 +43,17 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divw %si ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -38,6 +61,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -47,6 +71,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divl %esi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -54,6 +89,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -63,4 +99,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divq %rsi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/udivrem.clif b/cranelift/filetests/filetests/isa/x64/udivrem.clif
index 4087566f64..9540502a61 100644
--- a/cranelift/filetests/filetests/isa/x64/udivrem.clif
+++ b/cranelift/filetests/filetests/isa/x64/udivrem.clif
@@ -10,6 +10,7 @@ block0(v0: i8, v1: i8):
   return v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -24,6 +25,22 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbl %dil, %eax
+;   divb %sil ; trap: int_divz
+;   movq %rax, %rcx
+;   movzbl %dil, %eax
+;   divb %sil ; trap: int_divz
+;   movq %rax, %rdx
+;   shrq $8, %rdx
+;   movq %rcx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %udivrem_i16(i16, i16) -> i16, i16 {
 block0(v0: i16, v1: i16):
@@ -32,6 +49,7 @@ block0(v0: i16, v1: i16):
   return v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -47,6 +65,23 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0, %edx
+;   movq %rdi, %rax
+;   divw %si ; trap: int_divz
+;   movq %rdi, %rcx
+;   movq %rax, %r8
+;   movl $0, %edx
+;   movq %rcx, %rax
+;   divw %si ; trap: int_divz
+;   movq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %udivrem_i32(i32, i32) -> i32, i32 {
 block0(v0: i32, v1: i32):
@@ -55,6 +90,7 @@ block0(v0: i32, v1: i32):
   return v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -70,6 +106,23 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0, %edx
+;   movq %rdi, %rax
+;   divl %esi ; trap: int_divz
+;   movq %rdi, %rcx
+;   movq %rax, %r8
+;   movl $0, %edx
+;   movq %rcx, %rax
+;   divl %esi ; trap: int_divz
+;   movq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %udivrem_i64(i64, i64) -> i64, i64 {
 block0(v0: i64, v1: i64):
@@ -78,6 +131,7 @@ block0(v0: i64, v1: i64):
   return v2, v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -93,4 +147,21 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl $0, %edx
+;   movq %rdi, %rax
+;   divq %rsi ; trap: int_divz
+;   movq %rdi, %rcx
+;   movq %rax, %r8
+;   movl $0, %edx
+;   movq %rcx, %rax
+;   divq %rsi ; trap: int_divz
+;   movq %r8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/uextend-elision.clif b/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
index 7ffc50c086..35bd0020e2 100644
--- a/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
+++ b/cranelift/filetests/filetests/isa/x64/uextend-elision.clif
@@ -8,6 +8,7 @@ block0(v0: i32, v1: i32):
     return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,4 +17,14 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   addl %esi, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/umax-bug.clif b/cranelift/filetests/filetests/isa/x64/umax-bug.clif
index 09b7c8106b..9b67e5ad5c 100644
--- a/cranelift/filetests/filetests/isa/x64/umax-bug.clif
+++ b/cranelift/filetests/filetests/isa/x64/umax-bug.clif
@@ -8,6 +8,7 @@ block0(v1: i32, v2: i64):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -18,4 +19,16 @@ block0(v1: i32, v2: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movl (%rsi), %edx
+;   cmpl %edi, %edx
+;   movq %rdi, %rax
+;   cmovael %edx, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/umulhi.clif b/cranelift/filetests/filetests/isa/x64/umulhi.clif
index c5b0b73a26..09442e8173 100644
--- a/cranelift/filetests/filetests/isa/x64/umulhi.clif
+++ b/cranelift/filetests/filetests/isa/x64/umulhi.clif
@@ -7,6 +7,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   mulw %si
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -23,6 +35,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -32,6 +45,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   mull %esi
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -39,6 +63,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -48,4 +73,15 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   mulq %rsi
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/urem.clif b/cranelift/filetests/filetests/isa/x64/urem.clif
index d89984faba..fa4396fa4d 100644
--- a/cranelift/filetests/filetests/isa/x64/urem.clif
+++ b/cranelift/filetests/filetests/isa/x64/urem.clif
@@ -7,6 +7,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -16,6 +17,17 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbl %dil, %eax
+;   divb %sil ; trap: int_divz
+;   shrq $8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -23,6 +35,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -33,6 +46,18 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divw %si ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -40,6 +65,7 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -50,6 +76,18 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divl %esi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -57,6 +95,7 @@ block0(v0: i64, v1: i64):
   return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -67,4 +106,16 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   movl $0, %edx
+;   divq %rsi ; trap: int_divz
+;   movq %rdx, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/ushr.clif b/cranelift/filetests/filetests/isa/x64/ushr.clif
index 0424599689..1ce022b62f 100644
--- a/cranelift/filetests/filetests/isa/x64/ushr.clif
+++ b/cranelift/filetests/filetests/isa/x64/ushr.clif
@@ -12,6 +12,7 @@ block0(v0: i128, v1: i8):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -37,6 +38,33 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movzbq %dl, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r10
+;   shrq %cl, %r10
+;   movq %rcx, %r9
+;   movl $0x40, %ecx
+;   movq %r9, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r11
+;   shlq %cl, %r11
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r11
+;   orq %r8, %r11
+;   testq $0x40, %rdi
+;   movq %r10, %rax
+;   cmoveq %r11, %rax
+;   cmoveq %r10, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i128_i64(i128, i64) -> i128 {
 block0(v0: i128, v1: i64):
@@ -44,6 +72,7 @@ block0(v0: i128, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -68,6 +97,32 @@ block0(v0: i128, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r9
+;   shrq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r10
+;   orq %r8, %r10
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r10, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i128_i32(i128, i32) -> i128 {
 block0(v0: i128, v1: i32):
@@ -75,6 +130,7 @@ block0(v0: i128, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -99,6 +155,32 @@ block0(v0: i128, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r9
+;   shrq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r10
+;   orq %r8, %r10
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r10, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i128_i16(i128, i16) -> i128 {
 block0(v0: i128, v1: i16):
@@ -106,6 +188,7 @@ block0(v0: i128, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -130,6 +213,32 @@ block0(v0: i128, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r9
+;   shrq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r10
+;   orq %r8, %r10
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r10, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i128_i8(i128, i8) -> i128 {
 block0(v0: i128, v1: i8):
@@ -137,6 +246,7 @@ block0(v0: i128, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -161,6 +271,32 @@ block0(v0: i128, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdx, %rcx
+;   movq %rdi, %r8
+;   shrq %cl, %r8
+;   movq %rsi, %r9
+;   shrq %cl, %r9
+;   movl $0x40, %ecx
+;   movq %rdx, %rdi
+;   subq %rdi, %rcx
+;   movq %rsi, %r10
+;   shlq %cl, %r10
+;   xorq %rdx, %rdx
+;   testq $0x7f, %rdi
+;   cmoveq %rdx, %r10
+;   orq %r8, %r10
+;   testq $0x40, %rdi
+;   movq %r9, %rax
+;   cmoveq %r10, %rax
+;   cmoveq %r9, %rdx
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_i128(i64, i128) -> i64 {
 block0(v0: i64, v1: i128):
@@ -168,6 +304,7 @@ block0(v0: i64, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -177,6 +314,17 @@ block0(v0: i64, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_i128(i32, i64, i64) -> i32 {
 block0(v0: i32, v1: i64, v2: i64):
@@ -185,6 +333,7 @@ block0(v0: i32, v1: i64, v2: i64):
     return v4
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -194,6 +343,17 @@ block0(v0: i32, v1: i64, v2: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_i128(i16, i128) -> i16 {
 block0(v0: i16, v1: i128):
@@ -201,6 +361,7 @@ block0(v0: i16, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -211,6 +372,18 @@ block0(v0: i16, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shrw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_i128(i8, i128) -> i8 {
 block0(v0: i8, v1: i128):
@@ -218,6 +391,7 @@ block0(v0: i8, v1: i128):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -228,6 +402,18 @@ block0(v0: i8, v1: i128):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shrb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_i64(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
@@ -235,6 +421,7 @@ block0(v0: i64, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -244,6 +431,17 @@ block0(v0: i64, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_i32(i64, i32) -> i64 {
 block0(v0: i64, v1: i32):
@@ -251,6 +449,7 @@ block0(v0: i64, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -260,6 +459,17 @@ block0(v0: i64, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_i16(i64, i16) -> i64 {
 block0(v0: i64, v1: i16):
@@ -267,6 +477,7 @@ block0(v0: i64, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -276,6 +487,17 @@ block0(v0: i64, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_i8(i64, i8) -> i64 {
 block0(v0: i64, v1: i8):
@@ -283,6 +505,7 @@ block0(v0: i64, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -292,6 +515,17 @@ block0(v0: i64, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrq %cl, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_i64(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
@@ -299,6 +533,7 @@ block0(v0: i32, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -308,6 +543,17 @@ block0(v0: i32, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_i32(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):
@@ -315,6 +561,7 @@ block0(v0: i32, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -324,6 +571,17 @@ block0(v0: i32, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_i16(i32, i16) -> i32 {
 block0(v0: i32, v1: i16):
@@ -331,6 +589,7 @@ block0(v0: i32, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -340,6 +599,17 @@ block0(v0: i32, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_i8(i32, i8) -> i32 {
 block0(v0: i32, v1: i8):
@@ -347,6 +617,7 @@ block0(v0: i32, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -356,6 +627,17 @@ block0(v0: i32, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   movq %rdi, %rax
+;   shrl %cl, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_i64(i16, i64) -> i16 {
 block0(v0: i16, v1: i64):
@@ -363,6 +645,7 @@ block0(v0: i16, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -373,6 +656,18 @@ block0(v0: i16, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shrw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_i32(i16, i32) -> i16 {
 block0(v0: i16, v1: i32):
@@ -380,6 +675,7 @@ block0(v0: i16, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -390,6 +686,18 @@ block0(v0: i16, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shrw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_i16(i16, i16) -> i16 {
 block0(v0: i16, v1: i16):
@@ -397,6 +705,7 @@ block0(v0: i16, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -407,6 +716,18 @@ block0(v0: i16, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shrw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_i8(i16, i8) -> i16 {
 block0(v0: i16, v1: i8):
@@ -414,6 +735,7 @@ block0(v0: i16, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -424,6 +746,18 @@ block0(v0: i16, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $0xf, %rcx
+;   movq %rdi, %rax
+;   shrw %cl, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_i64(i8, i64) -> i8 {
 block0(v0: i8, v1: i64):
@@ -431,6 +765,7 @@ block0(v0: i8, v1: i64):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -441,6 +776,18 @@ block0(v0: i8, v1: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shrb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_i32(i8, i32) -> i8 {
 block0(v0: i8, v1: i32):
@@ -448,6 +795,7 @@ block0(v0: i8, v1: i32):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -458,6 +806,18 @@ block0(v0: i8, v1: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shrb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_i16(i8, i16) -> i8 {
 block0(v0: i8, v1: i16):
@@ -465,6 +825,7 @@ block0(v0: i8, v1: i16):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -475,6 +836,18 @@ block0(v0: i8, v1: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shrb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_i8(i8, i8) -> i8 {
 block0(v0: i8, v1: i8):
@@ -482,6 +855,7 @@ block0(v0: i8, v1: i8):
     return v2
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -492,6 +866,18 @@ block0(v0: i8, v1: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rsi, %rcx
+;   andq $7, %rcx
+;   movq %rdi, %rax
+;   shrb %cl, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i64_const(i64) -> i64 {
 block0(v0: i64):
@@ -499,6 +885,7 @@ block0(v0: i64):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -507,6 +894,16 @@ block0(v0: i64):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrq $1, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i32_const(i32) -> i32 {
 block0(v0: i32):
@@ -514,6 +911,7 @@ block0(v0: i32):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -522,6 +920,16 @@ block0(v0: i32):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrl $1, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i16_const(i16) -> i16 {
 block0(v0: i16):
@@ -529,6 +937,7 @@ block0(v0: i16):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -537,6 +946,16 @@ block0(v0: i16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrw $1, %ax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %ushr_i8_const(i8) -> i8 {
 block0(v0: i8):
@@ -544,6 +963,7 @@ block0(v0: i8):
     return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -552,4 +972,14 @@ block0(v0: i8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movq %rdi, %rax
+;   shrb $1, %al
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/uunarrow.clif b/cranelift/filetests/filetests/isa/x64/uunarrow.clif
index f42e52ee08..604908f502 100644
--- a/cranelift/filetests/filetests/isa/x64/uunarrow.clif
+++ b/cranelift/filetests/filetests/isa/x64/uunarrow.clif
@@ -9,6 +9,7 @@ block0(v0: f64x2):
   return v3
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -24,4 +25,26 @@ block0(v0: f64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   xorpd %xmm2, %xmm2
+;   movdqa %xmm0, %xmm6
+;   maxpd %xmm2, %xmm6
+;   movupd 0x28(%rip), %xmm7
+;   minpd %xmm7, %xmm6
+;   roundpd $3, %xmm6, %xmm0
+;   movupd 0x25(%rip), %xmm12
+;   addpd %xmm12, %xmm0
+;   shufps $0x88, %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %al, (%rax)
+;   addb %ah, %al
 
diff --git a/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif b/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif
index f0de62903f..6be6db07d4 100644
--- a/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif
+++ b/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif
@@ -7,6 +7,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovmskb %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i8x16) -> i16 {
 block0(v0: i8x16):
@@ -21,6 +31,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovmskb %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i16x8) -> i8 {
 block0(v0: i16x8):
@@ -35,6 +55,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -45,6 +66,18 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm2
+;   packsswb %xmm0, %xmm2
+;   pmovmskb %xmm2, %eax
+;   shrq $8, %rax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i32x4) -> i8 {
 block0(v0: i32x4):
@@ -52,6 +85,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -59,6 +93,15 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movmskps %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i64x2) -> i8 {
 block0(v0: i64x2):
@@ -66,6 +109,7 @@ block0(v0: i64x2):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -73,4 +117,13 @@ block0(v0: i64x2):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movmskpd %xmm0, %eax
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif b/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif
index d6f381c85c..95532db790 100644
--- a/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif
+++ b/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif
@@ -8,6 +8,7 @@ block0(v0: i64, v2: i8x16):
     return v6
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -17,4 +18,15 @@ block0(v0: i64, v2: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqu 0x50(%rdi), %xmm3
+;   palignr $8, %xmm3, %xmm3
+;   pmovzxbw %xmm3, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/filetests/isa/x64/widening.clif b/cranelift/filetests/filetests/isa/x64/widening.clif
index e432267d07..2cfaaa38e6 100644
--- a/cranelift/filetests/filetests/isa/x64/widening.clif
+++ b/cranelift/filetests/filetests/isa/x64/widening.clif
@@ -7,6 +7,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -14,6 +15,15 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovsxbw %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f2(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -21,6 +31,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -28,6 +39,15 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovsxwd %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f3(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -35,6 +55,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -42,6 +63,15 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovsxdq %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f4(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -49,6 +79,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -58,6 +89,17 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm2
+;   palignr $8, %xmm0, %xmm2
+;   pmovsxbw %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f5(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -65,6 +107,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -74,6 +117,17 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm2
+;   palignr $8, %xmm0, %xmm2
+;   pmovsxwd %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f6(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -81,6 +135,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -89,6 +144,16 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0xee, %xmm0, %xmm2
+;   pmovsxdq %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f7(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -96,6 +161,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -103,6 +169,15 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovzxbw %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f8(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -110,6 +185,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -117,6 +193,15 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovzxwd %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f9(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -124,6 +209,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -131,6 +217,15 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pmovzxdq %xmm0, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f10(i8x16) -> i16x8 {
 block0(v0: i8x16):
@@ -138,6 +233,7 @@ block0(v0: i8x16):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -147,6 +243,17 @@ block0(v0: i8x16):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm2
+;   palignr $8, %xmm0, %xmm2
+;   pmovzxbw %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f11(i16x8) -> i32x4 {
 block0(v0: i16x8):
@@ -154,6 +261,7 @@ block0(v0: i16x8):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -163,6 +271,17 @@ block0(v0: i16x8):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   movdqa %xmm0, %xmm2
+;   palignr $8, %xmm0, %xmm2
+;   pmovzxwd %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
 function %f12(i32x4) -> i64x2 {
 block0(v0: i32x4):
@@ -170,6 +289,7 @@ block0(v0: i32x4):
   return v1
 }
 
+; VCode:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
@@ -178,4 +298,14 @@ block0(v0: i32x4):
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
+; 
+; Disassembled:
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block0: ; offset 0x4
+;   pshufd $0xee, %xmm0, %xmm2
+;   pmovzxdq %xmm2, %xmm0
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
 
diff --git a/cranelift/filetests/src/runone.rs b/cranelift/filetests/src/runone.rs
index 885b6742e2..c616f45384 100644
--- a/cranelift/filetests/src/runone.rs
+++ b/cranelift/filetests/src/runone.rs
@@ -38,6 +38,7 @@ pub fn run(
     let options = ParseOptions {
         target,
         passes,
+        machine_code_cfg_info: true,
         ..ParseOptions::default()
     };
 
diff --git a/cranelift/filetests/src/test_compile.rs b/cranelift/filetests/src/test_compile.rs
index cfc180ba9d..94c975c147 100644
--- a/cranelift/filetests/src/test_compile.rs
+++ b/cranelift/filetests/src/test_compile.rs
@@ -5,6 +5,9 @@
 use crate::subtest::{run_filecheck, Context, SubTest};
 use anyhow::{bail, Result};
 use cranelift_codegen::ir;
+use cranelift_codegen::ir::function::FunctionParameters;
+use cranelift_codegen::isa;
+use cranelift_codegen::CompiledCode;
 use cranelift_reader::{TestCommand, TestOption};
 use log::info;
 use similar::TextDiff;
@@ -48,6 +51,7 @@ impl SubTest for TestCompile {
 
     fn run(&self, func: Cow<ir::Function>, context: &Context) -> Result<()> {
         let isa = context.isa.expect("compile needs an ISA");
+        let params = func.params.clone();
         let mut comp_ctx = cranelift_codegen::Context::for_function(func.into_owned());
 
         // With `MachBackend`s, we need to explicitly request dissassembly results.
@@ -58,20 +62,35 @@ impl SubTest for TestCompile {
             .map_err(|e| crate::pretty_anyhow_error(&e.func, e.inner))?;
         let total_size = compiled_code.code_info().total_size;
 
-        let disasm = compiled_code.disasm.as_ref().unwrap();
+        let vcode = compiled_code.vcode.as_ref().unwrap();
 
-        info!("Generated {} bytes of code:\n{}", total_size, disasm);
+        info!("Generated {} bytes of code:\n{}", total_size, vcode);
 
         if self.precise_output {
-            check_precise_output(&disasm, context)
+            check_precise_output(isa, &params, &compiled_code, context)
         } else {
-            run_filecheck(&disasm, context)
+            run_filecheck(&vcode, context)
         }
     }
 }
 
-fn check_precise_output(text: &str, context: &Context) -> Result<()> {
-    let actual = text.lines().collect::<Vec<_>>();
+fn check_precise_output(
+    isa: &dyn isa::TargetIsa,
+    params: &FunctionParameters,
+    compiled_code: &CompiledCode,
+    context: &Context,
+) -> Result<()> {
+    let cs = isa
+        .to_capstone()
+        .map_err(|e| anyhow::format_err!("{}", e))?;
+    let dis = compiled_code.disassemble(Some(params), &cs)?;
+
+    let actual = Vec::from_iter(
+        std::iter::once("VCode:")
+            .chain(compiled_code.vcode.as_ref().unwrap().lines())
+            .chain(["", "Disassembled:"])
+            .chain(dis.lines()),
+    );
 
     // Use the comments after the function to build the test expectation.
     let expected = context
diff --git a/cranelift/filetests/src/test_wasm.rs b/cranelift/filetests/src/test_wasm.rs
index b246178e30..0ecba3510a 100644
--- a/cranelift/filetests/src/test_wasm.rs
+++ b/cranelift/filetests/src/test_wasm.rs
@@ -61,7 +61,7 @@ pub fn run(path: &Path, wat: &str) -> Result<()> {
                 .compile(isa)
                 .map_err(|e| crate::pretty_anyhow_error(&e.func, e.inner))?;
             writeln!(&mut actual, "function {}:", func.name).unwrap();
-            writeln!(&mut actual, "{}", code.disasm.as_ref().unwrap()).unwrap();
+            writeln!(&mut actual, "{}", code.vcode.as_ref().unwrap()).unwrap();
         } else if config.optimize {
             let mut ctx = cranelift_codegen::Context::for_function(func.clone());
             ctx.optimize(isa)
diff --git a/cranelift/reader/src/parser.rs b/cranelift/reader/src/parser.rs
index 91f4d50a64..c15693d516 100644
--- a/cranelift/reader/src/parser.rs
+++ b/cranelift/reader/src/parser.rs
@@ -97,6 +97,8 @@ pub struct ParseOptions<'a> {
     pub default_calling_convention: CallConv,
     /// Default for unwind-info setting (enabled or disabled).
     pub unwind_info: bool,
+    /// Default for machine_code_cfg_info setting (enabled or disabled).
+    pub machine_code_cfg_info: bool,
 }
 
 impl Default for ParseOptions<'_> {
@@ -106,6 +108,7 @@ impl Default for ParseOptions<'_> {
             target: None,
             default_calling_convention: CallConv::Fast,
             unwind_info: false,
+            machine_code_cfg_info: false,
         }
     }
 }
@@ -1046,9 +1049,24 @@ impl<'a> Parser<'a> {
         let mut targets = Vec::new();
         let mut flag_builder = settings::builder();
 
-        let unwind_info = if options.unwind_info { "true" } else { "false" };
+        let bool_to_str = |val: bool| {
+            if val {
+                "true"
+            } else {
+                "false"
+            }
+        };
+
+        // default to enabling cfg info
         flag_builder
-            .set("unwind_info", unwind_info)
+            .set(
+                "machine_code_cfg_info",
+                bool_to_str(options.machine_code_cfg_info),
+            )
+            .expect("machine_code_cfg_info option should be present");
+
+        flag_builder
+            .set("unwind_info", bool_to_str(options.unwind_info))
             .expect("unwind_info option should be present");
 
         while let Some(Token::Identifier(command)) = self.token() {
diff --git a/cranelift/src/disasm.rs b/cranelift/src/disasm.rs
index 67caf28bc3..1739f526b8 100644
--- a/cranelift/src/disasm.rs
+++ b/cranelift/src/disasm.rs
@@ -69,75 +69,8 @@ pub fn print_stack_maps(traps: &[MachStackMap]) -> String {
 
 cfg_if! {
     if #[cfg(feature = "disas")] {
-        use capstone::prelude::*;
-        use target_lexicon::Architecture;
-
-        fn get_disassembler(isa: &dyn TargetIsa) -> Result<Capstone> {
-            let cs = match isa.triple().architecture {
-                Architecture::X86_32(_) => Capstone::new()
-                    .x86()
-                    .mode(arch::x86::ArchMode::Mode32)
-                    .build()
-                    .map_err(map_caperr)?,
-                Architecture::X86_64 => Capstone::new()
-                    .x86()
-                    .mode(arch::x86::ArchMode::Mode64)
-                    .build()
-                    .map_err(map_caperr)?,
-                Architecture::Arm(arm) => {
-                    if arm.is_thumb() {
-                        Capstone::new()
-                            .arm()
-                            .mode(arch::arm::ArchMode::Thumb)
-                            .build()
-                            .map_err(map_caperr)?
-                    } else {
-                        Capstone::new()
-                            .arm()
-                            .mode(arch::arm::ArchMode::Arm)
-                            .build()
-                            .map_err(map_caperr)?
-                    }
-                }
-                Architecture::Aarch64 {..} => {
-                    let mut cs = Capstone::new()
-                        .arm64()
-                        .mode(arch::arm64::ArchMode::Arm)
-                        .build()
-                        .map_err(map_caperr)?;
-                    // AArch64 uses inline constants rather than a separate constant pool right now.
-                    // Without this option, Capstone will stop disassembling as soon as it sees
-                    // an inline constant that is not also a valid instruction. With this option,
-                    // Capstone will print a `.byte` directive with the bytes of the inline constant
-                    // and continue to the next instruction.
-                    cs.set_skipdata(true).map_err(map_caperr)?;
-                    cs
-                }
-                Architecture::S390x {..} => Capstone::new()
-                    .sysz()
-                    .mode(arch::sysz::ArchMode::Default)
-                    .build()
-                    .map_err(map_caperr)?,
-                Architecture::Riscv64 {..} => {
-                    let mut cs = Capstone::new()
-                        .riscv()
-                        .mode(arch::riscv::ArchMode::RiscV64)
-                        .build()
-                        .map_err(map_caperr)?;
-                    // Similar to AArch64, RISC-V uses inline constants rather than a separate
-                    // constant pool. We want to skip dissasembly over inline constants instead
-                    // of stopping on invalid bytes.
-                    cs.set_skipdata(true).map_err(map_caperr)?;
-                    cs
-                }
-                _ => anyhow::bail!("Unknown ISA"),
-            };
-
-            Ok(cs)
-        }
-
         pub fn print_disassembly(isa: &dyn TargetIsa, mem: &[u8]) -> Result<()> {
-            let cs = get_disassembler(isa)?;
+            let cs = isa.to_capstone().map_err(|e| anyhow::format_err!("{}", e))?;
 
             println!("\nDisassembly of {} bytes:", mem.len());
             let insns = cs.disasm_all(&mem, 0x0).unwrap();
@@ -174,10 +107,6 @@ cfg_if! {
             }
             Ok(())
         }
-
-        fn map_caperr(err: capstone::Error) -> anyhow::Error{
-            anyhow::format_err!("{}", err)
-        }
     } else {
         pub fn print_disassembly(_: &dyn TargetIsa, _: &[u8]) -> Result<()> {
             println!("\nNo disassembly available.");