arm64: Implement checks in division / remainder
This implements the divide by 0 and signed overflow checks that Wasm specifies. Copyright (c) 2020, Arm Limited.
This commit is contained in:
Joey Gouly
committed by
Benjamin Bouvier
Benjamin Bouvier
parent
b6e6998713
commit
f020f0812e
@@ -917,6 +917,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
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} else {
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NarrowValueMode::ZeroExtend64
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};
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// TODO: Add SDiv32 to implement 32-bit directly, rather
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// than extending the input.
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let div_op = if is_signed {
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ALUOp::SDiv64
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} else {
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@@ -925,16 +927,19 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], narrow_mode);
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if !is_rem {
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let rm = input_to_reg(ctx, inputs[1], narrow_mode);
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ctx.emit(Inst::AluRRR {
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alu_op: div_op,
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rd,
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rn,
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rm,
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});
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} else {
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let rm = input_to_reg(ctx, inputs[1], narrow_mode);
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let rm = input_to_reg(ctx, inputs[1], narrow_mode);
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// The div instruction does not trap on divide by zero or signed overflow
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// so checks are inserted below.
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//
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// div rd, rn, rm
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ctx.emit(Inst::AluRRR {
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alu_op: div_op,
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rd,
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rn,
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rm,
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});
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if is_rem {
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// Remainder (rn % rm) is implemented as:
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//
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// tmp = rn / rm
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@@ -943,13 +948,20 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
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// use 'rd' for tmp and you have:
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//
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// div rd, rn, rm ; rd = rn / rm
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// cbnz rm, #8 ; branch over trap
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// udf ; divide by zero
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// msub rd, rd, rm, rn ; rd = rn - rd * rm
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ctx.emit(Inst::AluRRR {
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alu_op: div_op,
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rd,
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rn,
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rm,
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// Check for divide by 0.
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let branch_size = 8;
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ctx.emit(Inst::CondBrLowered {
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target: BranchTarget::ResolvedOffset(branch_size),
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kind: CondBrKind::NotZero(rm),
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});
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let trap_info = (ctx.srcloc(insn), TrapCode::IntegerDivisionByZero);
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ctx.emit(Inst::Udf { trap_info });
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ctx.emit(Inst::AluRRRR {
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alu_op: ALUOp::MSub64,
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rd: rd,
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@@ -957,6 +969,65 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
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rm: rm,
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ra: rn,
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});
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} else {
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if div_op == ALUOp::SDiv64 {
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// cbz rm, #20
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// cmn rm, 1
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// ccmp rn, 1, #nzcv, eq
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// b.vc 12
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// udf ; signed overflow
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// udf ; divide by zero
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// Check for divide by 0.
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let branch_size = 20;
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ctx.emit(Inst::CondBrLowered {
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target: BranchTarget::ResolvedOffset(branch_size),
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kind: CondBrKind::Zero(rm),
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});
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// Check for signed overflow. The only case is min_value / -1.
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let ty = ty.unwrap();
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// The following checks must be done in 32-bit or 64-bit, depending
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// on the input type. Even though the initial div instruction is
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// always done in 64-bit currently.
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let size = InstSize::from_ty(ty);
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// Check RHS is -1.
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ctx.emit(Inst::AluRRImm12 {
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alu_op: choose_32_64(ty, ALUOp::AddS32, ALUOp::AddS64),
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rd: writable_zero_reg(),
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rn: rm,
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imm12: Imm12::maybe_from_u64(1).unwrap(),
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});
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// Check LHS is min_value, by subtracting 1 and branching if
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// there is overflow.
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ctx.emit(Inst::CCmpImm {
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size,
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rn,
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imm: UImm5::maybe_from_u8(1).unwrap(),
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nzcv: NZCV::new(false, false, false, false),
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cond: Cond::Eq,
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});
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ctx.emit(Inst::CondBrLowered {
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target: BranchTarget::ResolvedOffset(12),
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kind: CondBrKind::Cond(Cond::Vc),
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});
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let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow);
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ctx.emit(Inst::Udf { trap_info });
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} else {
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// cbnz rm, #8
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// udf ; divide by zero
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// Check for divide by 0.
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let branch_size = 8;
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ctx.emit(Inst::CondBrLowered {
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target: BranchTarget::ResolvedOffset(branch_size),
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kind: CondBrKind::NotZero(rm),
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});
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}
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let trap_info = (ctx.srcloc(insn), TrapCode::IntegerDivisionByZero);
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ctx.emit(Inst::Udf { trap_info });
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}
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}
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@@ -75,7 +75,14 @@ block0(v0: i64, v1: i64):
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x0, x0, x1
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; nextln: sdiv x2, x0, x1
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; nextln: cbz x1, 20
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; nextln: adds xzr, x1, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 12
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; nextln: udf
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; nextln: udf
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; nextln: mov x0, x2
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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@@ -89,8 +96,15 @@ block0(v0: i64):
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: sdiv x0, x0, x1
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; nextln: movz x2, #2
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; nextln: sdiv x1, x0, x2
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; nextln: cbz x2, 20
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; nextln: adds xzr, x2, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 12
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; nextln: udf
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; nextln: udf
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; nextln: mov x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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@@ -104,6 +118,8 @@ block0(v0: i64, v1: i64):
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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@@ -119,6 +135,8 @@ block0(v0: i64):
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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@@ -132,6 +150,8 @@ block0(v0: i64, v1: i64):
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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@@ -146,6 +166,126 @@ block0(v0: i64, v1: i64):
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x3, w0
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; nextln: sxtw x2, w1
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; nextln: sdiv x0, x3, x2
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; nextln: cbz x2, 20
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w3, #1, #nzcv, eq
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; nextln: b.vc 12
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; nextln: udf
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: movz x0, #2
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; nextln: sxtw x1, w1
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; nextln: sxtw x2, w0
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; nextln: sdiv x0, x1, x2
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; nextln: cbz x2, 20
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w1, #1, #nzcv, eq
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; nextln: b.vc 12
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; nextln: udf
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: sxtw x1, w1
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8
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; nextln: udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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