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Update to Rust 2018 edition (#632)

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* initial cargo fix run

* Upgrade cranelift-entity crate

* Upgrade bforest crate

* Upgrade the codegen crate

* Upgrade the faerie crate

* Upgrade the filetests crate

* Upgrade the codegen-meta crate

* Upgrade the frontend crate

* Upgrade the cranelift-module crate

* Upgrade the cranelift-native crate

* Upgrade the cranelift-preopt crate

* Upgrade the cranelift-reader crate

* Upgrade the cranelift-serde crate

* Upgrade the cranelift-simplejit crate

* Upgrade the cranelift or cranelift-umbrella crate

* Upgrade the cranelift-wasm crate

* Upgrade cranelift-tools crate

* Use new import style on remaining files

* run format-all.sh

* run test-all.sh, update Readme and travis ci configuration
fixed an AssertionError also

* Remove deprecated functions
This commit is contained in:
Muhammad Mominul Huque
2018-12-26 23:49:05 +06:00
committed by Dan Gohman
parent e3db942b0c
commit effe6c04e4
217 changed files with 963 additions and 1021 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/codegen/src/abi.rs
View File

@@ -3,7 +3,7 @@
//! This module provides functions and data structures that are useful for implementing the
//! `TargetIsa::legalize_signature()` method.
use ir::{AbiParam, ArgumentExtension, ArgumentLoc, Type};
use crate::ir::{AbiParam, ArgumentExtension, ArgumentLoc, Type};
use std::cmp::Ordering;
use std::vec::Vec;
@@ -182,8 +182,8 @@ pub fn legalize_abi_value(have: Type, arg: &AbiParam) -> ValueConversion {
#[cfg(test)]
mod tests {
use super::*;
use ir::types;
use ir::AbiParam;
use crate::ir::types;
use crate::ir::AbiParam;
#[test]
fn legalize() {

10
lib/codegen/src/binemit/memorysink.rs
View File

@@ -15,7 +15,7 @@
//! `CodeSink::put*` methods, so the performance impact of the virtual callbacks is less severe.
use super::{Addend, CodeOffset, CodeSink, Reloc};
use ir::{ExternalName, JumpTable, SourceLoc, TrapCode};
use crate::ir::{ExternalName, JumpTable, SourceLoc, TrapCode};
use std::ptr::write_unaligned;
/// A `CodeSink` that writes binary machine code directly into memory.
@@ -57,13 +57,13 @@ impl<'a> MemoryCodeSink<'a> {
/// A trait for receiving relocations for code that is emitted directly into memory.
pub trait RelocSink {
/// Add a relocation referencing an EBB at the current offset.
fn reloc_ebb(&mut self, CodeOffset, Reloc, CodeOffset);
fn reloc_ebb(&mut self, _: CodeOffset, _: Reloc, _: CodeOffset);
/// Add a relocation referencing an external symbol at the current offset.
fn reloc_external(&mut self, CodeOffset, Reloc, &ExternalName, Addend);
fn reloc_external(&mut self, _: CodeOffset, _: Reloc, _: &ExternalName, _: Addend);
/// Add a relocation referencing a jump table.
fn reloc_jt(&mut self, CodeOffset, Reloc, JumpTable);
fn reloc_jt(&mut self, _: CodeOffset, _: Reloc, _: JumpTable);
}
/// A trait for receiving trap codes and offsets.
@@ -72,7 +72,7 @@ pub trait RelocSink {
/// [`NullTrapSink`](binemit/trait.TrapSink.html) implementation.
pub trait TrapSink {
/// Add trap information for a specific offset.
fn trap(&mut self, CodeOffset, SourceLoc, TrapCode);
fn trap(&mut self, _: CodeOffset, _: SourceLoc, _: TrapCode);
}
impl<'a> CodeSink for MemoryCodeSink<'a> {

20
lib/codegen/src/binemit/mod.rs
View File

@@ -10,9 +10,9 @@ mod shrink;
pub use self::memorysink::{MemoryCodeSink, NullTrapSink, RelocSink, TrapSink};
pub use self::relaxation::relax_branches;
pub use self::shrink::shrink_instructions;
pub use regalloc::RegDiversions;
pub use crate::regalloc::RegDiversions;
use ir::{ExternalName, Function, Inst, JumpTable, SourceLoc, TrapCode};
use crate::ir::{ExternalName, Function, Inst, JumpTable, SourceLoc, TrapCode};
use std::fmt;
/// Offset in bytes from the beginning of the function.
@@ -72,28 +72,28 @@ pub trait CodeSink {
fn offset(&self) -> CodeOffset;
/// Add 1 byte to the code section.
fn put1(&mut self, u8);
fn put1(&mut self, _: u8);
/// Add 2 bytes to the code section.
fn put2(&mut self, u16);
fn put2(&mut self, _: u16);
/// Add 4 bytes to the code section.
fn put4(&mut self, u32);
fn put4(&mut self, _: u32);
/// Add 8 bytes to the code section.
fn put8(&mut self, u64);
fn put8(&mut self, _: u64);
/// Add a relocation referencing an EBB at the current offset.
fn reloc_ebb(&mut self, Reloc, CodeOffset);
fn reloc_ebb(&mut self, _: Reloc, _: CodeOffset);
/// Add a relocation referencing an external symbol plus the addend at the current offset.
fn reloc_external(&mut self, Reloc, &ExternalName, Addend);
fn reloc_external(&mut self, _: Reloc, _: &ExternalName, _: Addend);
/// Add a relocation referencing a jump table.
fn reloc_jt(&mut self, Reloc, JumpTable);
fn reloc_jt(&mut self, _: Reloc, _: JumpTable);
/// Add trap information for the current offset.
fn trap(&mut self, TrapCode, SourceLoc);
fn trap(&mut self, _: TrapCode, _: SourceLoc);
/// Code output is complete, read-only data may follow.
fn begin_rodata(&mut self);

17
lib/codegen/src/binemit/relaxation.rs
View File

@@ -27,14 +27,15 @@
//! ebb23:
//! ```
use binemit::CodeOffset;
use cursor::{Cursor, FuncCursor};
use ir::{Function, InstructionData, Opcode};
use isa::{EncInfo, TargetIsa};
use iterators::IteratorExtras;
use regalloc::RegDiversions;
use timing;
use CodegenResult;
use crate::binemit::CodeOffset;
use crate::cursor::{Cursor, FuncCursor};
use crate::ir::{Function, InstructionData, Opcode};
use crate::isa::{EncInfo, TargetIsa};
use crate::iterators::IteratorExtras;
use crate::regalloc::RegDiversions;
use crate::timing;
use crate::CodegenResult;
use log::debug;
/// Relax branches and compute the final layout of EBB headers in `func`.
///

11
lib/codegen/src/binemit/shrink.rs
View File

@@ -5,11 +5,12 @@
//! flexibility. However, once register allocation is done, this is no longer important, and we
//! can switch to smaller encodings when possible.
use ir::instructions::InstructionData;
use ir::Function;
use isa::TargetIsa;
use regalloc::RegDiversions;
use timing;
use crate::ir::instructions::InstructionData;
use crate::ir::Function;
use crate::isa::TargetIsa;
use crate::regalloc::RegDiversions;
use crate::timing;
use log::debug;
/// Pick the smallest valid encodings for instructions.
pub fn shrink_instructions(func: &mut Function, isa: &TargetIsa) {

6
lib/codegen/src/cfg_printer.rs
View File

@@ -2,9 +2,9 @@
use std::fmt::{Display, Formatter, Result, Write};
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::instructions::BranchInfo;
use ir::Function;
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::instructions::BranchInfo;
use crate::ir::Function;
/// A utility for pretty-printing the CFG of a `Function`.
pub struct CFGPrinter<'a> {

38
lib/codegen/src/context.rs
View File

@@ -9,28 +9,28 @@
//! contexts concurrently. Typically, you would have one context per compilation thread and only a
//! single ISA instance.
use binemit::{
use crate::binemit::{
relax_branches, shrink_instructions, CodeOffset, MemoryCodeSink, RelocSink, TrapSink,
};
use dce::do_dce;
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::Function;
use isa::TargetIsa;
use legalize_function;
use licm::do_licm;
use loop_analysis::LoopAnalysis;
use nan_canonicalization::do_nan_canonicalization;
use postopt::do_postopt;
use regalloc;
use result::CodegenResult;
use settings::{FlagsOrIsa, OptLevel};
use simple_gvn::do_simple_gvn;
use simple_preopt::do_preopt;
use crate::dce::do_dce;
use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir::Function;
use crate::isa::TargetIsa;
use crate::legalize_function;
use crate::licm::do_licm;
use crate::loop_analysis::LoopAnalysis;
use crate::nan_canonicalization::do_nan_canonicalization;
use crate::postopt::do_postopt;
use crate::regalloc;
use crate::result::CodegenResult;
use crate::settings::{FlagsOrIsa, OptLevel};
use crate::simple_gvn::do_simple_gvn;
use crate::simple_preopt::do_preopt;
use crate::timing;
use crate::unreachable_code::eliminate_unreachable_code;
use crate::verifier::{verify_context, verify_locations, VerifierErrors, VerifierResult};
use std::vec::Vec;
use timing;
use unreachable_code::eliminate_unreachable_code;
use verifier::{verify_context, verify_locations, VerifierErrors, VerifierResult};
/// Persistent data structures and compilation pipeline.
pub struct Context {

4
lib/codegen/src/cursor.rs
View File

@@ -2,8 +2,8 @@
//!
//! This module defines cursor data types that can be used for inserting instructions.
use ir;
use isa::TargetIsa;
use crate::ir;
use crate::isa::TargetIsa;
/// The possible positions of a cursor.
#[derive(Clone, Copy, PartialEq, Eq, Debug)]

12
lib/codegen/src/dce.rs
View File

@@ -3,13 +3,13 @@
//! Dead code here means instructions that have no side effects and have no
//! result values used by other instructions.
use cursor::{Cursor, FuncCursor};
use dominator_tree::DominatorTree;
use entity::EntityRef;
use ir::instructions::InstructionData;
use ir::{DataFlowGraph, Function, Inst, Opcode};
use crate::cursor::{Cursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::entity::EntityRef;
use crate::ir::instructions::InstructionData;
use crate::ir::{DataFlowGraph, Function, Inst, Opcode};
use crate::timing;
use std::vec::Vec;
use timing;
/// Test whether the given opcode is unsafe to even consider for DCE.
fn trivially_unsafe_for_dce(opcode: Opcode) -> bool {

24
lib/codegen/src/dominator_tree.rs
View File

@@ -1,15 +1,15 @@
//! A Dominator Tree represented as mappings of Ebbs to their immediate dominator.
use entity::SecondaryMap;
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::instructions::BranchInfo;
use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
use packed_option::PackedOption;
use crate::entity::SecondaryMap;
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::instructions::BranchInfo;
use crate::ir::{Ebb, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
use crate::packed_option::PackedOption;
use crate::timing;
use std::cmp;
use std::cmp::Ordering;
use std::mem;
use std::vec::Vec;
use timing;
/// RPO numbers are not first assigned in a contiguous way but as multiples of STRIDE, to leave
/// room for modifications of the dominator tree.
@@ -671,12 +671,12 @@ impl DominatorTreePreorder {
#[cfg(test)]
mod tests {
use super::*;
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::types::*;
use ir::{Function, InstBuilder, TrapCode};
use settings;
use verifier::{verify_context, VerifierErrors};
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::types::*;
use crate::ir::{Function, InstBuilder, TrapCode};
use crate::settings;
use crate::verifier::{verify_context, VerifierErrors};
#[test]
fn empty() {

14
lib/codegen/src/flowgraph.rs
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@@ -23,12 +23,12 @@
//! Here `Ebb1` and `Ebb2` would each have a single predecessor denoted as `(Ebb0, brz)`
//! and `(Ebb0, jmp Ebb2)` respectively.
use bforest;
use entity::SecondaryMap;
use ir::instructions::BranchInfo;
use ir::{Ebb, Function, Inst};
use crate::bforest;
use crate::entity::SecondaryMap;
use crate::ir::instructions::BranchInfo;
use crate::ir::{Ebb, Function, Inst};
use crate::timing;
use std::mem;
use timing;
/// A basic block denoted by its enclosing Ebb and last instruction.
#[derive(PartialEq, Eq)]
@@ -212,8 +212,8 @@ pub type SuccIter<'a> = bforest::SetIter<'a, Ebb>;
#[cfg(test)]
mod tests {
use super::*;
use cursor::{Cursor, FuncCursor};
use ir::{types, Function, InstBuilder};
use crate::cursor::{Cursor, FuncCursor};
use crate::ir::{types, Function, InstBuilder};
use std::vec::Vec;
#[test]

18
lib/codegen/src/ir/builder.rs
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@@ -3,11 +3,11 @@
//! A `Builder` provides a convenient interface for inserting instructions into a Cranelift
//! function. Many of its methods are generated from the meta language instruction definitions.
use ir;
use ir::types;
use ir::{DataFlowGraph, InstructionData};
use ir::{Inst, Opcode, Type, Value};
use isa;
use crate::ir;
use crate::ir::types;
use crate::ir::{DataFlowGraph, InstructionData};
use crate::ir::{Inst, Opcode, Type, Value};
use crate::isa;
/// Base trait for instruction builders.
///
@@ -215,10 +215,10 @@ impl<'f> InstBuilderBase<'f> for ReplaceBuilder<'f> {
#[cfg(test)]
mod tests {
use cursor::{Cursor, FuncCursor};
use ir::condcodes::*;
use ir::types::*;
use ir::{Function, InstBuilder, ValueDef};
use crate::cursor::{Cursor, FuncCursor};
use crate::ir::condcodes::*;
use crate::ir::types::*;
use crate::ir::{Function, InstBuilder, ValueDef};
#[test]
fn types() {

30
lib/codegen/src/ir/dfg.rs
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@@ -1,20 +1,20 @@
//! Data flow graph tracking Instructions, Values, and EBBs.
use entity::{self, PrimaryMap, SecondaryMap};
use ir;
use ir::builder::ReplaceBuilder;
use ir::extfunc::ExtFuncData;
use ir::instructions::{BranchInfo, CallInfo, InstructionData};
use ir::types;
use ir::{Ebb, FuncRef, Inst, SigRef, Signature, Type, Value, ValueList, ValueListPool};
use isa::TargetIsa;
use packed_option::ReservedValue;
use crate::entity::{self, PrimaryMap, SecondaryMap};
use crate::ir;
use crate::ir::builder::ReplaceBuilder;
use crate::ir::extfunc::ExtFuncData;
use crate::ir::instructions::{BranchInfo, CallInfo, InstructionData};
use crate::ir::types;
use crate::ir::{Ebb, FuncRef, Inst, SigRef, Signature, Type, Value, ValueList, ValueListPool};
use crate::isa::TargetIsa;
use crate::packed_option::ReservedValue;
use crate::write::write_operands;
use std::fmt;
use std::iter;
use std::mem;
use std::ops::{Index, IndexMut};
use std::u16;
use write::write_operands;
/// A data flow graph defines all instructions and extended basic blocks in a function as well as
/// the data flow dependencies between them. The DFG also tracks values which can be either
@@ -1063,9 +1063,9 @@ impl DataFlowGraph {
#[cfg(test)]
mod tests {
use super::*;
use cursor::{Cursor, FuncCursor};
use ir::types;
use ir::{Function, InstructionData, Opcode, TrapCode};
use crate::cursor::{Cursor, FuncCursor};
use crate::ir::types;
use crate::ir::{Function, InstructionData, Opcode, TrapCode};
use std::string::ToString;
#[test]
@@ -1218,8 +1218,8 @@ mod tests {
#[test]
fn aliases() {
use ir::condcodes::IntCC;
use ir::InstBuilder;
use crate::ir::condcodes::IntCC;
use crate::ir::InstBuilder;
let mut func = Function::new();
let ebb0 = func.dfg.make_ebb();

3
lib/codegen/src/ir/entities.rs
View File

@@ -19,6 +19,7 @@
//! The entity references all implement the `Display` trait in a way that matches the textual IR
//! format.
use crate::entity::entity_impl;
use std::fmt;
use std::u32;
@@ -318,7 +319,7 @@ mod tests {
#[test]
fn memory() {
use packed_option::PackedOption;
use crate::packed_option::PackedOption;
use std::mem;
// This is the whole point of `PackedOption`.
assert_eq!(

6
lib/codegen/src/ir/extfunc.rs
View File

@@ -5,8 +5,8 @@
//!
//! This module declares the data types used to represent external functions and call signatures.
use ir::{ArgumentLoc, ExternalName, SigRef, Type};
use isa::{CallConv, RegInfo, RegUnit};
use crate::ir::{ArgumentLoc, ExternalName, SigRef, Type};
use crate::isa::{CallConv, RegInfo, RegUnit};
use std::fmt;
use std::str::FromStr;
use std::vec::Vec;
@@ -334,7 +334,7 @@ impl fmt::Display for ExtFuncData {
#[cfg(test)]
mod tests {
use super::*;
use ir::types::{B8, F32, I32};
use crate::ir::types::{B8, F32, I32};
use std::string::ToString;
#[test]

4
lib/codegen/src/ir/extname.rs
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@@ -4,7 +4,7 @@
//! function. The name of an external declaration doesn't have any meaning to
//! Cranelift, which compiles functions independently.
use ir::LibCall;
use crate::ir::LibCall;
use std::cmp;
use std::fmt::{self, Write};
use std::str::FromStr;
@@ -119,7 +119,7 @@ impl FromStr for ExternalName {
#[cfg(test)]
mod tests {
use super::ExternalName;
use ir::LibCall;
use crate::ir::LibCall;
use std::string::ToString;
use std::u32;

20
lib/codegen/src/ir/function.rs
View File

@@ -3,20 +3,20 @@
//! The `Function` struct defined in this module owns all of its extended basic blocks and
//! instructions.
use binemit::CodeOffset;
use entity::{PrimaryMap, SecondaryMap};
use ir;
use ir::{DataFlowGraph, ExternalName, Layout, Signature};
use ir::{
use crate::binemit::CodeOffset;
use crate::entity::{PrimaryMap, SecondaryMap};
use crate::ir;
use crate::ir::{DataFlowGraph, ExternalName, Layout, Signature};
use crate::ir::{
Ebb, ExtFuncData, FuncRef, GlobalValue, GlobalValueData, Heap, HeapData, JumpTable,
JumpTableData, SigRef, StackSlot, StackSlotData, Table, TableData,
};
use ir::{EbbOffsets, InstEncodings, SourceLocs, StackSlots, ValueLocations};
use ir::{JumpTableOffsets, JumpTables};
use isa::{CallConv, EncInfo, Encoding, Legalize, TargetIsa};
use regalloc::RegDiversions;
use crate::ir::{EbbOffsets, InstEncodings, SourceLocs, StackSlots, ValueLocations};
use crate::ir::{JumpTableOffsets, JumpTables};
use crate::isa::{CallConv, EncInfo, Encoding, Legalize, TargetIsa};
use crate::regalloc::RegDiversions;
use crate::write::write_function;
use std::fmt;
use write::write_function;
/// A function.
///

6
lib/codegen/src/ir/globalvalue.rs
View File

@@ -1,8 +1,8 @@
//! Global values.
use ir::immediates::{Imm64, Offset32};
use ir::{ExternalName, GlobalValue, Type};
use isa::TargetIsa;
use crate::ir::immediates::{Imm64, Offset32};
use crate::ir::{ExternalName, GlobalValue, Type};
use crate::isa::TargetIsa;
use std::fmt;
/// Information about a global value declaration.

4
lib/codegen/src/ir/heap.rs
View File

@@ -1,7 +1,7 @@
//! Heaps.
use ir::immediates::Uimm64;
use ir::{GlobalValue, Type};
use crate::ir::immediates::Uimm64;
use crate::ir::{GlobalValue, Type};
use std::fmt;
/// Information about a heap declaration.

18
lib/codegen/src/ir/instructions.rs
View File

@@ -11,14 +11,14 @@ use std::ops::{Deref, DerefMut};
use std::str::FromStr;
use std::vec::Vec;
use ir;
use ir::types;
use ir::{Ebb, FuncRef, JumpTable, SigRef, Type, Value};
use isa;
use crate::ir;
use crate::ir::types;
use crate::ir::{Ebb, FuncRef, JumpTable, SigRef, Type, Value};
use crate::isa;
use bitset::BitSet;
use entity;
use ref_slice::{ref_slice, ref_slice_mut};
use crate::bitset::BitSet;
use crate::entity;
use crate::ref_slice::{ref_slice, ref_slice_mut};
/// Some instructions use an external list of argument values because there is not enough space in
/// the 16-byte `InstructionData` struct. These value lists are stored in a memory pool in
@@ -73,7 +73,7 @@ impl FromStr for Opcode {
/// Parse an Opcode name from a string.
fn from_str(s: &str) -> Result<Self, &'static str> {
use constant_hash::{probe, simple_hash, Table};
use crate::constant_hash::{probe, simple_hash, Table};
impl<'a> Table<&'a str> for [Option<Opcode>] {
fn len(&self) -> usize {
@@ -645,7 +645,7 @@ mod tests {
#[test]
fn value_set() {
use ir::types::*;
use crate::ir::types::*;
let vts = ValueTypeSet {
lanes: BitSet16::from_range(0, 8),

6
lib/codegen/src/ir/jumptable.rs
View File

@@ -3,7 +3,7 @@
//! Jump tables are declared in the preamble and assigned an `ir::entities::JumpTable` reference.
//! The actual table of destinations is stored in a `JumpTableData` struct defined in this module.
use ir::entities::Ebb;
use crate::ir::entities::Ebb;
use std::fmt::{self, Display, Formatter};
use std::slice::{Iter, IterMut};
use std::vec::Vec;
@@ -83,8 +83,8 @@ impl Display for JumpTableData {
#[cfg(test)]
mod tests {
use super::JumpTableData;
use entity::EntityRef;
use ir::Ebb;
use crate::entity::EntityRef;
use crate::ir::Ebb;
use std::string::ToString;
#[test]

17
lib/codegen/src/ir/layout.rs
View File

@@ -3,13 +3,14 @@
//! The order of extended basic blocks in a function and the order of instructions in an EBB is
//! determined by the `Layout` data structure defined in this module.
use entity::SecondaryMap;
use ir::progpoint::{ExpandedProgramPoint, ProgramOrder};
use ir::{Ebb, Inst};
use packed_option::PackedOption;
use crate::entity::SecondaryMap;
use crate::ir::progpoint::{ExpandedProgramPoint, ProgramOrder};
use crate::ir::{Ebb, Inst};
use crate::packed_option::PackedOption;
use crate::timing;
use log::debug;
use std::cmp;
use std::iter::{IntoIterator, Iterator};
use timing;
/// The `Layout` struct determines the layout of EBBs and instructions in a function. It does not
/// contain definitions of instructions or EBBs, but depends on `Inst` and `Ebb` entity references
@@ -741,9 +742,9 @@ impl<'f> DoubleEndedIterator for Insts<'f> {
#[cfg(test)]
mod tests {
use super::Layout;
use cursor::{Cursor, CursorPosition};
use entity::EntityRef;
use ir::{Ebb, Inst, ProgramOrder, SourceLoc};
use crate::cursor::{Cursor, CursorPosition};
use crate::entity::EntityRef;
use crate::ir::{Ebb, Inst, ProgramOrder, SourceLoc};
use std::cmp::Ordering;
use std::vec::Vec;

4
lib/codegen/src/ir/libcall.rs
View File

@@ -1,10 +1,10 @@
//! Naming well-known routines in the runtime library.
use ir::{
use crate::ir::{
types, AbiParam, ArgumentPurpose, ExtFuncData, ExternalName, FuncRef, Function, Inst, Opcode,
Signature, Type,
};
use isa::{CallConv, RegUnit, TargetIsa};
use crate::isa::{CallConv, RegUnit, TargetIsa};
use std::fmt;
use std::str::FromStr;

50
lib/codegen/src/ir/mod.rs
View File

@@ -23,32 +23,36 @@ mod trapcode;
pub mod types;
mod valueloc;
pub use ir::builder::{InsertBuilder, InstBuilder, InstBuilderBase, InstInserterBase};
pub use ir::dfg::{DataFlowGraph, ValueDef};
pub use ir::entities::{
pub use crate::ir::builder::{InsertBuilder, InstBuilder, InstBuilderBase, InstInserterBase};
pub use crate::ir::dfg::{DataFlowGraph, ValueDef};
pub use crate::ir::entities::{
Ebb, FuncRef, GlobalValue, Heap, Inst, JumpTable, SigRef, StackSlot, Table, Value,
};
pub use ir::extfunc::{AbiParam, ArgumentExtension, ArgumentPurpose, ExtFuncData, Signature};
pub use ir::extname::ExternalName;
pub use ir::function::Function;
pub use ir::globalvalue::GlobalValueData;
pub use ir::heap::{HeapData, HeapStyle};
pub use ir::instructions::{InstructionData, Opcode, ValueList, ValueListPool, VariableArgs};
pub use ir::jumptable::JumpTableData;
pub use ir::layout::Layout;
pub use ir::libcall::{get_libcall_funcref, get_probestack_funcref, LibCall};
pub use ir::memflags::MemFlags;
pub use ir::progpoint::{ExpandedProgramPoint, ProgramOrder, ProgramPoint};
pub use ir::sourceloc::SourceLoc;
pub use ir::stackslot::{StackSlotData, StackSlotKind, StackSlots};
pub use ir::table::TableData;
pub use ir::trapcode::TrapCode;
pub use ir::types::Type;
pub use ir::valueloc::{ArgumentLoc, ValueLoc};
pub use crate::ir::extfunc::{
AbiParam, ArgumentExtension, ArgumentPurpose, ExtFuncData, Signature,
};
pub use crate::ir::extname::ExternalName;
pub use crate::ir::function::Function;
pub use crate::ir::globalvalue::GlobalValueData;
pub use crate::ir::heap::{HeapData, HeapStyle};
pub use crate::ir::instructions::{
InstructionData, Opcode, ValueList, ValueListPool, VariableArgs,
};
pub use crate::ir::jumptable::JumpTableData;
pub use crate::ir::layout::Layout;
pub use crate::ir::libcall::{get_libcall_funcref, get_probestack_funcref, LibCall};
pub use crate::ir::memflags::MemFlags;
pub use crate::ir::progpoint::{ExpandedProgramPoint, ProgramOrder, ProgramPoint};
pub use crate::ir::sourceloc::SourceLoc;
pub use crate::ir::stackslot::{StackSlotData, StackSlotKind, StackSlots};
pub use crate::ir::table::TableData;
pub use crate::ir::trapcode::TrapCode;
pub use crate::ir::types::Type;
pub use crate::ir::valueloc::{ArgumentLoc, ValueLoc};
use binemit;
use entity::{PrimaryMap, SecondaryMap};
use isa;
use crate::binemit;
use crate::entity::{PrimaryMap, SecondaryMap};
use crate::isa;
/// Map of value locations.
pub type ValueLocations = SecondaryMap<Value, ValueLoc>;

8
lib/codegen/src/ir/progpoint.rs
View File

@@ -1,7 +1,7 @@
//! Program points.
use entity::EntityRef;
use ir::{Ebb, Inst, ValueDef};
use crate::entity::EntityRef;
use crate::ir::{Ebb, Inst, ValueDef};
use std::cmp;
use std::fmt;
use std::u32;
@@ -146,8 +146,8 @@ pub trait ProgramOrder {
#[cfg(test)]
mod tests {
use super::*;
use entity::EntityRef;
use ir::{Ebb, Inst};
use crate::entity::EntityRef;
use crate::ir::{Ebb, Inst};
use std::string::ToString;
#[test]

2
lib/codegen/src/ir/sourceloc.rs
View File

@@ -50,7 +50,7 @@ impl fmt::Display for SourceLoc {
#[cfg(test)]
mod tests {
use ir::SourceLoc;
use crate::ir::SourceLoc;
use std::string::ToString;
#[test]

10
lib/codegen/src/ir/stackslot.rs
View File

@@ -3,9 +3,9 @@
//! The `StackSlotData` struct keeps track of a single stack slot in a function.
//!
use entity::{Iter, IterMut, Keys, PrimaryMap};
use ir::{StackSlot, Type};
use packed_option::PackedOption;
use crate::entity::{Iter, IterMut, Keys, PrimaryMap};
use crate::ir::{StackSlot, Type};
use crate::packed_option::PackedOption;
use std::cmp;
use std::fmt;
use std::ops::{Index, IndexMut};
@@ -340,8 +340,8 @@ impl StackSlots {
#[cfg(test)]
mod tests {
use super::*;
use ir::types;
use ir::Function;
use crate::ir::types;
use crate::ir::Function;
use std::string::ToString;
#[test]

4
lib/codegen/src/ir/table.rs
View File

@@ -1,7 +1,7 @@
//! Tables.
use ir::immediates::Uimm64;
use ir::{GlobalValue, Type};
use crate::ir::immediates::Uimm64;
use crate::ir::{GlobalValue, Type};
use std::fmt;
/// Information about a table declaration.

4
lib/codegen/src/ir/valueloc.rs
View File

@@ -3,8 +3,8 @@
//! The register allocator assigns every SSA value to either a register or a stack slot. This
//! assignment is represented by a `ValueLoc` object.
use ir::StackSlot;
use isa::{RegInfo, RegUnit};
use crate::ir::StackSlot;
use crate::isa::{RegInfo, RegUnit};
use std::fmt;
/// Value location.

8
lib/codegen/src/isa/arm32/abi.rs
View File

@@ -1,10 +1,10 @@
//! ARM ABI implementation.
use super::registers::{D, GPR, Q, S};
use ir;
use isa::RegClass;
use regalloc::RegisterSet;
use settings as shared_settings;
use crate::ir;
use crate::isa::RegClass;
use crate::regalloc::RegisterSet;
use crate::settings as shared_settings;
/// Legalize `sig`.
pub fn legalize_signature(

6
lib/codegen/src/isa/arm32/binemit.rs
View File

@@ -1,7 +1,7 @@
//! Emitting binary ARM32 machine code.
use binemit::{bad_encoding, CodeSink};
use ir::{Function, Inst};
use regalloc::RegDiversions;
use crate::binemit::{bad_encoding, CodeSink};
use crate::ir::{Function, Inst};
use crate::regalloc::RegDiversions;
include!(concat!(env!("OUT_DIR"), "/binemit-arm32.rs"));

9
lib/codegen/src/isa/arm32/enc_tables.rs
View File

@@ -1,10 +1,9 @@
//! Encoding tables for ARM32 ISA.
use ir;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
use crate::isa;
use crate::isa::constraints::*;
use crate::isa::enc_tables::*;
use crate::isa::encoding::RecipeSizing;
include!(concat!(env!("OUT_DIR"), "/encoding-arm32.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-arm32.rs"));

14
lib/codegen/src/isa/arm32/mod.rs
View File

@@ -8,13 +8,13 @@ pub mod settings;
use super::super::settings as shared_settings;
#[cfg(feature = "testing_hooks")]
use binemit::CodeSink;
use binemit::{emit_function, MemoryCodeSink};
use ir;
use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use isa::Builder as IsaBuilder;
use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use regalloc;
use crate::binemit::CodeSink;
use crate::binemit::{emit_function, MemoryCodeSink};
use crate::ir;
use crate::isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use crate::isa::Builder as IsaBuilder;
use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use crate::regalloc;
use std::boxed::Box;
use std::fmt;
use target_lexicon::{Architecture, Triple};

6
lib/codegen/src/isa/arm32/registers.rs
View File

@@ -1,13 +1,13 @@
//! ARM32 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
use crate::isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));
#[cfg(test)]
mod tests {
use super::{D, GPR, INFO, S};
use isa::RegUnit;
use crate::isa::RegUnit;
use std::string::{String, ToString};
#[test]
@@ -34,7 +34,7 @@ mod tests {
#[test]
fn overlaps() {
// arm32 has the most interesting register geometries, so test `regs_overlap()` here.
use isa::regs_overlap;
use crate::isa::regs_overlap;
let r0 = GPR.unit(0);
let r1 = GPR.unit(1);

2
lib/codegen/src/isa/arm32/settings.rs
View File

@@ -1,6 +1,6 @@
//! ARM32 Settings.
use settings::{self, detail, Builder};
use crate::settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public

8
lib/codegen/src/isa/arm64/abi.rs
View File

@@ -1,10 +1,10 @@
//! ARM 64 ABI implementation.
use super::registers::{FPR, GPR};
use ir;
use isa::RegClass;
use regalloc::RegisterSet;
use settings as shared_settings;
use crate::ir;
use crate::isa::RegClass;
use crate::regalloc::RegisterSet;
use crate::settings as shared_settings;
/// Legalize `sig`.
pub fn legalize_signature(

6
lib/codegen/src/isa/arm64/binemit.rs
View File

@@ -1,7 +1,7 @@
//! Emitting binary ARM64 machine code.
use binemit::{bad_encoding, CodeSink};
use ir::{Function, Inst};
use regalloc::RegDiversions;
use crate::binemit::{bad_encoding, CodeSink};
use crate::ir::{Function, Inst};
use crate::regalloc::RegDiversions;
include!(concat!(env!("OUT_DIR"), "/binemit-arm64.rs"));

9
lib/codegen/src/isa/arm64/enc_tables.rs
View File

@@ -1,10 +1,9 @@
//! Encoding tables for ARM64 ISA.
use ir;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
use crate::isa;
use crate::isa::constraints::*;
use crate::isa::enc_tables::*;
use crate::isa::encoding::RecipeSizing;
include!(concat!(env!("OUT_DIR"), "/encoding-arm64.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-arm64.rs"));

14
lib/codegen/src/isa/arm64/mod.rs
View File

@@ -8,13 +8,13 @@ pub mod settings;
use super::super::settings as shared_settings;
#[cfg(feature = "testing_hooks")]
use binemit::CodeSink;
use binemit::{emit_function, MemoryCodeSink};
use ir;
use isa::enc_tables::{lookup_enclist, Encodings};
use isa::Builder as IsaBuilder;
use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use regalloc;
use crate::binemit::CodeSink;
use crate::binemit::{emit_function, MemoryCodeSink};
use crate::ir;
use crate::isa::enc_tables::{lookup_enclist, Encodings};
use crate::isa::Builder as IsaBuilder;
use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use crate::regalloc;
use std::boxed::Box;
use std::fmt;
use target_lexicon::Triple;

4
lib/codegen/src/isa/arm64/registers.rs
View File

@@ -1,13 +1,13 @@
//! ARM64 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
use crate::isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));
#[cfg(test)]
mod tests {
use super::INFO;
use isa::RegUnit;
use crate::isa::RegUnit;
use std::string::{String, ToString};
#[test]

2
lib/codegen/src/isa/arm64/settings.rs
View File

@@ -1,6 +1,6 @@
//! ARM64 Settings.
use settings::{self, detail, Builder};
use crate::settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public

8
lib/codegen/src/isa/constraints.rs
View File

@@ -7,10 +7,10 @@
//! It is the register allocator's job to make sure that the register constraints on value operands
//! are satisfied.
use binemit::CodeOffset;
use ir::{Function, Inst, ValueLoc};
use isa::{RegClass, RegUnit};
use regalloc::RegDiversions;
use crate::binemit::CodeOffset;
use crate::ir::{Function, Inst, ValueLoc};
use crate::isa::{RegClass, RegUnit};
use crate::regalloc::RegDiversions;
/// Register constraint for a single value operand or instruction result.
#[derive(PartialEq, Debug)]

8
lib/codegen/src/isa/enc_tables.rs
View File

@@ -3,10 +3,10 @@
//! This module contains types and functions for working with the encoding tables generated by
//! `lib/codegen/meta-python/gen_encoding.py`.
use constant_hash::{probe, Table};
use ir::{Function, InstructionData, Opcode, Type};
use isa::{Encoding, Legalize};
use settings::PredicateView;
use crate::constant_hash::{probe, Table};
use crate::ir::{Function, InstructionData, Opcode, Type};
use crate::isa::{Encoding, Legalize};
use crate::settings::PredicateView;
use std::ops::Range;
/// A recipe predicate.

8
lib/codegen/src/isa/encoding.rs
View File

@@ -1,9 +1,9 @@
//! The `Encoding` struct.
use binemit::CodeOffset;
use ir::{Function, Inst};
use isa::constraints::{BranchRange, RecipeConstraints};
use regalloc::RegDiversions;
use crate::binemit::CodeOffset;
use crate::ir::{Function, Inst};
use crate::isa::constraints::{BranchRange, RecipeConstraints};
use crate::regalloc::RegDiversions;
use std::fmt;
/// Bits needed to encode an instruction as binary machine code.

35
lib/codegen/src/isa/mod.rs
View File

@@ -46,24 +46,27 @@
//! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
//! concurrent function compilations.
pub use isa::call_conv::CallConv;
pub use isa::constraints::{BranchRange, ConstraintKind, OperandConstraint, RecipeConstraints};
pub use isa::encoding::{base_size, EncInfo, Encoding};
pub use isa::registers::{regs_overlap, RegClass, RegClassIndex, RegInfo, RegUnit};
pub use isa::stack::{StackBase, StackBaseMask, StackRef};
pub use crate::isa::call_conv::CallConv;
pub use crate::isa::constraints::{
BranchRange, ConstraintKind, OperandConstraint, RecipeConstraints,
};
pub use crate::isa::encoding::{base_size, EncInfo, Encoding};
pub use crate::isa::registers::{regs_overlap, RegClass, RegClassIndex, RegInfo, RegUnit};
pub use crate::isa::stack::{StackBase, StackBaseMask, StackRef};
use binemit;
use flowgraph;
use ir;
use isa::enc_tables::Encodings;
use regalloc;
use result::CodegenResult;
use settings;
use settings::SetResult;
use crate::binemit;
use crate::flowgraph;
use crate::ir;
use crate::isa::enc_tables::Encodings;
use crate::regalloc;
use crate::result::CodegenResult;
use crate::settings;
use crate::settings::SetResult;
use crate::timing;
use failure_derive::Fail;
use std::boxed::Box;
use std::fmt;
use target_lexicon::{Architecture, PointerWidth, Triple};
use timing;
#[cfg(build_riscv)]
mod riscv;
@@ -334,8 +337,8 @@ pub trait TargetIsa: fmt::Display + Sync {
fn prologue_epilogue(&self, func: &mut ir::Function) -> CodegenResult<()> {
let _tt = timing::prologue_epilogue();
// This default implementation is unlikely to be good enough.
use ir::stackslot::{StackOffset, StackSize};
use stack_layout::layout_stack;
use crate::ir::stackslot::{StackOffset, StackSize};
use crate::stack_layout::layout_stack;
let word_size = StackSize::from(self.pointer_bytes());

2
lib/codegen/src/isa/registers.rs
View File

@@ -1,6 +1,6 @@
//! Data structures describing the registers in an ISA.
use entity::EntityRef;
use crate::entity::EntityRef;
use std::fmt;
/// Register units are the smallest units of register allocation.

8
lib/codegen/src/isa/riscv/abi.rs
View File

@@ -7,10 +7,10 @@
use super::registers::{FPR, GPR};
use super::settings;
use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
use ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, Type};
use isa::RegClass;
use regalloc::RegisterSet;
use crate::abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
use crate::ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, Type};
use crate::isa::RegClass;
use crate::regalloc::RegisterSet;
use std::i32;
use target_lexicon::Triple;

10
lib/codegen/src/isa/riscv/binemit.rs
View File

@@ -1,10 +1,10 @@
//! Emitting binary RISC-V machine code.
use binemit::{bad_encoding, CodeSink, Reloc};
use ir::{Function, Inst, InstructionData};
use isa::{RegUnit, StackBaseMask, StackRef};
use predicates::is_signed_int;
use regalloc::RegDiversions;
use crate::binemit::{bad_encoding, CodeSink, Reloc};
use crate::ir::{Function, Inst, InstructionData};
use crate::isa::{RegUnit, StackBaseMask, StackRef};
use crate::predicates::is_signed_int;
use crate::regalloc::RegDiversions;
use std::u32;
include!(concat!(env!("OUT_DIR"), "/binemit-riscv.rs"));

10
lib/codegen/src/isa/riscv/enc_tables.rs
View File

@@ -1,11 +1,11 @@
//! Encoding tables for RISC-V.
use super::registers::*;
use ir;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::{base_size, RecipeSizing};
use crate::ir;
use crate::isa;
use crate::isa::constraints::*;
use crate::isa::enc_tables::*;
use crate::isa::encoding::{base_size, RecipeSizing};
// Include the generated encoding tables:
// - `LEVEL1_RV32`

24
lib/codegen/src/isa/riscv/mod.rs
View File

@@ -8,13 +8,13 @@ pub mod settings;
use super::super::settings as shared_settings;
#[cfg(feature = "testing_hooks")]
use binemit::CodeSink;
use binemit::{emit_function, MemoryCodeSink};
use ir;
use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use isa::Builder as IsaBuilder;
use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use regalloc;
use crate::binemit::CodeSink;
use crate::binemit::{emit_function, MemoryCodeSink};
use crate::ir;
use crate::isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use crate::isa::Builder as IsaBuilder;
use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use crate::regalloc;
use std::boxed::Box;
use std::fmt;
use target_lexicon::{PointerWidth, Triple};
@@ -125,13 +125,13 @@ impl TargetIsa for Isa {
#[cfg(test)]
mod tests {
use ir::{immediates, types};
use ir::{Function, InstructionData, Opcode};
use isa;
use settings::{self, Configurable};
use crate::ir::{immediates, types};
use crate::ir::{Function, InstructionData, Opcode};
use crate::isa;
use crate::settings::{self, Configurable};
use std::str::FromStr;
use std::string::{String, ToString};
use target_lexicon;
use target_lexicon::triple;
fn encstr(isa: &isa::TargetIsa, enc: Result<isa::Encoding, isa::Legalize>) -> String {
match enc {

4
lib/codegen/src/isa/riscv/registers.rs
View File

@@ -1,13 +1,13 @@
//! RISC-V register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
use crate::isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));
#[cfg(test)]
mod tests {
use super::{FPR, GPR, INFO};
use isa::RegUnit;
use crate::isa::RegUnit;
use std::string::{String, ToString};
#[test]

4
lib/codegen/src/isa/riscv/settings.rs
View File

@@ -1,6 +1,6 @@
//! RISC-V Settings.
use settings::{self, detail, Builder};
use crate::settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
@@ -11,7 +11,7 @@ include!(concat!(env!("OUT_DIR"), "/settings-riscv.rs"));
#[cfg(test)]
mod tests {
use super::{builder, Flags};
use settings::{self, Configurable};
use crate::settings::{self, Configurable};
use std::string::ToString;
#[test]

4
lib/codegen/src/isa/stack.rs
View File

@@ -4,8 +4,8 @@
//! defined in this module expresses the low-level details of accessing a stack slot from an
//! encoded instruction.
use ir::stackslot::{StackOffset, StackSlotKind, StackSlots};
use ir::StackSlot;
use crate::ir::stackslot::{StackOffset, StackSlotKind, StackSlots};
use crate::ir::StackSlot;
/// A method for referencing a stack slot in the current stack frame.
///

22
lib/codegen/src/isa/x86/abi.rs
View File

@@ -1,19 +1,19 @@
//! x86 ABI implementation.
use super::registers::{FPR, GPR, RU};
use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
use cursor::{Cursor, CursorPosition, EncCursor};
use ir;
use ir::immediates::Imm64;
use ir::stackslot::{StackOffset, StackSize};
use ir::{
use crate::abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
use crate::cursor::{Cursor, CursorPosition, EncCursor};
use crate::ir;
use crate::ir::immediates::Imm64;
use crate::ir::stackslot::{StackOffset, StackSize};
use crate::ir::{
get_probestack_funcref, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, InstBuilder,
ValueLoc,
};
use isa::{CallConv, RegClass, RegUnit, TargetIsa};
use regalloc::RegisterSet;
use result::CodegenResult;
use stack_layout::layout_stack;
use crate::isa::{CallConv, RegClass, RegUnit, TargetIsa};
use crate::regalloc::RegisterSet;
use crate::result::CodegenResult;
use crate::stack_layout::layout_stack;
use std::i32;
use target_lexicon::{PointerWidth, Triple};
@@ -511,7 +511,7 @@ fn insert_common_prologue(
/// Insert a check that generates a trap if the stack pointer goes
/// below a value in `stack_limit_arg`.
fn insert_stack_check(pos: &mut EncCursor, stack_size: i64, stack_limit_arg: ir::Value) {
use ir::condcodes::IntCC;
use crate::ir::condcodes::IntCC;
// Copy `stack_limit_arg` into a %rax and use it for calculating
// a SP threshold.

14
lib/codegen/src/isa/x86/binemit.rs
View File

@@ -2,11 +2,11 @@
use super::enc_tables::{needs_offset, needs_sib_byte};
use super::registers::RU;
use binemit::{bad_encoding, CodeSink, Reloc};
use ir::condcodes::{CondCode, FloatCC, IntCC};
use ir::{Ebb, Function, Inst, InstructionData, JumpTable, Opcode, TrapCode};
use isa::{RegUnit, StackBase, StackBaseMask, StackRef};
use regalloc::RegDiversions;
use crate::binemit::{bad_encoding, CodeSink, Reloc};
use crate::ir::condcodes::{CondCode, FloatCC, IntCC};
use crate::ir::{Ebb, Function, Inst, InstructionData, JumpTable, Opcode, TrapCode};
use crate::isa::{RegUnit, StackBase, StackBaseMask, StackRef};
use crate::regalloc::RegDiversions;
include!(concat!(env!("OUT_DIR"), "/binemit-x86.rs"));
@@ -270,7 +270,7 @@ fn sib<CS: CodeSink + ?Sized>(scale: u8, index: RegUnit, base: RegUnit, sink: &m
/// 0x0f 0x90: SetCC.
///
fn icc2opc(cond: IntCC) -> u16 {
use ir::condcodes::IntCC::*;
use crate::ir::condcodes::IntCC::*;
match cond {
// 0x0 = Overflow.
// 0x1 = !Overflow.
@@ -303,7 +303,7 @@ fn icc2opc(cond: IntCC) -> u16 {
///
/// Not all floating point condition codes are supported.
fn fcc2opc(cond: FloatCC) -> u16 {
use ir::condcodes::FloatCC::*;
use crate::ir::condcodes::FloatCC::*;
match cond {
Ordered => 0xb, // EQ|LT|GT => *np (P=0)
Unordered => 0xa, // UN => *p (P=1)

44
lib/codegen/src/isa/x86/enc_tables.rs
View File

@@ -1,18 +1,18 @@
//! Encoding tables for x86 ISAs.
use super::registers::*;
use bitset::BitSet;
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::condcodes::IntCC;
use ir::{self, Function, Inst, InstBuilder};
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::base_size;
use isa::encoding::RecipeSizing;
use isa::RegUnit;
use regalloc::RegDiversions;
use crate::bitset::BitSet;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::condcodes::IntCC;
use crate::ir::{self, Function, Inst, InstBuilder};
use crate::isa;
use crate::isa::constraints::*;
use crate::isa::enc_tables::*;
use crate::isa::encoding::base_size;
use crate::isa::encoding::RecipeSizing;
use crate::isa::RegUnit;
use crate::regalloc::RegDiversions;
include!(concat!(env!("OUT_DIR"), "/encoding-x86.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-x86.rs"));
@@ -228,7 +228,7 @@ fn expand_minmax(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::FloatCC;
use crate::ir::condcodes::FloatCC;
let (x, y, x86_opc, bitwise_opc) = match func.dfg[inst] {
ir::InstructionData::Binary {
@@ -322,7 +322,7 @@ fn expand_fcvt_from_uint(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::IntCC;
use crate::ir::condcodes::IntCC;
let x;
match func.dfg[inst] {
@@ -395,8 +395,8 @@ fn expand_fcvt_to_sint(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::{FloatCC, IntCC};
use ir::immediates::{Ieee32, Ieee64};
use crate::ir::condcodes::{FloatCC, IntCC};
use crate::ir::immediates::{Ieee32, Ieee64};
let x = match func.dfg[inst] {
ir::InstructionData::Unary {
@@ -491,8 +491,8 @@ fn expand_fcvt_to_sint_sat(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::{FloatCC, IntCC};
use ir::immediates::{Ieee32, Ieee64};
use crate::ir::condcodes::{FloatCC, IntCC};
use crate::ir::immediates::{Ieee32, Ieee64};
let x = match func.dfg[inst] {
ir::InstructionData::Unary {
@@ -611,8 +611,8 @@ fn expand_fcvt_to_uint(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::{FloatCC, IntCC};
use ir::immediates::{Ieee32, Ieee64};
use crate::ir::condcodes::{FloatCC, IntCC};
use crate::ir::immediates::{Ieee32, Ieee64};
let x = match func.dfg[inst] {
ir::InstructionData::Unary {
@@ -693,8 +693,8 @@ fn expand_fcvt_to_uint_sat(
cfg: &mut ControlFlowGraph,
_isa: &isa::TargetIsa,
) {
use ir::condcodes::{FloatCC, IntCC};
use ir::immediates::{Ieee32, Ieee64};
use crate::ir::condcodes::{FloatCC, IntCC};
use crate::ir::immediates::{Ieee32, Ieee64};
let x = match func.dfg[inst] {
ir::InstructionData::Unary {

18
lib/codegen/src/isa/x86/mod.rs
View File

@@ -8,18 +8,18 @@ pub mod settings;
use super::super::settings as shared_settings;
#[cfg(feature = "testing_hooks")]
use binemit::CodeSink;
use binemit::{emit_function, MemoryCodeSink};
use ir;
use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use isa::Builder as IsaBuilder;
use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use regalloc;
use result::CodegenResult;
use crate::binemit::CodeSink;
use crate::binemit::{emit_function, MemoryCodeSink};
use crate::ir;
use crate::isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
use crate::isa::Builder as IsaBuilder;
use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
use crate::regalloc;
use crate::result::CodegenResult;
use crate::timing;
use std::boxed::Box;
use std::fmt;
use target_lexicon::{PointerWidth, Triple};
use timing;
#[allow(dead_code)]
struct Isa {

4
lib/codegen/src/isa/x86/registers.rs
View File

@@ -1,13 +1,13 @@
//! x86 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
use crate::isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-x86.rs"));
#[cfg(test)]
mod tests {
use super::*;
use isa::RegUnit;
use crate::isa::RegUnit;
use std::string::{String, ToString};
#[test]

4
lib/codegen/src/isa/x86/settings.rs
View File

@@ -1,6 +1,6 @@
//! x86 Settings.
use settings::{self, detail, Builder};
use crate::settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
@@ -11,7 +11,7 @@ include!(concat!(env!("OUT_DIR"), "/settings-x86.rs"));
#[cfg(test)]
mod tests {
use super::{builder, Flags};
use settings::{self, Configurable};
use crate::settings::{self, Configurable};
#[test]
fn presets() {

15
lib/codegen/src/legalizer/boundary.rs
View File

@@ -17,16 +17,17 @@
//! Between the two phases, preamble signatures and call/return arguments don't match. This
//! intermediate state doesn't type check.
use abi::{legalize_abi_value, ValueConversion};
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::instructions::CallInfo;
use ir::{
use crate::abi::{legalize_abi_value, ValueConversion};
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::instructions::CallInfo;
use crate::ir::{
AbiParam, ArgumentLoc, ArgumentPurpose, DataFlowGraph, Ebb, Function, Inst, InstBuilder,
SigRef, Signature, Type, Value, ValueLoc,
};
use isa::TargetIsa;
use legalizer::split::{isplit, vsplit};
use crate::isa::TargetIsa;
use crate::legalizer::split::{isplit, vsplit};
use log::debug;
use std::vec::Vec;
/// Legalize all the function signatures in `func`.

8
lib/codegen/src/legalizer/call.rs
View File

@@ -3,10 +3,10 @@
//! This module exports the `expand_call` function which transforms a `call`
//! instruction into `func_addr` and `call_indirect` instructions.
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::{self, InstBuilder};
use isa::TargetIsa;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::{self, InstBuilder};
use crate::isa::TargetIsa;
/// Expand a `call` instruction. This lowers it to a `call_indirect`, which
/// is only done if the ABI doesn't support direct calls.

8
lib/codegen/src/legalizer/globalvalue.rs
View File

@@ -3,10 +3,10 @@
//! This module exports the `expand_global_value` function which transforms a `global_value`
//! instruction into code that depends on the kind of global value referenced.
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::{self, InstBuilder};
use isa::TargetIsa;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::{self, InstBuilder};
use crate::isa::TargetIsa;
/// Expand a `global_value` instruction according to the definition of the global value.
pub fn expand_global_value(

10
lib/codegen/src/legalizer/heap.rs
View File

@@ -3,11 +3,11 @@
//! This module exports the `expand_heap_addr` function which transforms a `heap_addr`
//! instruction into code that depends on the kind of heap referenced.
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::condcodes::IntCC;
use ir::{self, InstBuilder};
use isa::TargetIsa;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::condcodes::IntCC;
use crate::ir::{self, InstBuilder};
use crate::isa::TargetIsa;
/// Expand a `heap_addr` instruction according to the definition of the heap.
pub fn expand_heap_addr(

8
lib/codegen/src/legalizer/libcall.rs
View File

@@ -1,9 +1,9 @@
//! Expanding instructions as runtime library calls.
use ir;
use ir::{get_libcall_funcref, InstBuilder};
use isa::TargetIsa;
use legalizer::boundary::legalize_libcall_signature;
use crate::ir;
use crate::ir::{get_libcall_funcref, InstBuilder};
use crate::isa::TargetIsa;
use crate::legalizer::boundary::legalize_libcall_signature;
use std::vec::Vec;
/// Try to expand `inst` as a library call, returning true is successful.

18
lib/codegen/src/legalizer/mod.rs
View File

@@ -13,13 +13,13 @@
//! The legalizer does not deal with register allocation constraints. These constraints are derived
//! from the encoding recipes, and solved later by the register allocator.
use bitset::BitSet;
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::types::I32;
use ir::{self, InstBuilder, MemFlags};
use isa::TargetIsa;
use timing;
use crate::bitset::BitSet;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::types::I32;
use crate::ir::{self, InstBuilder, MemFlags};
use crate::isa::TargetIsa;
use crate::timing;
mod boundary;
mod call;
@@ -195,7 +195,7 @@ fn expand_br_table_jt(
cfg: &mut ControlFlowGraph,
isa: &TargetIsa,
) {
use ir::condcodes::IntCC;
use crate::ir::condcodes::IntCC;
let (arg, default_ebb, table) = match func.dfg[inst] {
ir::InstructionData::BranchTable {
@@ -241,7 +241,7 @@ fn expand_br_table_conds(
cfg: &mut ControlFlowGraph,
_isa: &TargetIsa,
) {
use ir::condcodes::IntCC;
use crate::ir::condcodes::IntCC;
let (arg, default_ebb, table) = match func.dfg[inst] {
ir::InstructionData::BranchTable {

6
lib/codegen/src/legalizer/split.rs
View File

@@ -64,9 +64,9 @@
//! It is possible to have circular dependencies of EBB arguments that are never used by any real
//! instructions. These loops will remain in the program.
use cursor::{Cursor, CursorPosition, FuncCursor};
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::{self, Ebb, Inst, InstBuilder, InstructionData, Opcode, Type, Value, ValueDef};
use crate::cursor::{Cursor, CursorPosition, FuncCursor};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::{self, Ebb, Inst, InstBuilder, InstructionData, Opcode, Type, Value, ValueDef};
use std::iter;
use std::vec::Vec;

12
lib/codegen/src/legalizer/table.rs
View File

@@ -3,12 +3,12 @@
//! This module exports the `expand_table_addr` function which transforms a `table_addr`
//! instruction into code that depends on the kind of table referenced.
use cursor::{Cursor, FuncCursor};
use flowgraph::ControlFlowGraph;
use ir::condcodes::IntCC;
use ir::immediates::Offset32;
use ir::{self, InstBuilder};
use isa::TargetIsa;
use crate::cursor::{Cursor, FuncCursor};
use crate::flowgraph::ControlFlowGraph;
use crate::ir::condcodes::IntCC;
use crate::ir::immediates::Offset32;
use crate::ir::{self, InstBuilder};
use crate::isa::TargetIsa;
/// Expand a `table_addr` instruction according to the definition of the table.
pub fn expand_table_addr(

25
lib/codegen/src/lib.rs
View File

@@ -49,26 +49,17 @@
#[cfg(not(feature = "std"))]
#[macro_use]
extern crate alloc;
extern crate failure;
#[macro_use]
extern crate failure_derive;
#[cfg_attr(test, macro_use)]
extern crate target_lexicon;
#[macro_use]
extern crate log;
pub use context::Context;
pub use legalizer::legalize_function;
pub use verifier::verify_function;
pub use write::write_function;
pub use crate::context::Context;
pub use crate::legalizer::legalize_function;
pub use crate::verifier::verify_function;
pub use crate::write::write_function;
/// Version number of the cranelift-codegen crate.
pub const VERSION: &str = env!("CARGO_PKG_VERSION");
#[macro_use]
pub extern crate cranelift_entity as entity;
pub extern crate cranelift_bforest as bforest;
pub use cranelift_bforest as bforest;
pub use cranelift_entity as entity;
pub mod binemit;
pub mod cfg_printer;
@@ -85,7 +76,7 @@ pub mod timing;
pub mod verifier;
pub mod write;
pub use entity::packed_option;
pub use crate::entity::packed_option;
mod abi;
mod bitset;
@@ -111,7 +102,7 @@ mod stack_layout;
mod topo_order;
mod unreachable_code;
pub use result::{CodegenError, CodegenResult};
pub use crate::result::{CodegenError, CodegenResult};
/// This replaces `std` in builds with `core`.
#[cfg(not(feature = "std"))]

18
lib/codegen/src/licm.rs
View File

@@ -1,15 +1,15 @@
//! A Loop Invariant Code Motion optimization pass
use cursor::{Cursor, EncCursor, FuncCursor};
use dominator_tree::DominatorTree;
use entity::{EntityList, ListPool};
use flowgraph::{BasicBlock, ControlFlowGraph};
use fx::FxHashSet;
use ir::{DataFlowGraph, Ebb, Function, Inst, InstBuilder, Layout, Opcode, Type, Value};
use isa::TargetIsa;
use loop_analysis::{Loop, LoopAnalysis};
use crate::cursor::{Cursor, EncCursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::entity::{EntityList, ListPool};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::fx::FxHashSet;
use crate::ir::{DataFlowGraph, Ebb, Function, Inst, InstBuilder, Layout, Opcode, Type, Value};
use crate::isa::TargetIsa;
use crate::loop_analysis::{Loop, LoopAnalysis};
use crate::timing;
use std::vec::Vec;
use timing;
/// Performs the LICM pass by detecting loops within the CFG and moving
/// loop-invariant instructions out of them.

25
lib/codegen/src/loop_analysis.rs
View File

@@ -1,14 +1,15 @@
//! A loop analysis represented as mappings of loops to their header Ebb
//! and parent in the loop tree.
use dominator_tree::DominatorTree;
use entity::SecondaryMap;
use entity::{Keys, PrimaryMap};
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::{Ebb, Function, Layout};
use packed_option::PackedOption;
use crate::dominator_tree::DominatorTree;
use crate::entity::entity_impl;
use crate::entity::SecondaryMap;
use crate::entity::{Keys, PrimaryMap};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::{Ebb, Function, Layout};
use crate::packed_option::PackedOption;
use crate::timing;
use std::vec::Vec;
use timing;
/// A opaque reference to a code loop.
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
@@ -231,11 +232,11 @@ impl LoopAnalysis {
#[cfg(test)]
mod tests {
use cursor::{Cursor, FuncCursor};
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::{types, Function, InstBuilder};
use loop_analysis::{Loop, LoopAnalysis};
use crate::cursor::{Cursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir::{types, Function, InstBuilder};
use crate::loop_analysis::{Loop, LoopAnalysis};
use std::vec::Vec;
#[test]

14
lib/codegen/src/nan_canonicalization.rs
View File

@@ -2,13 +2,13 @@
//! instructions that may return a NaN result with a sequence of operations
//! that will replace nondeterministic NaN's with a single canonical NaN value.
use cursor::{Cursor, FuncCursor};
use ir::condcodes::FloatCC;
use ir::immediates::{Ieee32, Ieee64};
use ir::types;
use ir::types::Type;
use ir::{Function, Inst, InstBuilder, InstructionData, Opcode, Value};
use timing;
use crate::cursor::{Cursor, FuncCursor};
use crate::ir::condcodes::FloatCC;
use crate::ir::immediates::{Ieee32, Ieee64};
use crate::ir::types;
use crate::ir::types::Type;
use crate::ir::{Function, Inst, InstBuilder, InstructionData, Opcode, Value};
use crate::timing;
// Canonical 32-bit and 64-bit NaN values.
static CANON_32BIT_NAN: u32 = 0b01111111110000000000000000000000;

16
lib/codegen/src/postopt.rs
View File

@@ -2,14 +2,14 @@
#![allow(non_snake_case)]
use cursor::{Cursor, EncCursor};
use ir::condcodes::{CondCode, FloatCC, IntCC};
use ir::dfg::ValueDef;
use ir::immediates::{Imm64, Offset32};
use ir::instructions::{Opcode, ValueList};
use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, MemFlags, Type, Value};
use isa::TargetIsa;
use timing;
use crate::cursor::{Cursor, EncCursor};
use crate::ir::condcodes::{CondCode, FloatCC, IntCC};
use crate::ir::dfg::ValueDef;
use crate::ir::immediates::{Imm64, Offset32};
use crate::ir::instructions::{Opcode, ValueList};
use crate::ir::{Ebb, Function, Inst, InstBuilder, InstructionData, MemFlags, Type, Value};
use crate::isa::TargetIsa;
use crate::timing;
/// Information collected about a compare+branch sequence.
struct CmpBrInfo {

4
lib/codegen/src/predicates.rs
View File

@@ -9,7 +9,7 @@
//! Some of these predicates may be unused in certain ISA configurations, so we suppress the
//! dead code warning.
use ir;
use crate::ir;
/// Check that a 64-bit floating point value is zero.
#[allow(dead_code)]
@@ -93,7 +93,7 @@ mod tests {
#[test]
fn cvt_imm64() {
use ir::immediates::Imm64;
use crate::ir::immediates::Imm64;
let x1 = Imm64::new(-8);
let x2 = Imm64::new(8);

16
lib/codegen/src/print_errors.rs
View File

@@ -1,18 +1,18 @@
//! Utility routines for pretty-printing error messages.
use entity::SecondaryMap;
use ir;
use ir::entities::{AnyEntity, Ebb, Inst, Value};
use ir::function::Function;
use isa::TargetIsa;
use result::CodegenError;
use crate::entity::SecondaryMap;
use crate::ir;
use crate::ir::entities::{AnyEntity, Ebb, Inst, Value};
use crate::ir::function::Function;
use crate::isa::TargetIsa;
use crate::result::CodegenError;
use crate::verifier::{VerifierError, VerifierErrors};
use crate::write::{decorate_function, FuncWriter, PlainWriter};
use std::boxed::Box;
use std::fmt;
use std::fmt::Write;
use std::string::{String, ToString};
use std::vec::Vec;
use verifier::{VerifierError, VerifierErrors};
use write::{decorate_function, FuncWriter, PlainWriter};
/// Pretty-print a verifier error.
pub fn pretty_verifier_error<'a>(

4
lib/codegen/src/regalloc/affinity.rs
View File

@@ -8,8 +8,8 @@
//! subclass. This is just a hint, and the register allocator is allowed to pick a register from a
//! larger register class instead.
use ir::{AbiParam, ArgumentLoc};
use isa::{ConstraintKind, OperandConstraint, RegClassIndex, RegInfo, TargetIsa};
use crate::ir::{AbiParam, ArgumentLoc};
use crate::isa::{ConstraintKind, OperandConstraint, RegClassIndex, RegInfo, TargetIsa};
use std::fmt;
/// Preferred register allocation for an SSA value.

25
lib/codegen/src/regalloc/coalescing.rs
View File

@@ -5,23 +5,24 @@
//! possible and inserting copies where necessary such that all argument values passed to an EBB
//! parameter will belong to the same virtual register as the EBB parameter value itself.
use cursor::{Cursor, EncCursor};
use dbg::DisplayList;
use dominator_tree::{DominatorTree, DominatorTreePreorder};
use flowgraph::{BasicBlock, ControlFlowGraph};
use fx::FxHashMap;
use ir::{self, InstBuilder, ProgramOrder};
use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Value};
use isa::{EncInfo, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::liveness::Liveness;
use regalloc::virtregs::{VirtReg, VirtRegs};
use crate::cursor::{Cursor, EncCursor};
use crate::dbg::DisplayList;
use crate::dominator_tree::{DominatorTree, DominatorTreePreorder};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::fx::FxHashMap;
use crate::ir::{self, InstBuilder, ProgramOrder};
use crate::ir::{Ebb, ExpandedProgramPoint, Function, Inst, Value};
use crate::isa::{EncInfo, TargetIsa};
use crate::regalloc::affinity::Affinity;
use crate::regalloc::liveness::Liveness;
use crate::regalloc::virtregs::{VirtReg, VirtRegs};
use crate::timing;
use log::debug;
use std::cmp;
use std::fmt;
use std::iter;
use std::slice;
use std::vec::Vec;
use timing;
// # Implementation
//

35
lib/codegen/src/regalloc/coloring.rs
View File

@@ -42,22 +42,23 @@
//!
//! The exception is the entry block whose arguments are colored from the ABI requirements.
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use ir::{AbiParam, ArgumentLoc, InstBuilder, ValueDef};
use ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
use isa::{regs_overlap, RegClass, RegInfo, RegUnit};
use isa::{ConstraintKind, EncInfo, OperandConstraint, RecipeConstraints, TargetIsa};
use packed_option::PackedOption;
use regalloc::affinity::Affinity;
use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use regalloc::liveness::Liveness;
use regalloc::liverange::{LiveRange, LiveRangeContext};
use regalloc::register_set::RegisterSet;
use regalloc::solver::{Solver, SolverError};
use regalloc::RegDiversions;
use crate::cursor::{Cursor, EncCursor};
use crate::dominator_tree::DominatorTree;
use crate::ir::{AbiParam, ArgumentLoc, InstBuilder, ValueDef};
use crate::ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
use crate::isa::{regs_overlap, RegClass, RegInfo, RegUnit};
use crate::isa::{ConstraintKind, EncInfo, OperandConstraint, RecipeConstraints, TargetIsa};
use crate::packed_option::PackedOption;
use crate::regalloc::affinity::Affinity;
use crate::regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use crate::regalloc::liveness::Liveness;
use crate::regalloc::liverange::{LiveRange, LiveRangeContext};
use crate::regalloc::register_set::RegisterSet;
use crate::regalloc::solver::{Solver, SolverError};
use crate::regalloc::RegDiversions;
use crate::timing;
use log::debug;
use std::mem;
use timing;
/// Data structures for the coloring pass.
///
@@ -901,7 +902,7 @@ impl<'a> Context<'a> {
/// branch destinations. Branch arguments and EBB parameters are not considered live on the
/// edge.
fn is_live_on_outgoing_edge(&self, value: Value) -> bool {
use ir::instructions::BranchInfo::*;
use crate::ir::instructions::BranchInfo::*;
let inst = self.cur.current_inst().expect("Not on an instruction");
let ctx = self.liveness.context(&self.cur.func.layout);
@@ -930,7 +931,7 @@ impl<'a> Context<'a> {
///
/// The solver needs to be reminded of the available registers before any moves are inserted.
fn shuffle_inputs(&mut self, regs: &mut RegisterSet) {
use regalloc::solver::Move::*;
use crate::regalloc::solver::Move::*;
let spills = self.solver.schedule_moves(regs);

32
lib/codegen/src/regalloc/context.rs
View File

@@ -4,21 +4,23 @@
//! the register allocator algorithm. This doesn't preserve any data between functions, but it
//! avoids allocating data structures independently for each function begin compiled.
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::Function;
use isa::TargetIsa;
use regalloc::coalescing::Coalescing;
use regalloc::coloring::Coloring;
use regalloc::live_value_tracker::LiveValueTracker;
use regalloc::liveness::Liveness;
use regalloc::reload::Reload;
use regalloc::spilling::Spilling;
use regalloc::virtregs::VirtRegs;
use result::CodegenResult;
use timing;
use topo_order::TopoOrder;
use verifier::{verify_context, verify_cssa, verify_liveness, verify_locations, VerifierErrors};
use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir::Function;
use crate::isa::TargetIsa;
use crate::regalloc::coalescing::Coalescing;
use crate::regalloc::coloring::Coloring;
use crate::regalloc::live_value_tracker::LiveValueTracker;
use crate::regalloc::liveness::Liveness;
use crate::regalloc::reload::Reload;
use crate::regalloc::spilling::Spilling;
use crate::regalloc::virtregs::VirtRegs;
use crate::result::CodegenResult;
use crate::timing;
use crate::topo_order::TopoOrder;
use crate::verifier::{
verify_context, verify_cssa, verify_liveness, verify_locations, VerifierErrors,
};
/// Persistent memory allocations for register allocation.
pub struct Context {

12
lib/codegen/src/regalloc/diversion.rs
View File

@@ -7,10 +7,10 @@
//! These register diversions are local to an EBB. No values can be diverted when entering a new
//! EBB.
use fx::FxHashMap;
use ir::{InstructionData, Opcode};
use ir::{StackSlot, Value, ValueLoc, ValueLocations};
use isa::{RegInfo, RegUnit};
use crate::fx::FxHashMap;
use crate::ir::{InstructionData, Opcode};
use crate::ir::{StackSlot, Value, ValueLoc, ValueLocations};
use crate::isa::{RegInfo, RegUnit};
use std::collections::hash_map::{Entry, Iter};
use std::fmt;
@@ -191,8 +191,8 @@ impl<'a> fmt::Display for DisplayDiversions<'a> {
#[cfg(test)]
mod tests {
use super::*;
use entity::EntityRef;
use ir::Value;
use crate::entity::EntityRef;
use crate::ir::Value;
#[test]
fn inserts() {

16
lib/codegen/src/regalloc/live_value_tracker.rs
View File

@@ -4,14 +4,14 @@
//! The sets of live values are computed on the fly as the tracker is moved from instruction to
//! instruction, starting at the EBB header.
use dominator_tree::DominatorTree;
use entity::{EntityList, ListPool};
use fx::FxHashMap;
use ir::{DataFlowGraph, Ebb, ExpandedProgramPoint, Inst, Layout, Value};
use partition_slice::partition_slice;
use regalloc::affinity::Affinity;
use regalloc::liveness::Liveness;
use regalloc::liverange::LiveRange;
use crate::dominator_tree::DominatorTree;
use crate::entity::{EntityList, ListPool};
use crate::fx::FxHashMap;
use crate::ir::{DataFlowGraph, Ebb, ExpandedProgramPoint, Inst, Layout, Value};
use crate::partition_slice::partition_slice;
use crate::regalloc::affinity::Affinity;
use crate::regalloc::liveness::Liveness;
use crate::regalloc::liverange::LiveRange;
use std::vec::Vec;
type ValueList = EntityList<Value>;

16
lib/codegen/src/regalloc/liveness.rs
View File

@@ -175,17 +175,17 @@
//!
//! There is some room for improvement.
use entity::SparseMap;
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::dfg::ValueDef;
use ir::{Ebb, Function, Inst, Layout, ProgramPoint, Value};
use isa::{EncInfo, OperandConstraint, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::liverange::{LiveRange, LiveRangeContext, LiveRangeForest};
use crate::entity::SparseMap;
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::dfg::ValueDef;
use crate::ir::{Ebb, Function, Inst, Layout, ProgramPoint, Value};
use crate::isa::{EncInfo, OperandConstraint, TargetIsa};
use crate::regalloc::affinity::Affinity;
use crate::regalloc::liverange::{LiveRange, LiveRangeContext, LiveRangeForest};
use crate::timing;
use std::mem;
use std::ops::Index;
use std::vec::Vec;
use timing;
/// A set of live ranges, indexed by value number.
type LiveRangeSet = SparseMap<Value, LiveRange>;

16
lib/codegen/src/regalloc/liverange.rs
View File

@@ -107,10 +107,10 @@
//! of coalescing, so we would need to roll our own.
//!
use bforest;
use entity::SparseMapValue;
use ir::{Ebb, ExpandedProgramPoint, Inst, Layout, ProgramOrder, ProgramPoint, Value};
use regalloc::affinity::Affinity;
use crate::bforest;
use crate::entity::SparseMapValue;
use crate::ir::{Ebb, ExpandedProgramPoint, Inst, Layout, ProgramOrder, ProgramPoint, Value};
use crate::regalloc::affinity::Affinity;
use std::cmp::Ordering;
use std::marker::PhantomData;
@@ -457,10 +457,10 @@ impl<PO: ProgramOrder> SparseMapValue<Value> for GenLiveRange<PO> {
#[cfg(test)]
mod tests {
use super::{GenLiveRange, LiveRangeContext};
use bforest;
use entity::EntityRef;
use ir::{Ebb, Inst, Value};
use ir::{ExpandedProgramPoint, ProgramOrder};
use crate::bforest;
use crate::entity::EntityRef;
use crate::ir::{Ebb, Inst, Value};
use crate::ir::{ExpandedProgramPoint, ProgramOrder};
use std::cmp::Ordering;
use std::vec::Vec;

14
lib/codegen/src/regalloc/pressure.rs
View File

@@ -36,8 +36,8 @@
// Remove once we're using the pressure tracker.
#![allow(dead_code)]
use isa::registers::{RegClass, RegClassMask, RegInfo, MAX_TRACKED_TOPRCS};
use regalloc::RegisterSet;
use crate::isa::registers::{RegClass, RegClassMask, RegInfo, MAX_TRACKED_TOPRCS};
use crate::regalloc::RegisterSet;
use std::cmp::min;
use std::fmt;
use std::iter::ExactSizeIterator;
@@ -273,17 +273,17 @@ impl fmt::Display for Pressure {
#[cfg(build_arm32)]
mod tests {
use super::Pressure;
use isa::{RegClass, TargetIsa};
use regalloc::RegisterSet;
use crate::isa::{RegClass, TargetIsa};
use crate::regalloc::RegisterSet;
use std::borrow::Borrow;
use std::boxed::Box;
use std::str::FromStr;
use target_lexicon;
use target_lexicon::triple;
// Make an arm32 `TargetIsa`, if possible.
fn arm32() -> Option<Box<TargetIsa>> {
use isa;
use settings;
use crate::isa;
use crate::settings;
let shared_builder = settings::builder();
let shared_flags = settings::Flags::new(shared_builder);

4
lib/codegen/src/regalloc/register_set.rs
View File

@@ -5,7 +5,7 @@
//! "register unit" abstraction. Every register contains one or more register units. Registers that
//! share a register unit can't be in use at the same time.
use isa::registers::{RegClass, RegInfo, RegUnit, RegUnitMask};
use crate::isa::registers::{RegClass, RegInfo, RegUnit, RegUnitMask};
use std::char;
use std::fmt;
use std::iter::ExactSizeIterator;
@@ -228,7 +228,7 @@ impl fmt::Display for RegisterSet {
#[cfg(test)]
mod tests {
use super::*;
use isa::registers::{RegClass, RegClassData};
use crate::isa::registers::{RegClass, RegClassData};
use std::vec::Vec;
// Register classes for testing.

25
lib/codegen/src/regalloc/reload.rs
View File

@@ -9,19 +9,20 @@
//! possible to minimize the number of `fill` instructions needed. This must not cause the register
//! pressure limits to be exceeded.
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use entity::{SparseMap, SparseMapValue};
use ir::{AbiParam, ArgumentLoc, InstBuilder};
use ir::{Ebb, Function, Inst, InstructionData, Opcode, Value};
use isa::RegClass;
use isa::{ConstraintKind, EncInfo, Encoding, RecipeConstraints, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use regalloc::liveness::Liveness;
use crate::cursor::{Cursor, EncCursor};
use crate::dominator_tree::DominatorTree;
use crate::entity::{SparseMap, SparseMapValue};
use crate::ir::{AbiParam, ArgumentLoc, InstBuilder};
use crate::ir::{Ebb, Function, Inst, InstructionData, Opcode, Value};
use crate::isa::RegClass;
use crate::isa::{ConstraintKind, EncInfo, Encoding, RecipeConstraints, TargetIsa};
use crate::regalloc::affinity::Affinity;
use crate::regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use crate::regalloc::liveness::Liveness;
use crate::timing;
use crate::topo_order::TopoOrder;
use log::debug;
use std::vec::Vec;
use timing;
use topo_order::TopoOrder;
/// Reusable data structures for the reload pass.
pub struct Reload {

25
lib/codegen/src/regalloc/solver.rs
View File

@@ -99,11 +99,12 @@
//! over.
use super::RegisterSet;
use dbg::DisplayList;
use entity::{SparseMap, SparseMapValue};
use ir::Value;
use isa::{RegClass, RegUnit};
use regalloc::register_set::RegSetIter;
use crate::dbg::DisplayList;
use crate::entity::{SparseMap, SparseMapValue};
use crate::ir::Value;
use crate::isa::{RegClass, RegUnit};
use crate::regalloc::register_set::RegSetIter;
use log::debug;
use std::cmp;
use std::fmt;
use std::mem;
@@ -1129,18 +1130,18 @@ impl fmt::Display for Solver {
#[cfg(build_arm32)]
mod tests {
use super::{Move, Solver};
use entity::EntityRef;
use ir::Value;
use isa::{RegClass, RegInfo, RegUnit, TargetIsa};
use regalloc::RegisterSet;
use crate::entity::EntityRef;
use crate::ir::Value;
use crate::isa::{RegClass, RegInfo, RegUnit, TargetIsa};
use crate::regalloc::RegisterSet;
use std::boxed::Box;
use std::str::FromStr;
use target_lexicon;
use target_lexicon::triple;
// Make an arm32 `TargetIsa`, if possible.
fn arm32() -> Option<Box<TargetIsa>> {
use isa;
use settings;
use crate::isa;
use crate::settings;
let shared_builder = settings::builder();
let shared_flags = settings::Flags::new(shared_builder);

25
lib/codegen/src/regalloc/spilling.rs
View File

@@ -15,20 +15,21 @@
//! be compatible. Otherwise, the value must be copied into a new register for some of the
//! operands.
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use ir::{ArgumentLoc, Ebb, Function, Inst, InstBuilder, SigRef, Value, ValueLoc};
use isa::registers::{RegClass, RegClassIndex, RegClassMask, RegUnit};
use isa::{ConstraintKind, EncInfo, RecipeConstraints, RegInfo, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use regalloc::liveness::Liveness;
use regalloc::pressure::Pressure;
use regalloc::virtregs::VirtRegs;
use crate::cursor::{Cursor, EncCursor};
use crate::dominator_tree::DominatorTree;
use crate::ir::{ArgumentLoc, Ebb, Function, Inst, InstBuilder, SigRef, Value, ValueLoc};
use crate::isa::registers::{RegClass, RegClassIndex, RegClassMask, RegUnit};
use crate::isa::{ConstraintKind, EncInfo, RecipeConstraints, RegInfo, TargetIsa};
use crate::regalloc::affinity::Affinity;
use crate::regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use crate::regalloc::liveness::Liveness;
use crate::regalloc::pressure::Pressure;
use crate::regalloc::virtregs::VirtRegs;
use crate::timing;
use crate::topo_order::TopoOrder;
use log::debug;
use std::fmt;
use std::vec::Vec;
use timing;
use topo_order::TopoOrder;
/// Return a top-level register class which contains `unit`.
fn toprc_containing_regunit(unit: RegUnit, reginfo: &RegInfo) -> RegClass {

19
lib/codegen/src/regalloc/virtregs.rs
View File

@@ -11,13 +11,14 @@
//! If any values in a virtual register are spilled, they will use the same stack slot. This avoids
//! memory-to-memory copies when a spilled value is passed as an EBB argument.
use dbg::DisplayList;
use dominator_tree::DominatorTreePreorder;
use entity::{EntityList, ListPool};
use entity::{Keys, PrimaryMap, SecondaryMap};
use ir::{Function, Value};
use packed_option::PackedOption;
use ref_slice::ref_slice;
use crate::dbg::DisplayList;
use crate::dominator_tree::DominatorTreePreorder;
use crate::entity::entity_impl;
use crate::entity::{EntityList, ListPool};
use crate::entity::{Keys, PrimaryMap, SecondaryMap};
use crate::ir::{Function, Value};
use crate::packed_option::PackedOption;
use crate::ref_slice::ref_slice;
use std::cmp::Ordering;
use std::fmt;
use std::vec::Vec;
@@ -399,8 +400,8 @@ impl VirtRegs {
#[cfg(test)]
mod tests {
use super::*;
use entity::EntityRef;
use ir::Value;
use crate::entity::EntityRef;
use crate::ir::Value;
#[test]
fn empty_union_find() {

3
lib/codegen/src/result.rs
View File

@@ -1,6 +1,7 @@
//! Result and error types representing the outcome of compiling a function.
use verifier::VerifierErrors;
use crate::verifier::VerifierErrors;
use failure_derive::Fail;
/// A compilation error.
///

2
lib/codegen/src/scoped_hash_map.rs
View File

@@ -4,7 +4,7 @@
//! container that has a concept of scopes that can be entered and exited, such that
//! values inserted while inside a scope aren't visible outside the scope.
use fx::FxHashMap;
use crate::fx::FxHashMap;
use std::collections::hash_map;
use std::hash::Hash;
use std::mem;

7
lib/codegen/src/settings.rs
View File

@@ -20,8 +20,9 @@
//! assert_eq!(f.opt_level(), settings::OptLevel::Fastest);
//! ```
use constant_hash::{probe, simple_hash};
use isa::TargetIsa;
use crate::constant_hash::{probe, simple_hash};
use crate::isa::TargetIsa;
use failure_derive::Fail;
use std::boxed::Box;
use std::fmt;
use std::str;
@@ -202,7 +203,7 @@ impl<'a> PredicateView<'a> {
/// This module holds definitions that need to be public so the can be instantiated by generated
/// code in other modules.
pub mod detail {
use constant_hash;
use crate::constant_hash;
use std::fmt;
/// An instruction group template.

12
lib/codegen/src/simple_gvn.rs
View File

@@ -1,13 +1,13 @@
//! A simple GVN pass.
use cursor::{Cursor, FuncCursor};
use dominator_tree::DominatorTree;
use ir::{Function, Inst, InstructionData, Opcode, Type};
use scoped_hash_map::ScopedHashMap;
use crate::cursor::{Cursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::ir::{Function, Inst, InstructionData, Opcode, Type};
use crate::scoped_hash_map::ScopedHashMap;
use crate::timing;
use std::cell::{Ref, RefCell};
use std::hash::{Hash, Hasher};
use std::vec::Vec;
use timing;
/// Test whether the given opcode is unsafe to even consider for GVN.
fn trivially_unsafe_for_gvn(opcode: Opcode) -> bool {
@@ -121,7 +121,7 @@ pub fn do_simple_gvn(func: &mut Function, domtree: &mut DominatorTree) {
ty: ctrl_typevar,
pos: &pos,
};
use scoped_hash_map::Entry::*;
use crate::scoped_hash_map::Entry::*;
match visible_values.entry(key) {
Occupied(entry) => {
debug_assert!(domtree.dominates(*entry.get(), inst, &func.layout));

18
lib/codegen/src/simple_preopt.rs
View File

@@ -2,15 +2,15 @@
#![allow(non_snake_case)]
use cursor::{Cursor, FuncCursor};
use divconst_magic_numbers::{magicS32, magicS64, magicU32, magicU64};
use divconst_magic_numbers::{MS32, MS64, MU32, MU64};
use ir::dfg::ValueDef;
use ir::instructions::Opcode;
use ir::types::{I32, I64};
use ir::Inst;
use ir::{DataFlowGraph, Function, InstBuilder, InstructionData, Type, Value};
use timing;
use crate::cursor::{Cursor, FuncCursor};
use crate::divconst_magic_numbers::{magicS32, magicS64, magicU32, magicU64};
use crate::divconst_magic_numbers::{MS32, MS64, MU32, MU64};
use crate::ir::dfg::ValueDef;
use crate::ir::instructions::Opcode;
use crate::ir::types::{I32, I64};
use crate::ir::Inst;
use crate::ir::{DataFlowGraph, Function, InstBuilder, InstructionData, Type, Value};
use crate::timing;
//----------------------------------------------------------------------
//

14
lib/codegen/src/stack_layout.rs
View File

@@ -1,8 +1,8 @@
//! Computing stack layout.
use ir::stackslot::{StackOffset, StackSize, StackSlotKind};
use ir::StackSlots;
use result::{CodegenError, CodegenResult};
use crate::ir::stackslot::{StackOffset, StackSize, StackSlotKind};
use crate::ir::StackSlots;
use crate::result::{CodegenError, CodegenResult};
use std::cmp::{max, min};
/// Compute the stack frame layout.
@@ -111,10 +111,10 @@ pub fn layout_stack(frame: &mut StackSlots, alignment: StackSize) -> CodegenResu
#[cfg(test)]
mod tests {
use super::layout_stack;
use ir::stackslot::StackOffset;
use ir::types;
use ir::{StackSlotData, StackSlotKind, StackSlots};
use result::CodegenError;
use crate::ir::stackslot::StackOffset;
use crate::ir::types;
use crate::ir::{StackSlotData, StackSlotKind, StackSlots};
use crate::result::CodegenError;
#[test]
fn layout() {

1
lib/codegen/src/timing.rs
View File

@@ -102,6 +102,7 @@ impl fmt::Display for Pass {
#[cfg(feature = "std")]
mod details {
use super::{Pass, DESCRIPTIONS, NUM_PASSES};
use log::debug;
use std::cell::{Cell, RefCell};
use std::fmt;
use std::mem;

14
lib/codegen/src/topo_order.rs
View File

@@ -1,8 +1,8 @@
//! Topological order of EBBs, according to the dominator tree.
use dominator_tree::DominatorTree;
use entity::SparseSet;
use ir::{Ebb, Layout};
use crate::dominator_tree::DominatorTree;
use crate::entity::SparseSet;
use crate::ir::{Ebb, Layout};
use std::vec::Vec;
/// Present EBBs in a topological order such that all dominating EBBs are guaranteed to be visited
@@ -90,10 +90,10 @@ impl TopoOrder {
#[cfg(test)]
mod tests {
use super::*;
use cursor::{Cursor, FuncCursor};
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::{Function, InstBuilder};
use crate::cursor::{Cursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir::{Function, InstBuilder};
use std::iter;
#[test]

11
lib/codegen/src/unreachable_code.rs
View File

@@ -1,10 +1,11 @@
//! Unreachable code elimination.
use cursor::{Cursor, FuncCursor};
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir;
use timing;
use crate::cursor::{Cursor, FuncCursor};
use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir;
use crate::timing;
use log::debug;
/// Eliminate unreachable code.
///

16
lib/codegen/src/verifier/cssa.rs
View File

@@ -1,13 +1,13 @@
//! Verify conventional SSA form.
use dbg::DisplayList;
use dominator_tree::{DominatorTree, DominatorTreePreorder};
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::{ExpandedProgramPoint, Function};
use regalloc::liveness::Liveness;
use regalloc::virtregs::VirtRegs;
use timing;
use verifier::{VerifierErrors, VerifierStepResult};
use crate::dbg::DisplayList;
use crate::dominator_tree::{DominatorTree, DominatorTreePreorder};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::{ExpandedProgramPoint, Function};
use crate::regalloc::liveness::Liveness;
use crate::regalloc::virtregs::VirtRegs;
use crate::timing;
use crate::verifier::{VerifierErrors, VerifierStepResult};
/// Verify conventional SSA form for `func`.
///

16
lib/codegen/src/verifier/flags.rs
View File

@@ -1,13 +1,13 @@
//! Verify CPU flags values.
use entity::{SecondaryMap, SparseSet};
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir;
use ir::instructions::BranchInfo;
use isa;
use packed_option::PackedOption;
use timing;
use verifier::{VerifierErrors, VerifierStepResult};
use crate::entity::{SecondaryMap, SparseSet};
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir;
use crate::ir::instructions::BranchInfo;
use crate::isa;
use crate::packed_option::PackedOption;
use crate::timing;
use crate::verifier::{VerifierErrors, VerifierStepResult};
/// Verify that CPU flags are used correctly.
///

16
lib/codegen/src/verifier/liveness.rs
View File

@@ -1,14 +1,14 @@
//! Liveness verifier.
use flowgraph::{BasicBlock, ControlFlowGraph};
use ir::entities::AnyEntity;
use ir::{ExpandedProgramPoint, Function, Inst, ProgramOrder, ProgramPoint, Value};
use isa::TargetIsa;
use regalloc::liveness::Liveness;
use regalloc::liverange::LiveRange;
use crate::flowgraph::{BasicBlock, ControlFlowGraph};
use crate::ir::entities::AnyEntity;
use crate::ir::{ExpandedProgramPoint, Function, Inst, ProgramOrder, ProgramPoint, Value};
use crate::isa::TargetIsa;
use crate::regalloc::liveness::Liveness;
use crate::regalloc::liverange::LiveRange;
use crate::timing;
use crate::verifier::{VerifierErrors, VerifierStepResult};
use std::cmp::Ordering;
use timing;
use verifier::{VerifierErrors, VerifierStepResult};
/// Verify liveness information for `func`.
///

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