aarch64: Migrate {s,u}{sub,add}_sat to ISLE (#3551)

These were pretty straightforward! Only needed a single `rule` per
instruction with a new 128-bit vector type matcher.

cranelift/codegen/src/machinst/isle.rs

@@ -108,6 +108,14 @@ macro_rules! isle_prelude_methods {
             }
         }
 
+        fn vec128(&mut self, ty: Type) -> Option<Type> {
+            if ty.is_vector() && ty.bits() == 128 {
+                Some(ty)
+            } else {
+                None
+            }
+        }
+
         #[inline]
         fn value_list_slice(&mut self, list: ValueList) -> ValueSlice {
             list.as_slice(&self.lower_ctx.dfg().value_lists)