From ef8a1340dfe168d97c600f69c1edf15c0830734b Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Tue, 28 Feb 2023 10:48:14 +0000 Subject: [PATCH] fuzzgen: Disable unaligned atomics for RISCV (#5883) * fuzzgen: Disable unaligned atomics for RISCV * riscv64: Cleanup atomic alignment logic Co-authored-by: Jamey Sharp --------- Co-authored-by: Jamey Sharp --- cranelift/fuzzgen/src/function_generator.rs | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs index a0653cce32..37c504d215 100644 --- a/cranelift/fuzzgen/src/function_generator.rs +++ b/cranelift/fuzzgen/src/function_generator.rs @@ -647,6 +647,8 @@ fn valid_for_target(triple: &Triple, op: Opcode, args: &[Type], rets: &[Type]) - // TODO (Opcode::BxorNot, &[F32, F32]), (Opcode::BxorNot, &[F64, F64]), + // https://github.com/bytecodealliance/wasmtime/issues/5884 + (Opcode::AtomicRmw), ) } @@ -1493,10 +1495,14 @@ where is_atomic: bool, ) -> Result<(Value, MemFlags, Offset32)> { // Should we generate an aligned address - let is_aarch64 = matches!(self.target_triple.architecture, Architecture::Aarch64(_)); - let aligned = if is_atomic && is_aarch64 { - // AArch64 has issues with unaligned atomics. - // https://github.com/bytecodealliance/wasmtime/issues/5483 + // Some backends have issues with unaligned atomics. + // AArch64: https://github.com/bytecodealliance/wasmtime/issues/5483 + // RISCV: https://github.com/bytecodealliance/wasmtime/issues/5882 + let requires_aligned_atomics = matches!( + self.target_triple.architecture, + Architecture::Aarch64(_) | Architecture::Riscv64(_) + ); + let aligned = if is_atomic && requires_aligned_atomics { true } else { bool::arbitrary(self.u)?