machinst/x64: teach regalloc what FP instructions are moves;

and cosmetic changes after #1665 landed.

cranelift/codegen/src/isa/x64/abi.rs

@@ -315,9 +315,7 @@ impl ABIBody for X64ABIBody {
                         from_reg.to_reg(),
                         Writable::<Reg>::from_reg(to_reg.to_reg()),
                     ))
-                } else if to_reg.get_class() == RegClass::V128
-                    || to_reg.get_class() == RegClass::V128
-                {
+                } else if to_reg.get_class() == RegClass::V128 {
                     ret.push(Inst::xmm_r_r(
                         SSE_Op::SSE2_Movsd,
                         from_reg.to_reg(),

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -811,6 +811,11 @@ impl MachInst for Inst {
         // %reg.
         match self {
             Self::Mov_R_R { is_64, src, dst } if *is_64 => Some((*dst, *src)),
+            Self::XMM_R_R { op, src, dst }
+                if *op == SSE_Op::SSE_Movss || *op == SSE_Op::SSE2_Movsd =>
+            {
+                Some((*dst, *src))
+            }
             _ => None,
         }
     }

cranelift/codegen/src/machinst/vcode.rs

@@ -137,13 +137,10 @@ impl<I: VCodeInst> VCodeBuilder<I> {
     /// Set the type of a VReg.
     pub fn set_vreg_type(&mut self, vreg: VirtualReg, ty: Type) {
         if self.vcode.vreg_types.len() <= vreg.get_index() {
-            self.vcode.vreg_types.resize(
-                self.vcode.vreg_types.len()
-                    + ((vreg.get_index() + 1) - self.vcode.vreg_types.len()),
-                ir::types::I8,
-            )
+            self.vcode
+                .vreg_types
+                .resize(vreg.get_index() + 1, ir::types::I8);
         }
-
         self.vcode.vreg_types[vreg.get_index()] = ty;
     }