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Cranelift AArch64: Various small fixes

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* Use FMOV to move 64-bit FP registers and SIMD vectors.
* Add support for additional vector load types.
* Fix the printing of Inst::LoadAddr.

Copyright (c) 2020, Arm Limited.
This commit is contained in:
Anton Kirilov
2020-10-30 13:14:51 +00:00
parent 19640367db
commit edaada3f57
5 changed files with 141 additions and 66 deletions
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4
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -4219,8 +4219,8 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(4),
},
"881CA40E",
"mov v8.8b, v4.8b",
"8840601E",
"fmov d8, d4",
));
insns.push((