diff --git a/cranelift/filetests/isa/intel/binary64-pic.cton b/cranelift/filetests/isa/intel/binary64-pic.cton new file mode 100644 index 0000000000..fa422741e4 --- /dev/null +++ b/cranelift/filetests/isa/intel/binary64-pic.cton @@ -0,0 +1,54 @@ +; binary emission of 64-bit code. +test binemit +set is_64bit +set is_compressed +set is_pic +isa intel haswell + +; The binary encodings can be verified with the command: +; +; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-pic.cton | llvm-mc -show-encoding -triple=x86_64 +; + +; Tests for i64 instructions. +function %I64() { + fn0 = function %foo() + sig0 = () + + gv0 = globalsym %some_gv + + ; Use incoming_arg stack slots because they won't be relocated by the frame + ; layout. + ss0 = incoming_arg 8, offset 0 + ss1 = incoming_arg 1024, offset -1024 + ss2 = incoming_arg 1024, offset -2048 + ss3 = incoming_arg 8, offset -2056 + +ebb0: + + ; asm: call foo@PLT + call fn0() ; bin: e8 PLTRel4(%foo) 00000000 + + ; asm: mov 0x0(%rip), %rax + [-,%rax] v0 = func_addr.i64 fn0 ; bin: 48 8b 05 GotPCRel4(%foo) 00000000 + ; asm: mov 0x0(%rip), %rsi + [-,%rsi] v1 = func_addr.i64 fn0 ; bin: 48 8b 35 GotPCRel4(%foo) 00000000 + ; asm: mov 0x0(%rip), %r10 + [-,%r10] v2 = func_addr.i64 fn0 ; bin: 4c 8b 15 GotPCRel4(%foo) 00000000 + + ; asm: call *%rax + call_indirect sig0, v0() ; bin: ff d0 + ; asm: call *%rsi + call_indirect sig0, v1() ; bin: ff d6 + ; asm: call *%r10 + call_indirect sig0, v2() ; bin: 41 ff d2 + + ; asm: mov 0x0(%rip), %rcx + [-,%rcx] v3 = globalsym_addr.i64 gv0 ; bin: 48 8b 0d GotPCRel4(%some_gv) 00000000 + ; asm: mov 0x0(%rip), %rsi + [-,%rsi] v4 = globalsym_addr.i64 gv0 ; bin: 48 8b 35 GotPCRel4(%some_gv) 00000000 + ; asm: mov 0x0(%rip), %r10 + [-,%r10] v5 = globalsym_addr.i64 gv0 ; bin: 4c 8b 15 GotPCRel4(%some_gv) 00000000 + + return +}