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Remove =x uses from ISLE, and remove support from the DSL compiler. (#4078)

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This is a follow-up on #4074: now that we have the simplified syntax, we
can remove the old, redundant syntax.
This commit is contained in:
Chris Fallin
2022-04-28 11:17:08 -07:00
committed by GitHub
parent 477d394288
commit eceb433b28
8 changed files with 78 additions and 89 deletions
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2
cranelift/codegen/src/isa/x64/inst.isle
View File

@@ -1222,7 +1222,7 @@
(decl extend_to_gpr (Value Type ExtendKind) Gpr)
;; If the value is already of the requested type, no extending is necessary.
(rule (extend_to_gpr (and val (value_type ty)) =ty _kind)
(rule (extend_to_gpr (and val (value_type ty)) ty _kind)
(put_in_gpr val))
(rule (extend_to_gpr (and val (value_type from_ty))

62
cranelift/codegen/src/isa/x64/lower.isle
View File

@@ -2111,7 +2111,7 @@
;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; T -> T is a no-op.
(rule (lower (has_type ty (uextend src @ (value_type =ty))))
(rule (lower (has_type ty (uextend src @ (value_type ty))))
src)
;; I64 -> I128.
@@ -2177,7 +2177,7 @@
(decl generic_sextend (Value Type Type) InstOutput)
;; T -> T is a no-op.
(rule (generic_sextend src ty =ty)
(rule (generic_sextend src ty ty)
src)
;; Produce upper 64 bits sign-extended from lower 64: shift right by
@@ -2218,7 +2218,7 @@
;; Rules for `ireduce` / `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; T -> T is always a no-op, even I128 -> I128.
(rule (lower (has_type ty (ireduce src @ (value_type =ty))))
(rule (lower (has_type ty (ireduce src @ (value_type ty))))
src)
;; T -> I{64,32,16,8}: We can simply pass through the value: values
@@ -2229,7 +2229,7 @@
;; Likewise for breduce.
(rule (lower (has_type ty (breduce src @ (value_type =ty))))
(rule (lower (has_type ty (breduce src @ (value_type ty))))
src)
(rule (lower (has_type (fits_in_64 ty) (breduce src)))
@@ -2660,126 +2660,126 @@
;; Add mem, reg
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(iadd (and
(sinkable_load sink)
(load flags addr offset))
src2))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_add_mem ty (to_amode flags addr offset) src2))))
;; Add mem, reg with args swapped
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(iadd src2
(and
(sinkable_load sink)
(load flags addr offset))))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_add_mem ty (to_amode flags addr offset) src2))))
;; Sub mem, reg
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(isub (and
(sinkable_load sink)
(load flags addr offset))
src2))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_sub_mem ty (to_amode flags addr offset) src2))))
;; And mem, reg
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(band (and
(sinkable_load sink)
(load flags addr offset))
src2))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_and_mem ty (to_amode flags addr offset) src2))))
;; And mem, reg with args swapped
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(band src2
(and
(sinkable_load sink)
(load flags addr offset))))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_and_mem ty (to_amode flags addr offset) src2))))
;; Or mem, reg
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(bor (and
(sinkable_load sink)
(load flags addr offset))
src2))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_or_mem ty (to_amode flags addr offset) src2))))
;; Or mem, reg with args swapped
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(bor src2
(and
(sinkable_load sink)
(load flags addr offset))))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_or_mem ty (to_amode flags addr offset) src2))))
;; Xor mem, reg
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(bxor (and
(sinkable_load sink)
(load flags addr offset))
src2))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_xor_mem ty (to_amode flags addr offset) src2))))
;; Xor mem, reg with args swapped
(rule (lower
(store =flags
(store flags
(has_type (ty_32_or_64 ty)
(bxor src2
(and
(sinkable_load sink)
(load flags addr offset))))
=addr
=offset))
addr
offset))
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_xor_mem ty (to_amode flags addr offset) src2))))

4
cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest
View File

@@ -1,4 +1,4 @@
src/clif.isle 443b34b797fc8ace
src/prelude.isle a7915a6b88310eb5
src/isa/x64/inst.isle 6dcba190988a695
src/isa/x64/lower.isle b95161bdf07b9365
src/isa/x64/inst.isle a63b8ede292f2e20
src/isa/x64/lower.isle 4c567e9157f84afb