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Merge pull request #3290 from dheaton-arm/implement-ssatarith

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Implement `SaddSat` and `SsubSat` for the Cranelift interpreter
This commit is contained in:
Chris Fallin
2021-09-03 09:48:34 -07:00
committed by GitHub
parent c33700087d 8f057e0482
commit ecd795f736
7 changed files with 93 additions and 3 deletions
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6
cranelift/codegen/src/ir/immediates.rs
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@@ -26,6 +26,12 @@ impl IntoBytes for u8 {
}
}
impl IntoBytes for i8 {
fn into_bytes(self) -> Vec<u8> {
vec![self as u8]
}
}
impl IntoBytes for i16 {
fn into_bytes(self) -> Vec<u8> {
self.to_le_bytes().to_vec()

17
cranelift/filetests/filetests/runtests/simd-saddsat-aarch64.clif Normal file
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@@ -0,0 +1,17 @@
test interpret
test run
target aarch64
function %saddsat_i32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = sadd_sat v0, v1
return v2
}
; run: %saddsat_i32x4([256 -2147483000 2147483000 2147483000], [256 -1000 1000 1000]) == [512 -2147483648 2147483647 2147483647]
function %saddsat_i64x2(i64x2, i64x2) -> i64x2 {
block0(v0: i64x2, v1: i64x2):
v2 = sadd_sat v0, v1
return v2
}
; run: %saddsat_i64x2([-9223372036854775000 9223372036854775000], [-1000 1000]) == [-9223372036854775808 9223372036854775807]

19
cranelift/filetests/filetests/runtests/simd-saddsat.clif Normal file
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@@ -0,0 +1,19 @@
test interpret
test run
target aarch64
set enable_simd
target x86_64
function %saddsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):
v2 = sadd_sat v0, v1
return v2
}
; run: %saddsat_i8x16([1 100 100 100 100 100 100 100 -100 -100 -100 -100 -100 -100 -100 -100], [1 100 100 100 100 100 100 100 -100 -100 -100 -100 -100 -100 -100 -100]) == [2 127 127 127 127 127 127 127 -128 -128 -128 -128 -128 -128 -128 -128]
function %saddsat_i16x8(i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8):
v2 = sadd_sat v0, v1
return v2
}
; run: %saddsat_i16x8([1 -32000 -32000 -32000 32000 32000 32000 32000], [1 -1000 -1000 -1000 1000 1000 1000 1000]) == [2 -32768 -32768 -32768 32767 32767 32767 32767]

17
cranelift/filetests/filetests/runtests/simd-ssubsat-aarch64.clif Normal file
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@@ -0,0 +1,17 @@
test interpret
test run
target aarch64
function %ssubsat_i32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = ssub_sat v0, v1
return v2
}
; run: %ssubsat_i32x4([256 -2147483000 2147483000 2147483000], [256 1000 -1000 -1000]) == [0 -2147483648 2147483647 2147483647]
function %ssubsat_i64x2(i64x2, i64x2) -> i64x2 {
block0(v0: i64x2, v1: i64x2):
v2 = ssub_sat v0, v1
return v2
}
; run: %ssubsat_i64x2([-9223372036854775000 9223372036854775000], [1000 -1000]) == [-9223372036854775808 9223372036854775807]

19
cranelift/filetests/filetests/runtests/simd-ssubsat.clif Normal file
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@@ -0,0 +1,19 @@
test interpret
test run
target aarch64
set enable_simd
target x86_64
function %ssubsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):
v2 = ssub_sat v0, v1
return v2
}
; run: %ssubsat_i8x16([1 100 100 100 100 100 100 100 -100 -100 -100 -100 -100 -100 -100 -100], [1 -100 -100 -100 -100 -100 -100 -100 100 100 100 100 100 100 100 100]) == [0 127 127 127 127 127 127 127 -128 -128 -128 -128 -128 -128 -128 -128]
function %ssubsat_i16x8(i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8):
v2 = ssub_sat v0, v1
return v2
}
; run: %ssubsat_i16x8([1 -32000 -32000 -32000 32000 32000 32000 32000], [1 1000 1000 1000 -1000 -1000 -1000 -1000]) == [0 -32768 -32768 -32768 32767 32767 32767 32767]

16
cranelift/interpreter/src/step.rs
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@@ -503,7 +503,13 @@ where
Value::add_sat,
true,
)?),
Opcode::SaddSat => unimplemented!("SaddSat"),
Opcode::SaddSat => assign(binary_arith(
arg(0)?,
arg(1)?,
ctrl_ty,
Value::add_sat,
false,
)?),
Opcode::Isub => binary(Value::sub, arg(0)?, arg(1)?)?,
Opcode::UsubSat => assign(binary_arith(
arg(0)?,
@@ -512,7 +518,13 @@ where
Value::sub_sat,
true,
)?),
Opcode::SsubSat => unimplemented!("SsubSat"),
Opcode::SsubSat => assign(binary_arith(
arg(0)?,
arg(1)?,
ctrl_ty,
Value::sub_sat,
false,
)?),
Opcode::Ineg => binary(Value::sub, Value::int(0, ctrl_ty)?, arg(0)?)?,
Opcode::Iabs => unimplemented!("Iabs"),
Opcode::Imul => binary(Value::mul, arg(0)?, arg(1)?)?,

2
cranelift/reader/src/parser.rs
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@@ -1106,7 +1106,7 @@ impl<'a> Parser<'a> {
err!(self.loc, "Expected a controlling vector type, not {}", ty)
} else {
let constant_data = match ty.lane_type() {
I8 => consume!(ty, self.match_uimm8("Expected an 8-bit unsigned integer")?),
I8 => consume!(ty, self.match_imm8("Expected an 8-bit integer")?),
I16 => consume!(ty, self.match_imm16("Expected a 16-bit integer")?),
I32 => consume!(ty, self.match_imm32("Expected a 32-bit integer")?),
I64 => consume!(ty, self.match_imm64("Expected a 64-bit integer")?),