s390x: use full vector register file for FP operations (#4360)

This defines the full set of 32 128-bit vector registers on s390x.
(Note that the VRs overlap the existing FPRs.)  In addition, this
adds support to use all 32 vector registers to implement floating-
point operations, by using vector floating-point instructions with
the 'W' bit set to operate only on the first element.

This part of the vector instruction set mostly matches the old FP
instruction set, with two exceptions:

- There is no vector version of the COPY SIGN instruction.  Instead,
  now use a VECTOR SELECT with an appropriate bit mask to implement
  the fcopysign operation.

- There are no vector version of the float <-> int conversion
  instructions where source and target differ in bit size.  Use
  appropriate multiple conversion steps instead.  This also requires
  use of explicit checking to implement correct overflow handling.
  As a side effect, this version now also implements the i8 / i16
  variants of all conversions, which had been missing so far.

For all operations except those two above, we continue to use the
old FP instruction if applicable (i.e. if all operands happen to
have been allocated to the original FP register set), and use the
vector instruction otherwise.

cranelift/codegen/src/isa/s390x/inst/unwind/systemv.rs

@@ -45,7 +45,7 @@ pub fn map_reg(reg: Reg) -> Result<Register, RegisterMappingError> {
         Register(14),
         Register(15),
     ];
-    const FPR_MAP: [gimli::Register; 16] = [
+    const VR_MAP: [gimli::Register; 32] = [
         Register(16),
         Register(20),
         Register(17),
@@ -62,11 +62,27 @@ pub fn map_reg(reg: Reg) -> Result<Register, RegisterMappingError> {
         Register(30),
         Register(27),
         Register(31),
+        Register(68),
+        Register(72),
+        Register(69),
+        Register(73),
+        Register(70),
+        Register(74),
+        Register(71),
+        Register(75),
+        Register(76),
+        Register(80),
+        Register(77),
+        Register(81),
+        Register(78),
+        Register(82),
+        Register(79),
+        Register(83),
     ];
 
     match reg.class() {
         RegClass::Int => Ok(GPR_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]),
-        RegClass::Float => Ok(FPR_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]),
+        RegClass::Float => Ok(VR_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]),
     }
 }