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Add Intel encodings for more conversion instructions.

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The following instructions have simple encodings:

- bitcast.f32.i32
- bitcast.i32.f32
- bitcast.f64.i64
- bitcast.i64.f64
- fpromote.f64.f32
- fdemote.f32.f64

Also add helper functions enc_flt() and enc_i32_i64 to
intel.encodings.py for generating the common set of encodings for an
instruction: I32, I64 w/REX, I64 w/o REX.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-27 10:58:00 -07:00
parent 06bab60fcc
commit ebf5c80959
5 changed files with 195 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
filetests/isa/intel/binary64-float.cton
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@@ -25,27 +25,42 @@ ebb0:
; asm: cvtsi2ssq %r14, %xmm10
[-,%xmm10] v13 = fcvt_from_sint.f32 v3 ; bin: f3 4d 0f 2a d6
; asm: cvtss2sd %xmm10, %xmm5
[-,%xmm5] v14 = fpromote.f64 v11 ; bin: f3 41 0f 5a ea
; asm: cvtss2sd %xmm5, %xmm10
[-,%xmm10] v15 = fpromote.f64 v10 ; bin: f3 44 0f 5a d5
; asm: movd %r11d, %xmm5
[-,%xmm5] v16 = bitcast.f32 v0 ; bin: 66 41 0f 6e eb
; asm: movd %esi, %xmm10
[-,%xmm10] v17 = bitcast.f32 v1 ; bin: 66 44 0f 6e d6
; asm: movd %xmm5, %ecx
[-,%rcx] v18 = bitcast.i32 v10 ; bin: 66 40 0f 7e e9
; asm: movd %xmm10, %esi
[-,%rsi] v19 = bitcast.i32 v11 ; bin: 66 44 0f 7e d6
; Binary arithmetic.
; asm: addss %xmm10, %xmm5
[-,%xmm5] v20 = fadd v10, v11 ; bin: f3 41 0f 58 ea
; asm: addss %xmm5, %xmm10
[-,%xmm10] v21 = fadd v11, v10 ; bin: f3 44 0f 58 d5
[-,%xmm10] v21 = fadd v11, v10 ; bin: f3 44 0f 58 d5
; asm: subss %xmm10, %xmm5
[-,%xmm5] v22 = fsub v10, v11 ; bin: f3 41 0f 5c ea
; asm: subss %xmm5, %xmm10
[-,%xmm10] v23 = fsub v11, v10 ; bin: f3 44 0f 5c d5
[-,%xmm10] v23 = fsub v11, v10 ; bin: f3 44 0f 5c d5
; asm: mulss %xmm10, %xmm5
[-,%xmm5] v24 = fmul v10, v11 ; bin: f3 41 0f 59 ea
; asm: mulss %xmm5, %xmm10
[-,%xmm10] v25 = fmul v11, v10 ; bin: f3 44 0f 59 d5
[-,%xmm10] v25 = fmul v11, v10 ; bin: f3 44 0f 59 d5
; asm: divss %xmm10, %xmm5
[-,%xmm5] v26 = fdiv v10, v11 ; bin: f3 41 0f 5e ea
; asm: divss %xmm5, %xmm10
[-,%xmm10] v27 = fdiv v11, v10 ; bin: f3 44 0f 5e d5
[-,%xmm10] v27 = fdiv v11, v10 ; bin: f3 44 0f 5e d5
; Bitwise ops.
; We use the *ps SSE instructions for everything because they are smaller.
@@ -90,12 +105,27 @@ ebb0:
; asm: cvtsi2sdq %r14, %xmm10
[-,%xmm10] v13 = fcvt_from_sint.f64 v3 ; bin: f2 4d 0f 2a d6
; asm: cvtsd2ss %xmm10, %xmm5
[-,%xmm5] v14 = fdemote.f32 v11 ; bin: f2 41 0f 5a ea
; asm: cvtsd2ss %xmm5, %xmm10
[-,%xmm10] v15 = fdemote.f32 v10 ; bin: f2 44 0f 5a d5
; asm: movq %rax, %xmm5
[-,%xmm5] v16 = bitcast.f64 v2 ; bin: 66 48 0f 6e e8
; asm: movq %r14, %xmm10
[-,%xmm10] v17 = bitcast.f64 v3 ; bin: 66 4d 0f 6e d6
; asm: movq %xmm5, %rcx
[-,%rcx] v18 = bitcast.i64 v10 ; bin: 66 48 0f 7e e9
; asm: movq %xmm10, %rsi
[-,%rsi] v19 = bitcast.i64 v11 ; bin: 66 4c 0f 7e d6
; Binary arithmetic.
; asm: addsd %xmm10, %xmm5
[-,%xmm5] v20 = fadd v10, v11 ; bin: f2 41 0f 58 ea
; asm: addsd %xmm5, %xmm10
[-,%xmm10] v21 = fadd v11, v10 ; bin: f2 44 0f 58 d5
[-,%xmm10] v21 = fadd v11, v10 ; bin: f2 44 0f 58 d5
; asm: subsd %xmm10, %xmm5
[-,%xmm5] v22 = fsub v10, v11 ; bin: f2 41 0f 5c ea