Illegalize rbp/r13 for zero-offset loads on Intel x64 (#225)

* Switch RegClass to a bitmap implementation.

* Add special RegClass to remove r13 from 'ld' recipe.

* Use MASK_LEN constant instead of magic number.

* Enforce that RegClass slicing is only valid on contiguous classes.

* Use Optional[int] for RegClass optional bitmask parameter.

* Add comment explaining use of Intel ISA's GPR_NORIP register class.

lib/cretonne/meta/gen_registers.py

@@ -59,7 +59,7 @@ def gen_regclass(rc, fmt):
         fmt.format('width: {},', rc.width)
         fmt.format('bank: {},', rc.bank.index)
         fmt.format('toprc: {},', rc.toprc.index)
-        fmt.format('first: {},', rc.bank.first_unit + rc.start)
+        fmt.format('first: {},', rc.bank.first_unit + rc.start())
         fmt.format('subclasses: 0x{:x},', rc.subclass_mask())
         mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
         fmt.format('mask: [{}],', mask)