Flatten directory structure for cranelift_codegen_meta::isa
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bjorn3
224
cranelift/codegen/meta/src/isa/x86.rs
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224
cranelift/codegen/meta/src/isa/x86.rs
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
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use crate::shared::Definitions as SharedDefinitions;
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pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = define_settings(&shared_defs.settings);
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TargetIsa::new("x86", settings)
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}
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pub(crate) fn define_settings(shared: &SettingGroup) -> SettingGroup {
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let mut settings = SettingGroupBuilder::new("x86");
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// CPUID.01H:ECX
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let has_sse3 = settings.add_bool(
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"has_sse3",
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"Has support for SSE3.",
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"SSE3: CPUID.01H:ECX.SSE3[bit 0]",
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false,
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);
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let has_ssse3 = settings.add_bool(
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"has_ssse3",
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"Has support for SSSE3.",
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"SSSE3: CPUID.01H:ECX.SSSE3[bit 9]",
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false,
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);
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let has_sse41 = settings.add_bool(
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"has_sse41",
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"Has support for SSE4.1.",
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"SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]",
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false,
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);
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let has_sse42 = settings.add_bool(
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"has_sse42",
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"Has support for SSE4.2.",
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"SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]",
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false,
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);
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let has_avx = settings.add_bool(
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"has_avx",
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"Has support for AVX.",
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"AVX: CPUID.01H:ECX.AVX[bit 28]",
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false,
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);
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let has_avx2 = settings.add_bool(
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"has_avx2",
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"Has support for AVX2.",
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"AVX2: CPUID.07H:EBX.AVX2[bit 5]",
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false,
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);
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let has_avx512bitalg = settings.add_bool(
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"has_avx512bitalg",
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"Has support for AVX512BITALG.",
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"AVX512BITALG: CPUID.07H:ECX.AVX512BITALG[bit 12]",
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false,
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);
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let has_avx512dq = settings.add_bool(
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"has_avx512dq",
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"Has support for AVX512DQ.",
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"AVX512DQ: CPUID.07H:EBX.AVX512DQ[bit 17]",
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false,
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);
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let has_avx512vl = settings.add_bool(
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"has_avx512vl",
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"Has support for AVX512VL.",
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"AVX512VL: CPUID.07H:EBX.AVX512VL[bit 31]",
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false,
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);
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let has_avx512vbmi = settings.add_bool(
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"has_avx512vbmi",
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"Has support for AVX512VMBI.",
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"AVX512VBMI: CPUID.07H:ECX.AVX512VBMI[bit 1]",
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false,
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);
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let has_avx512f = settings.add_bool(
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"has_avx512f",
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"Has support for AVX512F.",
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"AVX512F: CPUID.07H:EBX.AVX512F[bit 16]",
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false,
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);
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let has_popcnt = settings.add_bool(
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"has_popcnt",
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"Has support for POPCNT.",
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"POPCNT: CPUID.01H:ECX.POPCNT[bit 23]",
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false,
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);
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// CPUID.(EAX=07H, ECX=0H):EBX
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let has_bmi1 = settings.add_bool(
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"has_bmi1",
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"Has support for BMI1.",
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"BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
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false,
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);
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let has_bmi2 = settings.add_bool(
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"has_bmi2",
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"Has support for BMI2.",
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"BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
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false,
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);
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// CPUID.EAX=80000001H:ECX
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let has_lzcnt = settings.add_bool(
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"has_lzcnt",
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"Has support for LZCNT.",
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"LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
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false,
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);
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let shared_enable_simd = shared.get_bool("enable_simd");
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settings.add_predicate("use_ssse3", predicate!(has_ssse3));
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settings.add_predicate("use_sse41", predicate!(has_sse41));
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settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
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settings.add_predicate(
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"use_ssse3_simd",
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predicate!(shared_enable_simd && has_ssse3),
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);
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settings.add_predicate(
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"use_sse41_simd",
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predicate!(shared_enable_simd && has_sse41),
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);
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settings.add_predicate(
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"use_sse42_simd",
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predicate!(shared_enable_simd && has_sse41 && has_sse42),
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);
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settings.add_predicate("use_avx_simd", predicate!(shared_enable_simd && has_avx));
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settings.add_predicate("use_avx2_simd", predicate!(shared_enable_simd && has_avx2));
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settings.add_predicate(
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"use_avx512bitalg_simd",
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predicate!(shared_enable_simd && has_avx512bitalg),
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);
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settings.add_predicate(
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"use_avx512dq_simd",
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predicate!(shared_enable_simd && has_avx512dq),
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);
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settings.add_predicate(
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"use_avx512vl_simd",
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predicate!(shared_enable_simd && has_avx512vl),
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);
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settings.add_predicate(
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"use_avx512vbmi_simd",
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predicate!(shared_enable_simd && has_avx512vbmi),
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);
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settings.add_predicate(
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"use_avx512f_simd",
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predicate!(shared_enable_simd && has_avx512f),
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);
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settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
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settings.add_predicate("use_bmi1", predicate!(has_bmi1));
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settings.add_predicate("use_lzcnt", predicate!(has_lzcnt));
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// Some shared boolean values are used in x86 instruction predicates, so we need to group them
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// in the same TargetIsa, for compatibility with code generated by meta-python.
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// TODO Once all the meta generation code has been migrated from Python to Rust, we can put it
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// back in the shared SettingGroup, and use it in x86 instruction predicates.
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let is_pic = shared.get_bool("is_pic");
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let emit_all_ones_funcaddrs = shared.get_bool("emit_all_ones_funcaddrs");
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settings.add_predicate("is_pic", predicate!(is_pic));
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settings.add_predicate("not_is_pic", predicate!(!is_pic));
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settings.add_predicate(
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"all_ones_funcaddrs_and_not_is_pic",
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predicate!(emit_all_ones_funcaddrs && !is_pic),
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);
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settings.add_predicate(
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"not_all_ones_funcaddrs_and_not_is_pic",
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predicate!(!emit_all_ones_funcaddrs && !is_pic),
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);
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// Presets corresponding to x86 CPUs.
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settings.add_preset(
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"baseline",
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"A baseline preset with no extensions enabled.",
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preset!(),
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);
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let nehalem = settings.add_preset(
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"nehalem",
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"Nehalem microarchitecture.",
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preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
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);
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let haswell = settings.add_preset(
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"haswell",
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"Haswell microarchitecture.",
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preset!(nehalem && has_bmi1 && has_bmi2 && has_lzcnt),
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);
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let broadwell = settings.add_preset(
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"broadwell",
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"Broadwell microarchitecture.",
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preset!(haswell),
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);
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let skylake = settings.add_preset("skylake", "Skylake microarchitecture.", preset!(broadwell));
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let cannonlake = settings.add_preset(
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"cannonlake",
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"Canon Lake microarchitecture.",
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preset!(skylake),
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);
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settings.add_preset(
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"icelake",
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"Ice Lake microarchitecture.",
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preset!(cannonlake),
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);
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settings.add_preset(
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"znver1",
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"Zen (first generation) microarchitecture.",
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preset!(
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has_sse3
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&& has_ssse3
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&& has_sse41
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&& has_sse42
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&& has_popcnt
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&& has_bmi1
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&& has_bmi2
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&& has_lzcnt
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),
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);
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settings.build()
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}
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