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Disassembler support for RV32/64

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This commit is contained in:
Qiu Wenbo
2021-07-19 17:31:28 +08:00
parent f628d06118
commit eafd10c1e8
1 changed files with 21 additions and 2 deletions
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23
cranelift/src/disasm.rs
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@@ -111,8 +111,27 @@ cfg_if! {
fn get_disassembler(isa: &dyn TargetIsa) -> Result<Capstone> { fn get_disassembler(isa: &dyn TargetIsa) -> Result<Capstone> {
let cs = match isa.triple().architecture { let cs = match isa.triple().architecture {
Architecture::Riscv32(_) | Architecture::Riscv64(_) => { Architecture::Riscv32(_) => {
anyhow::bail!("No disassembler for RiscV"); let mut cs = Capstone::new()
.riscv()
.mode(arch::riscv::ArchMode::RiscV32)
.extra_mode(std::iter::once(arch::riscv::ArchExtraMode::RiscVC))
.build()
.map_err(map_caperr)?;
// See the comment of AArch64 below
cs.set_skipdata(true).map_err(map_caperr)?;
cs
}
Architecture::Riscv64(_) => {
let mut cs = Capstone::new()
.riscv()
.mode(arch::riscv::ArchMode::RiscV64)
.extra_mode(std::iter::once(arch::riscv::ArchExtraMode::RiscVC))
.build()
.map_err(map_caperr)?;
// See the comment of AArch64 below
cs.set_skipdata(true).map_err(map_caperr)?;
cs
} }
Architecture::X86_32(_) => Capstone::new() Architecture::X86_32(_) => Capstone::new()
.x86() .x86()