machinst x64: add more FP support
This commit is contained in:
Benjamin Bouvier
@@ -792,29 +792,111 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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ctx.emit(Inst::Ud2 { trap_info })
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}
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Opcode::F64const => {
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// TODO use xorpd for 0
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let value = ctx.get_constant(insn).unwrap();
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let dst = output_to_reg(ctx, outputs[0]);
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for inst in Inst::gen_constant(dst, value, F64, |reg_class, ty| {
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ctx.alloc_tmp(reg_class, ty)
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}) {
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ctx.emit(inst);
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}
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}
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Opcode::F32const => {
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// TODO use xorps for 0.
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let value = ctx.get_constant(insn).unwrap();
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let dst = output_to_reg(ctx, outputs[0]);
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for inst in Inst::gen_constant(dst, value, F32, |reg_class, ty| {
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ctx.alloc_tmp(reg_class, ty)
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}) {
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ctx.emit(inst);
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}
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}
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Opcode::Fadd | Opcode::Fsub | Opcode::Fmul | Opcode::Fdiv => {
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let lhs = input_to_reg(ctx, inputs[0]);
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let lhs = input_to_reg_mem(ctx, inputs[0]);
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let rhs = input_to_reg(ctx, inputs[1]);
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let dst = output_to_reg(ctx, outputs[0]);
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// Note: min and max can't be handled here, because of the way Cranelift defines them:
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// if any operand is a NaN, they must return the NaN operand, while the x86 machine
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// instruction will return the other operand.
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let (f32_op, f64_op) = match op {
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Opcode::Fadd => (SseOpcode::Addss, SseOpcode::Addsd),
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Opcode::Fsub => (SseOpcode::Subss, SseOpcode::Subsd),
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Opcode::Fmul => (SseOpcode::Mulss, SseOpcode::Mulsd),
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Opcode::Fdiv => (SseOpcode::Divss, SseOpcode::Divsd),
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_ => unreachable!(),
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};
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let is_64 = flt_ty_is_64(ty.unwrap());
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if !is_64 {
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let sse_op = match op {
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Opcode::Fadd => SseOpcode::Addss,
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Opcode::Fsub => SseOpcode::Subss,
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Opcode::Fmul => SseOpcode::Mulss,
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Opcode::Fdiv => SseOpcode::Divss,
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// TODO Fmax, Fmin.
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_ => unimplemented!(),
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};
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ctx.emit(Inst::xmm_mov_rm_r(
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SseOpcode::Movss,
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RegMem::reg(lhs),
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dst,
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None,
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));
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ctx.emit(Inst::xmm_rm_r(sse_op, RegMem::reg(rhs), dst));
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let mov_op = if is_64 {
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SseOpcode::Movsd
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} else {
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unimplemented!("unimplemented lowering for opcode {:?}", op);
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SseOpcode::Movss
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};
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ctx.emit(Inst::xmm_mov(mov_op, lhs, dst, None));
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let sse_op = if is_64 { f64_op } else { f32_op };
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ctx.emit(Inst::xmm_rm_r(sse_op, RegMem::reg(rhs), dst));
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}
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Opcode::Sqrt => {
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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let (f32_op, f64_op) = match op {
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Opcode::Sqrt => (SseOpcode::Sqrtss, SseOpcode::Sqrtsd),
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_ => unreachable!(),
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};
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let sse_op = if flt_ty_is_64(ty.unwrap()) {
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f64_op
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} else {
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f32_op
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};
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ctx.emit(Inst::xmm_unary_rm_r(sse_op, src, dst));
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}
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Opcode::Fpromote => {
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::xmm_unary_rm_r(SseOpcode::Cvtss2sd, src, dst));
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}
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Opcode::Fdemote => {
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::xmm_unary_rm_r(SseOpcode::Cvtsd2ss, src, dst));
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}
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Opcode::Bitcast => {
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let input_ty = ctx.input_ty(insn, 0);
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let output_ty = ctx.output_ty(insn, 0);
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match (input_ty, output_ty) {
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(F32, I32) => {
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let src = input_to_reg(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::xmm_to_gpr(SseOpcode::Movd, src, dst));
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}
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(I32, F32) => {
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::gpr_to_xmm(SseOpcode::Movd, src, dst));
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}
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(F64, I64) => {
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let src = input_to_reg(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::xmm_to_gpr(SseOpcode::Movq, src, dst));
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}
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(I64, F64) => {
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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ctx.emit(Inst::gpr_to_xmm(SseOpcode::Movq, src, dst));
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}
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_ => unreachable!("invalid bitcast from {:?} to {:?}", input_ty, output_ty),
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}
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}
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@@ -834,20 +916,19 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let tmp_xmm1 = ctx.alloc_tmp(RegClass::V128, F32);
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let tmp_xmm2 = ctx.alloc_tmp(RegClass::V128, F32);
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ctx.emit(Inst::imm_r(true, 0x8000_0000, tmp_gpr1));
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ctx.emit(Inst::xmm_mov_rm_r(
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ctx.emit(Inst::gpr_to_xmm(
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SseOpcode::Movd,
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RegMem::reg(tmp_gpr1.to_reg()),
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tmp_xmm1,
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None,
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));
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ctx.emit(Inst::xmm_mov_rm_r(
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ctx.emit(Inst::xmm_mov(
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SseOpcode::Movaps,
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RegMem::reg(tmp_xmm1.to_reg()),
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dst,
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None,
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));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Andnps, RegMem::reg(lhs), dst));
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ctx.emit(Inst::xmm_mov_rm_r(
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ctx.emit(Inst::xmm_mov(
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SseOpcode::Movss,
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RegMem::reg(rhs),
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tmp_xmm2,
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@@ -982,8 +1063,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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}
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(_, true) => {
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ctx.emit(match elem_ty {
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F32 => Inst::xmm_mov_rm_r(SseOpcode::Movss, RegMem::mem(addr), dst, srcloc),
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_ => unimplemented!("FP load not 32-bit"),
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F32 => Inst::xmm_mov(SseOpcode::Movss, RegMem::mem(addr), dst, srcloc),
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F64 => Inst::xmm_mov(SseOpcode::Movsd, RegMem::mem(addr), dst, srcloc),
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_ => unreachable!("unexpected type for load: {:?}", elem_ty),
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});
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}
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}
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@@ -1025,7 +1107,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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| Opcode::Istore32Complex => {
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assert!(
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inputs.len() == 3,
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"can't handle more than two inputs in complex load"
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"can't handle more than two inputs in complex store"
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);
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let base = input_to_reg(ctx, inputs[1]);
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let index = input_to_reg(ctx, inputs[2]);
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@@ -1043,7 +1125,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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if is_float {
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ctx.emit(match elem_ty {
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F32 => Inst::xmm_mov_r_m(SseOpcode::Movss, src, addr, srcloc),
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_ => unimplemented!("FP store not 32-bit"),
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F64 => Inst::xmm_mov_r_m(SseOpcode::Movsd, src, addr, srcloc),
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_ => panic!("unexpected type for store {:?}", elem_ty),
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});
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} else {
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ctx.emit(Inst::mov_r_m(elem_ty.bytes() as u8, src, addr, srcloc));
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@@ -1119,18 +1202,23 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let dst = output_to_reg(ctx, outputs[0]);
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let ty = ctx.output_ty(insn, 0);
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assert!(is_int_ty(ty), "float cmov NYI");
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let size = ty.bytes() as u8;
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if size == 1 {
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// Sign-extend operands to 32, then do a cmove of size 4.
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let lhs_se = ctx.alloc_tmp(RegClass::I64, I32);
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ctx.emit(Inst::movsx_rm_r(ExtMode::BL, lhs, lhs_se, None));
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ctx.emit(Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rhs), dst, None));
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ctx.emit(Inst::cmove(4, cc, RegMem::reg(lhs_se.to_reg()), dst));
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if ty.is_int() {
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let size = ty.bytes() as u8;
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if size == 1 {
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// Sign-extend operands to 32, then do a cmove of size 4.
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let lhs_se = ctx.alloc_tmp(RegClass::I64, I32);
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ctx.emit(Inst::movsx_rm_r(ExtMode::BL, lhs, lhs_se, None));
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ctx.emit(Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rhs), dst, None));
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ctx.emit(Inst::cmove(4, cc, RegMem::reg(lhs_se.to_reg()), dst));
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} else {
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ctx.emit(Inst::gen_move(dst, rhs, ty));
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ctx.emit(Inst::cmove(size, cc, lhs, dst));
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}
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} else {
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debug_assert!(ty == F32 || ty == F64);
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ctx.emit(Inst::gen_move(dst, rhs, ty));
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ctx.emit(Inst::cmove(size, cc, lhs, dst));
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ctx.emit(Inst::xmm_cmove(ty == F64, cc, lhs, dst));
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}
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}
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