Cranelift AArch64: Migrate Splat to ISLE (#4521)

Copyright (c) 2022, Arm Limited.

cranelift/codegen/src/isa/aarch64/lower/isle.rs

@@ -5,12 +5,13 @@ pub mod generated_code;
 
 // Types that the generated ISLE code uses via `use super::*`.
 use super::{
-    writable_zero_reg, zero_reg, AMode, ASIMDFPModImm, ASIMDMovModImm, BranchTarget, CallIndInfo,
-    CallInfo, Cond, CondBrKind, ExtendOp, FPUOpRI, FloatCC, Imm12, ImmLogic, ImmShift,
+    insn_inputs, writable_zero_reg, zero_reg, AMode, ASIMDFPModImm, ASIMDMovModImm, BranchTarget,
+    CallIndInfo, CallInfo, Cond, CondBrKind, ExtendOp, FPUOpRI, FloatCC, Imm12, ImmLogic, ImmShift,
     Inst as MInst, IntCC, JTSequenceInfo, MachLabel, MoveWideConst, MoveWideOp, NarrowValueMode,
     Opcode, OperandSize, PairAMode, Reg, ScalarSize, ShiftOpAndAmt, UImm5, VecMisc2, VectorSize,
     NZCV,
 };
+use crate::isa::aarch64::lower::{lower_address, lower_splat_const};
 use crate::isa::aarch64::settings::Flags as IsaFlags;
 use crate::machinst::{isle::*, InputSourceInst};
 use crate::settings::Flags;
@@ -442,4 +443,25 @@ where
             _ => panic!(),
         }
     }
+
+    fn amode(&mut self, ty: Type, mem_op: Inst, offset: u32) -> AMode {
+        lower_address(
+            self.lower_ctx,
+            ty,
+            &insn_inputs(self.lower_ctx, mem_op)[..],
+            offset as i32,
+        )
+    }
+
+    fn amode_is_reg(&mut self, address: &AMode) -> Option<Reg> {
+        address.is_reg()
+    }
+
+    fn splat_const(&mut self, value: u64, size: &VectorSize) -> Reg {
+        let rd = self.temp_writable_reg(I8X16);
+
+        lower_splat_const(self.lower_ctx, rd, value, *size);
+
+        rd.to_reg()
+    }
 }