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Merge pull request #2042 from cfallin/aarch64-fix-regshift-mask

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Aarch64: mask shift-amounts incorporated into reg-reg-shift ALU insts.
This commit is contained in:
Chris Fallin
2020-07-18 19:33:35 -07:00
committed by GitHub
parent b35cf7cf8e 9bd9c628aa
commit ea894c0eeb
3 changed files with 26 additions and 2 deletions
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5
cranelift/codegen/src/isa/aarch64/inst/args.rs
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@@ -52,6 +52,11 @@ impl ShiftOpShiftImm {
pub fn value(self) -> u8 {
self.0
}
/// Mask down to a given number of bits.
pub fn mask(self, bits: u8) -> ShiftOpShiftImm {
ShiftOpShiftImm(self.0 & (bits - 1))
}
}
/// A shift operator with an amount, guaranteed to be within range.

8
cranelift/codegen/src/isa/aarch64/lower.rs
View File

@@ -321,8 +321,12 @@ fn put_input_in_rs<C: LowerCtx<I = Inst>>(
// Can we get the shift amount as an immediate?
if let Some(shiftimm) = input_to_shiftimm(ctx, shift_amt) {
let reg = put_input_in_reg(ctx, shiftee, narrow_mode);
return ResultRS::RegShift(reg, ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm));
let shiftee_bits = ty_bits(ctx.input_ty(insn, 0));
if shiftee_bits <= u8::MAX as usize {
let shiftimm = shiftimm.mask(shiftee_bits as u8);
let reg = put_input_in_reg(ctx, shiftee, narrow_mode);
return ResultRS::RegShift(reg, ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm));
}
}
}
}