Port icmp to ISLE (AArch64) (#4898)

* Port `icmp` to ISLE (AArch64)

Ported the existing implementation of `icmp` (and, by extension, the
`lower_icmp` function) to ISLE for AArch64.

Copyright (c) 2022 Arm Limited

* Allow 'producer chains', eliminating `Nop0`s

Copyright (c) 2022 Arm Limited

cranelift/filetests/filetests/isa/aarch64/condbr.clif

@@ -45,10 +45,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, lo
+;   cset x7, lo
 ;   subs xzr, x1, x3
-;   cset x11, lt
-;   csel x0, x8, x11, eq
+;   cset x10, lt
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_ult_i128(i128, i128) -> b1 {
@@ -59,10 +59,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, lo
+;   cset x7, lo
 ;   subs xzr, x1, x3
-;   cset x11, lo
-;   csel x0, x8, x11, eq
+;   cset x10, lo
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_sle_i128(i128, i128) -> b1 {
@@ -73,10 +73,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, ls
+;   cset x7, ls
 ;   subs xzr, x1, x3
-;   cset x11, le
-;   csel x0, x8, x11, eq
+;   cset x10, le
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_ule_i128(i128, i128) -> b1 {
@@ -87,10 +87,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, ls
+;   cset x7, ls
 ;   subs xzr, x1, x3
-;   cset x11, ls
-;   csel x0, x8, x11, eq
+;   cset x10, ls
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_sgt_i128(i128, i128) -> b1 {
@@ -101,10 +101,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, hi
+;   cset x7, hi
 ;   subs xzr, x1, x3
-;   cset x11, gt
-;   csel x0, x8, x11, eq
+;   cset x10, gt
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_ugt_i128(i128, i128) -> b1 {
@@ -115,10 +115,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, hi
+;   cset x7, hi
 ;   subs xzr, x1, x3
-;   cset x11, hi
-;   csel x0, x8, x11, eq
+;   cset x10, hi
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_sge_i128(i128, i128) -> b1 {
@@ -129,10 +129,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, hs
+;   cset x7, hs
 ;   subs xzr, x1, x3
-;   cset x11, ge
-;   csel x0, x8, x11, eq
+;   cset x10, ge
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %icmp_uge_i128(i128, i128) -> b1 {
@@ -143,10 +143,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x8, hs
+;   cset x7, hs
 ;   subs xzr, x1, x3
-;   cset x11, hs
-;   csel x0, x8, x11, eq
+;   cset x10, hs
+;   csel x0, x7, x10, eq
 ;   ret
 
 function %f(i64, i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif

@@ -15,11 +15,11 @@ block0:
 }
 
 ; block0:
-;   movz x3, #56780
-;   uxth w5, w3
-;   movz x7, #56780
-;   subs wzr, w5, w7, UXTH
-;   cset x4, ne
-;   and w0, w4, #1
+;   movz x2, #56780
+;   uxth w4, w2
+;   movz x6, #56780
+;   subs wzr, w4, w6, UXTH
+;   cset x9, ne
+;   and w0, w9, #1
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif

@@ -9,8 +9,8 @@ block0(v0: i32x4, v1: i32x4):
 }
 
 ; block0:
-;   cmeq v0.4s, v0.4s, v1.4s
-;   mvn v0.16b, v0.16b
+;   cmeq v4.4s, v0.4s, v1.4s
+;   mvn v0.16b, v4.16b
 ;   ret
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> b32x4 {