aarch64: Translate rot{r,l} to ISLE (#3614)
This commit translates the `rotl` and `rotr` lowerings already existing to ISLE. The port was relatively straightforward with the biggest changing being the instructions generated around i128 rotl/rotr primarily due to register changes.
This commit is contained in:
Alex Crichton
@@ -894,3 +894,145 @@
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(tst64_imm amt (u64_into_imm_logic $I64 64))
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(csel (Cond.Ne) hi_rshift maybe_lo)
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(csel (Cond.Ne) hi_sign hi_rshift))))
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;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; General 8/16-bit case.
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(rule (lower (has_type (fits_in_16 ty) (rotl x y)))
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(let ((neg_shift Reg (alu_rrr (ALUOp.Sub32) (zero_reg) (put_in_reg y))))
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(value_reg (small_rotr ty (put_in_reg_zext32 x) neg_shift))))
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;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
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(rule (lower (has_type (fits_in_16 ty) (rotl x (def_inst (iconst (imm_shift_from_imm64 <ty n))))))
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(value_reg (small_rotr_imm ty (put_in_reg_zext32 x) (negate_imm_shift ty n))))
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;; aarch64 doesn't have a left-rotate instruction, but a left rotation of K
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;; places is effectively a right rotation of N - K places, if N is the integer's
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;; bit size. We implement left rotations with this trick.
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;;
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;; Note that when negating the shift amount here the upper bits are ignored
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;; by the rotr instruction, meaning that we'll still left-shift by the desired
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;; amount.
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;; General 32-bit case.
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(rule (lower (has_type $I32 (rotl x y)))
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(let ((neg_shift Reg (alu_rrr (ALUOp.Sub32) (zero_reg) (put_in_reg y))))
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(value_reg (alu_rrr (ALUOp.RotR32) (put_in_reg x) neg_shift))))
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;; General 64-bit case.
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(rule (lower (has_type $I64 (rotl x y)))
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(let ((neg_shift Reg (alu_rrr (ALUOp.Sub64) (zero_reg) (put_in_reg y))))
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(value_reg (alu_rrr (ALUOp.RotR64) (put_in_reg x) neg_shift))))
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;; Specialization for the 32-bit case when the rotation amount is an immediate.
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(rule (lower (has_type $I32 (rotl x (def_inst (iconst (imm_shift_from_imm64 <$I32 n))))))
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(value_reg (alu_rr_imm_shift (ALUOp.RotR32) (put_in_reg x) (negate_imm_shift $I32 n))))
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;; Specialization for the 64-bit case when the rotation amount is an immediate.
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(rule (lower (has_type $I64 (rotl x (def_inst (iconst (imm_shift_from_imm64 <$I64 n))))))
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(value_reg (alu_rr_imm_shift (ALUOp.RotR64) (put_in_reg x) (negate_imm_shift $I64 n))))
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(decl negate_imm_shift (Type ImmShift) ImmShift)
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(extern constructor negate_imm_shift negate_imm_shift)
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;; General 128-bit case.
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;;
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;; TODO: much better codegen is possible with a constant amount.
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(rule (lower (has_type $I128 (rotl x y)))
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(let (
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(val ValueRegs (put_in_regs x))
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(amt Reg (value_regs_get (put_in_regs y) 0))
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(neg_amt Reg (alu_rrr (ALUOp.Sub64) (imm $I64 128) amt))
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(lshift ValueRegs (lower_shl128 val amt))
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(rshift ValueRegs (lower_ushr128 val neg_amt))
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)
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(value_regs
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(alu_rrr (ALUOp.Orr64) (value_regs_get lshift 0) (value_regs_get rshift 0))
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(alu_rrr (ALUOp.Orr64) (value_regs_get lshift 1) (value_regs_get rshift 1)))))
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;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; General 8/16-bit case.
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(rule (lower (has_type (fits_in_16 ty) (rotr x y)))
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(value_reg (small_rotr ty (put_in_reg_zext32 x) (put_in_reg y))))
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;; General 32-bit case.
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(rule (lower (has_type $I32 (rotr x y)))
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(value_reg (alu_rrr (ALUOp.RotR32) (put_in_reg x) (put_in_reg y))))
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;; General 64-bit case.
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(rule (lower (has_type $I64 (rotr x y)))
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(value_reg (alu_rrr (ALUOp.RotR64) (put_in_reg x) (put_in_reg y))))
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;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
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(rule (lower (has_type (fits_in_16 ty) (rotr x (def_inst (iconst (imm_shift_from_imm64 <ty n))))))
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(value_reg (small_rotr_imm ty (put_in_reg_zext32 x) n)))
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;; Specialization for the 32-bit case when the rotation amount is an immediate.
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(rule (lower (has_type $I32 (rotr x (def_inst (iconst (imm_shift_from_imm64 <$I32 n))))))
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(value_reg (alu_rr_imm_shift (ALUOp.RotR32) (put_in_reg x) n)))
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;; Specialization for the 64-bit case when the rotation amount is an immediate.
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(rule (lower (has_type $I64 (rotr x (def_inst (iconst (imm_shift_from_imm64 <$I64 n))))))
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(value_reg (alu_rr_imm_shift (ALUOp.RotR64) (put_in_reg x) n)))
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;; For a < 32-bit rotate-right, we synthesize this as:
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;;
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;; rotr rd, val, amt
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;;
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;; =>
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;;
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;; and masked_amt, amt, <bitwidth - 1>
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;; sub tmp_sub, masked_amt, <bitwidth>
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;; sub neg_amt, zero, tmp_sub ; neg
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;; lsr val_rshift, val, masked_amt
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;; lsl val_lshift, val, neg_amt
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;; orr rd, val_lshift val_rshift
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(decl small_rotr (Type Reg Reg) Reg)
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(rule (small_rotr ty val amt)
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(let (
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(masked_amt Reg (alu_rr_imm_logic (ALUOp.And32) amt (rotr_mask ty)))
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(tmp_sub Reg (alu_rr_imm12 (ALUOp.Sub32) masked_amt (u8_into_imm12 (ty_bits ty))))
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(neg_amt Reg (alu_rrr (ALUOp.Sub32) (zero_reg) tmp_sub))
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(val_rshift Reg (alu_rrr (ALUOp.Lsr32) val masked_amt))
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(val_lshift Reg (alu_rrr (ALUOp.Lsl32) val neg_amt))
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)
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(alu_rrr (ALUOp.Orr32) val_lshift val_rshift)))
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(decl rotr_mask (Type) ImmLogic)
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(extern constructor rotr_mask rotr_mask)
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;; For a constant amount, we can instead do:
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;;
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;; rotr rd, val, #amt
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;;
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;; =>
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;;
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;; lsr val_rshift, val, #<amt>
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;; lsl val_lshift, val, <bitwidth - amt>
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;; orr rd, val_lshift, val_rshift
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(decl small_rotr_imm (Type Reg ImmShift) Reg)
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(rule (small_rotr_imm ty val amt)
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(let (
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(val_rshift Reg (alu_rr_imm_shift (ALUOp.Lsr32) val amt))
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(val_lshift Reg (alu_rr_imm_shift (ALUOp.Lsl32) val (rotr_opposite_amount ty amt)))
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)
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(alu_rrr (ALUOp.Orr32) val_lshift val_rshift)))
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(decl rotr_opposite_amount (Type ImmShift) ImmShift)
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(extern constructor rotr_opposite_amount rotr_opposite_amount)
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;; General 128-bit case.
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;;
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;; TODO: much better codegen is possible with a constant amount.
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(rule (lower (has_type $I128 (rotr x y)))
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(let (
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(val ValueRegs (put_in_regs x))
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(amt Reg (value_regs_get (put_in_regs y) 0))
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(neg_amt Reg (alu_rrr (ALUOp.Sub64) (imm $I64 128) amt))
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(rshift ValueRegs (lower_ushr128 val amt))
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(lshift ValueRegs (lower_shl128 val neg_amt))
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(hi Reg (alu_rrr (ALUOp.Orr64) (value_regs_get rshift 1) (value_regs_get lshift 1)))
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(lo Reg (alu_rrr (ALUOp.Orr64) (value_regs_get rshift 0) (value_regs_get lshift 0)))
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)
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(value_regs lo hi)))
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