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AArch64: Introduce an enum for ternary integer operations

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This commit performs a small cleanup in the AArch64 backend - after
the MAdd and MSub variants have been extracted, the ALUOp enum is
used purely for binary integer operations.

Also, Inst::Mov has been renamed to Inst::Mov64 for consistency.

Copyright (c) 2020, Arm Limited.
This commit is contained in:
Anton Kirilov
2020-09-07 12:22:56 +01:00
parent a64af55cda
commit e92f949663
4 changed files with 47 additions and 66 deletions
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16
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -789,7 +789,7 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRR {
alu_op: ALUOp::MAdd32,
alu_op: ALUOp3::MAdd32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -800,7 +800,7 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp::MAdd64,
alu_op: ALUOp3::MAdd64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -811,7 +811,7 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp::MSub32,
alu_op: ALUOp3::MSub32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -822,7 +822,7 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp::MSub64,
alu_op: ALUOp3::MSub64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -832,23 +832,21 @@ fn test_aarch64_binemit() {
"msub x1, x2, x3, x4",
));
insns.push((
Inst::AluRRRR {
Inst::AluRRR {
alu_op: ALUOp::SMulH,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
ra: zero_reg(),
},
"417C439B",
"smulh x1, x2, x3",
));
insns.push((
Inst::AluRRRR {
Inst::AluRRR {
alu_op: ALUOp::UMulH,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
ra: zero_reg(),
},
"417CC39B",
"umulh x1, x2, x3",
@@ -1654,7 +1652,7 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::Mov {
Inst::Mov64 {
rd: writable_xreg(8),
rm: xreg(9),
},