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Remove IFLAGS/FFLAGS types (#5406)

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All instructions using the CPU flags types (IFLAGS/FFLAGS) were already
removed.  This patch completes the cleanup by removing all remaining
instructions that define values of CPU flags types, as well as the
types themselves.

Specifically, the following features are removed:
- The IFLAGS and FFLAGS types and the SpecialType category.
- Special handling of IFLAGS and FFLAGS in machinst/isle.rs and
  machinst/lower.rs.
- The ifcmp, ifcmp_imm, ffcmp, iadd_ifcin, iadd_ifcout, iadd_ifcarry,
  isub_ifbin, isub_ifbout, and isub_ifborrow instructions.
- The writes_cpu_flags instruction property.
- The flags verifier pass.
- Flags handling in the interpreter.

All of these features are currently unused; no functional change
intended by this patch.

This addresses https://github.com/bytecodealliance/wasmtime/issues/3249.
This commit is contained in:
Ulrich Weigand
2022-12-09 22:42:03 +01:00
committed by GitHub
parent 6e0a029c35
commit e913cf3647
42 changed files with 55 additions and 1119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -2318,7 +2318,6 @@ impl MachInst for Inst {
assert!(ty.bits() <= 128);
Ok((&[RegClass::Float], &[types::I8X16]))
}
types::IFLAGS | types::FFLAGS => Ok((&[RegClass::Int], &[types::I64])),
_ => Err(CodegenError::Unsupported(format!(
"Unexpected SSA-value type: {}",
ty

46
cranelift/codegen/src/isa/x64/lower.isle
View File

@@ -135,49 +135,6 @@
(uadd_sat x y)))
(x64_paddusw x y))
;;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; N.B.: the second output of `iadd_ifcout` is meant to be the
;; `iflags` value containing the carry result. However, we plan to
;; replace this with a bool carry flag, and all consumers of `iflags`
;; remain in the handwritten pattern-matching code and explicitly
;; match on the flags producer. So we can get away with just
;; using an invalid second output, and the reg-renaming code does the
;; right thing, for now. For safety, we assert elsewhere that no one
;; actually uses the register assigned to the SSA `iflags`-typed
;; `Value`.
(decl output_ifcout (Reg) InstOutput)
(rule (output_ifcout reg)
(output_pair reg (value_regs_invalid)))
;; Add two registers.
(rule 0 (lower (has_type (fits_in_64 ty)
(iadd_ifcout x y)))
(output_ifcout (x64_add ty x y)))
;; Add a register and an immediate.
(rule 1 (lower (has_type (fits_in_64 ty)
(iadd_ifcout x (simm32_from_value y))))
(output_ifcout (x64_add ty x y)))
(rule 2 (lower (has_type (fits_in_64 ty)
(iadd_ifcout (simm32_from_value x) y)))
(output_ifcout (x64_add ty y x)))
;; Add a register and memory.
(rule 3 (lower (has_type (fits_in_64 ty)
(iadd_ifcout x (sinkable_load y))))
(output_ifcout (x64_add ty x (sink_load_to_gpr_mem_imm y))))
(rule 4 (lower (has_type (fits_in_64 ty)
(iadd_ifcout (sinkable_load x) y)))
(output_ifcout (x64_add ty y (sink_load_to_gpr_mem_imm x))))
;; (No `iadd_ifcout` for `i128`.)
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller.
@@ -2180,9 +2137,6 @@
(rule (lower (has_type $I64
(uextend src @ (has_type $I32 (iadd _ _)))))
src)
(rule (lower (has_type $I64
(uextend src @ (has_type $I32 (iadd_ifcout _ _)))))
src)
(rule (lower (has_type $I64
(uextend src @ (has_type $I32 (isub _ _)))))
src)

18
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -332,7 +332,6 @@ fn lower_insn_to_regs(
| Opcode::Null
| Opcode::Iadd
| Opcode::IaddCout
| Opcode::IaddIfcout
| Opcode::SaddSat
| Opcode::UaddSat
| Opcode::Isub
@@ -360,6 +359,7 @@ fn lower_insn_to_regs(
| Opcode::Ineg
| Opcode::Trap
| Opcode::ResumableTrap
| Opcode::UaddOverflowTrap
| Opcode::Clz
| Opcode::Ctz
| Opcode::Popcnt
@@ -500,13 +500,6 @@ fn lower_insn_to_regs(
unimplemented!("Vector split/concat ops not implemented.");
}
// Opcodes that should be removed by legalization. These should
// eventually be removed if/when we replace in-situ legalization with
// something better.
Opcode::Ifcmp | Opcode::Ffcmp => {
panic!("Should never reach ifcmp/ffcmp as isel root!");
}
Opcode::IaddImm
| Opcode::ImulImm
| Opcode::UdivImm
@@ -515,16 +508,10 @@ fn lower_insn_to_regs(
| Opcode::SremImm
| Opcode::IrsubImm
| Opcode::IaddCin
| Opcode::IaddIfcin
| Opcode::IaddCarry
| Opcode::IaddIfcarry
| Opcode::IsubBin
| Opcode::IsubIfbin
| Opcode::IsubBout
| Opcode::IsubIfbout
| Opcode::IsubBorrow
| Opcode::IsubIfborrow
| Opcode::UaddOverflowTrap
| Opcode::BandImm
| Opcode::BorImm
| Opcode::BxorImm
@@ -533,8 +520,7 @@ fn lower_insn_to_regs(
| Opcode::IshlImm
| Opcode::UshrImm
| Opcode::SshrImm
| Opcode::IcmpImm
| Opcode::IfcmpImm => {
| Opcode::IcmpImm => {
panic!("ALU+imm and ALU+carry ops should not appear here!");
}