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Remove IFLAGS/FFLAGS types (#5406)

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All instructions using the CPU flags types (IFLAGS/FFLAGS) were already
removed.  This patch completes the cleanup by removing all remaining
instructions that define values of CPU flags types, as well as the
types themselves.

Specifically, the following features are removed:
- The IFLAGS and FFLAGS types and the SpecialType category.
- Special handling of IFLAGS and FFLAGS in machinst/isle.rs and
  machinst/lower.rs.
- The ifcmp, ifcmp_imm, ffcmp, iadd_ifcin, iadd_ifcout, iadd_ifcarry,
  isub_ifbin, isub_ifbout, and isub_ifborrow instructions.
- The writes_cpu_flags instruction property.
- The flags verifier pass.
- Flags handling in the interpreter.

All of these features are currently unused; no functional change
intended by this patch.

This addresses https://github.com/bytecodealliance/wasmtime/issues/3249.
This commit is contained in:
Ulrich Weigand
2022-12-09 22:42:03 +01:00
committed by GitHub
parent 6e0a029c35
commit e913cf3647
42 changed files with 55 additions and 1119 deletions
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3
cranelift/codegen/src/isa/s390x/inst/mod.rs
View File

@@ -1244,9 +1244,6 @@ impl MachInst for Inst {
types::F64 => Ok((&[RegClass::Float], &[types::F64])),
types::I128 => Ok((&[RegClass::Float], &[types::I128])),
_ if ty.is_vector() && ty.bits() == 128 => Ok((&[RegClass::Float], &[types::I8X16])),
// FIXME: We don't really have IFLAGS, but need to allow it here
// for now to support the SelectifSpectreGuard instruction.
types::IFLAGS => Ok((&[RegClass::Int], &[types::I64])),
_ => Err(CodegenError::Unsupported(format!(
"Unexpected SSA-value type: {}",
ty

53
cranelift/codegen/src/isa/s390x/lower.isle
View File

@@ -192,47 +192,6 @@
(vec_unpacks_low ty y))))
;;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; N.B.: the second output of `iadd_ifcout` is meant to be the `iflags` value
;; containing the carry result, but we do not support the `iflags` mechanism.
;; However, the only actual use case is where `iadd_ifcout` feeds into `trapif`,
;; which is implemented by explicitly matching on the flags producer. So we can
;; get away with just using an invalid second output, and the reg-renaming code
;; does the right thing, for now.
(decl output_ifcout (Reg) InstOutput)
(rule (output_ifcout reg)
(output_pair reg (value_regs_invalid)))
;; Add two registers.
(rule 0 (lower (has_type (fits_in_64 ty) (iadd_ifcout x y)))
(output_ifcout (add_logical_reg ty x y)))
;; Add a register and a zero-extended register.
(rule 4 (lower (has_type (fits_in_64 ty) (iadd_ifcout x (zext32_value y))))
(output_ifcout (add_logical_reg_zext32 ty x y)))
(rule 8 (lower (has_type (fits_in_64 ty) (iadd_ifcout (zext32_value x) y)))
(output_ifcout (add_logical_reg_zext32 ty y x)))
;; Add a register and an immediate.
(rule 3 (lower (has_type (fits_in_64 ty) (iadd_ifcout x (u32_from_value y))))
(output_ifcout (add_logical_zimm32 ty x y)))
(rule 7 (lower (has_type (fits_in_64 ty) (iadd_ifcout (u32_from_value x) y)))
(output_ifcout (add_logical_zimm32 ty y x)))
;; Add a register and memory (32/64-bit types).
(rule 2 (lower (has_type (fits_in_64 ty) (iadd_ifcout x (sinkable_load_32_64 y))))
(output_ifcout (add_logical_mem ty x (sink_load y))))
(rule 6 (lower (has_type (fits_in_64 ty) (iadd_ifcout (sinkable_load_32_64 x) y)))
(output_ifcout (add_logical_mem ty y (sink_load x))))
;; Add a register and zero-extended memory.
(rule 1 (lower (has_type (fits_in_64 ty) (iadd_ifcout x (sinkable_uload32 y))))
(output_ifcout (add_logical_mem_zext32 ty x (sink_uload32 y))))
(rule 5 (lower (has_type (fits_in_64 ty) (iadd_ifcout (sinkable_uload32 x) y)))
(output_ifcout (add_logical_mem_zext32 ty y (sink_uload32 x))))
;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Absolute value of a register.
@@ -3742,14 +3701,12 @@
;;;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; We do not support the `iflags` mechanism on our platform. However, common
;; code will unconditionally emit certain patterns using `iflags` which we
;; need to handle somehow. Note that only those specific patterns are
;; recognized by the code below, other uses will fail to lower.
;; We need to guarantee a conditional move instruction. But on this platform
;; this is already the best way to implement select in general, so the
;; implementation of `select_spectre_guard` is identical to `select`.
(rule (lower (has_type ty (select_spectre_guard
(icmp int_cc x y) val_true val_false)))
(select_bool_reg ty (icmp_val $false int_cc x y)
val_cond val_true val_false)))
(select_bool_reg ty (value_nonzero val_cond)
(put_in_reg val_true) (put_in_reg val_false)))

14
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -51,7 +51,6 @@ impl LowerBackend for S390xBackend {
| Opcode::Isplit
| Opcode::Iconcat
| Opcode::Iadd
| Opcode::IaddIfcout
| Opcode::Isub
| Opcode::UaddSat
| Opcode::SaddSat
@@ -177,6 +176,7 @@ impl LowerBackend for S390xBackend {
| Opcode::Trapnz
| Opcode::ResumableTrapnz
| Opcode::Debugtrap
| Opcode::UaddOverflowTrap
| Opcode::Call
| Opcode::CallIndirect
| Opcode::Return
@@ -221,9 +221,6 @@ impl LowerBackend for S390xBackend {
Opcode::GlobalValue => {
panic!("global_value should have been removed by legalization!");
}
Opcode::Ifcmp | Opcode::Ffcmp => {
panic!("Flags opcode should not be encountered.");
}
Opcode::Jump | Opcode::Brz | Opcode::Brnz | Opcode::BrTable => {
panic!("Branch opcode reached non-branch lowering logic!");
}
@@ -235,17 +232,11 @@ impl LowerBackend for S390xBackend {
| Opcode::SremImm
| Opcode::IrsubImm
| Opcode::IaddCin
| Opcode::IaddIfcin
| Opcode::IaddCout
| Opcode::IaddCarry
| Opcode::IaddIfcarry
| Opcode::UaddOverflowTrap
| Opcode::IsubBin
| Opcode::IsubIfbin
| Opcode::IsubBout
| Opcode::IsubIfbout
| Opcode::IsubBorrow
| Opcode::IsubIfborrow
| Opcode::BandImm
| Opcode::BorImm
| Opcode::BxorImm
@@ -254,8 +245,7 @@ impl LowerBackend for S390xBackend {
| Opcode::IshlImm
| Opcode::UshrImm
| Opcode::SshrImm
| Opcode::IcmpImm
| Opcode::IfcmpImm => {
| Opcode::IcmpImm => {
panic!("ALU+imm and ALU+carry ops should not appear here!");
}
}