Remove IFLAGS/FFLAGS types (#5406)

All instructions using the CPU flags types (IFLAGS/FFLAGS) were already
removed.  This patch completes the cleanup by removing all remaining
instructions that define values of CPU flags types, as well as the
types themselves.

Specifically, the following features are removed:
- The IFLAGS and FFLAGS types and the SpecialType category.
- Special handling of IFLAGS and FFLAGS in machinst/isle.rs and
  machinst/lower.rs.
- The ifcmp, ifcmp_imm, ffcmp, iadd_ifcin, iadd_ifcout, iadd_ifcarry,
  isub_ifbin, isub_ifbout, and isub_ifborrow instructions.
- The writes_cpu_flags instruction property.
- The flags verifier pass.
- Flags handling in the interpreter.

All of these features are currently unused; no functional change
intended by this patch.

This addresses https://github.com/bytecodealliance/wasmtime/issues/3249.

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -2037,10 +2037,6 @@
       (a2 Reg (alu_rr_imm12 (AluOPRRI.Addi) a (imm12_const 1))))
     (gen_select_reg (IntCC.SignedLessThan) r (zero_reg) a2 r)))
 
-(decl output_ifcout (Reg) InstOutput)
-(rule (output_ifcout reg)
-      (output_pair reg (value_regs_invalid)))
-
 (decl gen_trapff (FloatCC Reg Reg Type TrapCode) InstOutput)
 (rule
   (gen_trapff cc a b ty trap_code)

cranelift/codegen/src/isa/riscv64/inst/mod.rs

@@ -6,7 +6,7 @@
 
 use crate::binemit::{Addend, CodeOffset, Reloc};
 pub use crate::ir::condcodes::IntCC;
-use crate::ir::types::{F32, F64, FFLAGS, I128, I16, I32, I64, I8, IFLAGS, R32, R64};
+use crate::ir::types::{F32, F64, I128, I16, I32, I64, I8, R32, R64};
 
 pub use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, Type, ValueLabel};
 use crate::isa::CallConv;
@@ -778,8 +778,6 @@ impl MachInst for Inst {
             F32 => Ok((&[RegClass::Float], &[F32])),
             F64 => Ok((&[RegClass::Float], &[F64])),
             I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
-            IFLAGS => Ok((&[RegClass::Int], &[IFLAGS])),
-            FFLAGS => Ok((&[RegClass::Int], &[FFLAGS])),
             _ => Err(CodegenError::Unsupported(format!(
                 "Unexpected SSA-value type: {}",
                 ty

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -43,11 +43,6 @@
       (high Reg (alu_add high_tmp carry)))
     (value_regs low high)))
 
-;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;
-(rule
-  (lower (has_type (fits_in_64 ty) (iadd_ifcout x y)))
-  (output_ifcout (alu_add x y)))
-
 ;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;
 (rule
   (lower (has_type (fits_in_64 ty) (uadd_overflow_trap x y tc)))
@@ -747,14 +742,6 @@
 (rule
   (lower (icmp cc x @ (value_type ty) y))
   (lower_icmp cc x y ty))
-;; special for `iadd_ifcout` first out.
-(rule 2
-  (lower (icmp cc (iadd_ifcout a @ (value_type ty) b) y))
-  (lower_icmp cc (alu_add a b) y ty))
-
-(rule 1
-  (lower (icmp cc x (iadd_ifcout a @ (value_type ty) b)))
-  (lower_icmp cc x (alu_add a b) ty))
 
 (decl gen_fcmp (FloatCC Value Value Type) Reg)
 (rule