Remove IFLAGS/FFLAGS types (#5406)
All instructions using the CPU flags types (IFLAGS/FFLAGS) were already removed. This patch completes the cleanup by removing all remaining instructions that define values of CPU flags types, as well as the types themselves. Specifically, the following features are removed: - The IFLAGS and FFLAGS types and the SpecialType category. - Special handling of IFLAGS and FFLAGS in machinst/isle.rs and machinst/lower.rs. - The ifcmp, ifcmp_imm, ffcmp, iadd_ifcin, iadd_ifcout, iadd_ifcarry, isub_ifbin, isub_ifbout, and isub_ifborrow instructions. - The writes_cpu_flags instruction property. - The flags verifier pass. - Flags handling in the interpreter. All of these features are currently unused; no functional change intended by this patch. This addresses https://github.com/bytecodealliance/wasmtime/issues/3249.
This commit is contained in:
Ulrich Weigand
@@ -1940,14 +1940,6 @@
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(MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2)
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dst)))
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;; Helper for emitting `adds` instructions, setting flags in ambient
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;; state. Used only for `iadd_ifcout`.
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(decl add_with_flags (Type Reg Reg) Reg)
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(rule (add_with_flags ty src1 src2)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2))))
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dst))
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;; Helper for emitting `adc` instructions.
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(decl adc_paired (Type Reg Reg) ConsumesFlags)
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(rule (adc_paired ty src1 src2)
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@@ -1,7 +1,7 @@
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//! This module defines aarch64-specific machine instruction types.
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use crate::binemit::{Addend, CodeOffset, Reloc};
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use crate::ir::types::{F32, F64, FFLAGS, I128, I16, I32, I64, I8, I8X16, IFLAGS, R32, R64};
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use crate::ir::types::{F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
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use crate::ir::{types, ExternalName, MemFlags, Opcode, Type};
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use crate::isa::CallConv;
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use crate::machinst::*;
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@@ -1280,7 +1280,6 @@ impl MachInst for Inst {
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Ok((&[RegClass::Float], &[I8X16]))
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}
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_ if ty.is_dynamic_vector() => Ok((&[RegClass::Float], &[I8X16])),
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IFLAGS | FFLAGS => Ok((&[RegClass::Int], &[I64])),
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_ => Err(CodegenError::Unsupported(format!(
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"Unexpected SSA-value type: {}",
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ty
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@@ -2332,36 +2332,6 @@
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(lower_msb Reg (lsr_imm $I64 lower_msb (imm_shift_from_u8 63))))
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(add_shift $I64 lower_msb upper_msb (lshl_from_u64 $I64 1))))
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;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; This is a two-output instruction that is needed for the
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;; legalizer's explicit heap-check sequence, among possible other
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;; uses. Its second output is a flags output only ever meant to
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;; check for overflow using the
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;; `backend.unsigned_add_overflow_condition()` condition.
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;;
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;; Note that the CLIF validation will ensure that no flag-setting
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;; operation comes between this IaddIfcout and its use (e.g., a
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;; Trapif). Thus, we can rely on implicit communication through the
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;; processor flags rather than explicitly generating flags into a
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;; register. We simply use the variant of the add instruction that
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;; sets flags (`adds`) here.
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;;
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;; Note that the second output (the flags) need not be generated,
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;; because flags are never materialized into a register; the only
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;; instructions that can use a value of type `iflags` or `fflags`
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;; will look directly for the flags-producing instruction (which can
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;; always be found, by construction) and merge it.
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;;
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;; Now handle the iadd as above, except use an AddS opcode that sets
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;; flags.
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(rule (lower (has_type (ty_int ty)
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(iadd_ifcout a b)))
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(output_pair
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(add_with_flags ty a b)
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(invalid_reg)))
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;;; Rules for `iadd_cout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; For values smaller than a register, we do a normal `add` with both arguments
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@@ -167,14 +167,6 @@ pub(crate) fn lower_insn_to_regs(
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Opcode::Return => implemented_in_isle(ctx),
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Opcode::Ifcmp | Opcode::Ffcmp => {
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// An Ifcmp/Ffcmp must always be seen as a use of a brif/brff or trueif/trueff
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// instruction. This will always be the case as long as the IR uses an Ifcmp/Ffcmp from
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// the same block, or a dominating block. In other words, it cannot pass through a BB
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// param (phi). The flags pass of the verifier will ensure this.
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panic!("Should never reach ifcmp as isel root!");
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}
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Opcode::Icmp => implemented_in_isle(ctx),
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Opcode::Fcmp => implemented_in_isle(ctx),
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@@ -253,8 +245,6 @@ pub(crate) fn lower_insn_to_regs(
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Opcode::FcvtToUintSat | Opcode::FcvtToSintSat => implemented_in_isle(ctx),
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Opcode::IaddIfcout => implemented_in_isle(ctx),
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Opcode::UaddOverflowTrap => implemented_in_isle(ctx),
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Opcode::IaddCout => implemented_in_isle(ctx),
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@@ -267,15 +257,10 @@ pub(crate) fn lower_insn_to_regs(
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| Opcode::SremImm
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| Opcode::IrsubImm
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| Opcode::IaddCin
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| Opcode::IaddIfcin
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| Opcode::IaddCarry
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| Opcode::IaddIfcarry
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| Opcode::IsubBin
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| Opcode::IsubIfbin
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| Opcode::IsubBout
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| Opcode::IsubIfbout
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| Opcode::IsubBorrow
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| Opcode::IsubIfborrow
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| Opcode::BandImm
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| Opcode::BorImm
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| Opcode::BxorImm
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@@ -284,8 +269,7 @@ pub(crate) fn lower_insn_to_regs(
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| Opcode::IshlImm
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| Opcode::UshrImm
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| Opcode::SshrImm
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| Opcode::IcmpImm
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| Opcode::IfcmpImm => {
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| Opcode::IcmpImm => {
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panic!("ALU+imm and ALU+carry ops should not appear here!");
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}
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