x64 new backend: port ABI implementation to shared infrastructure with AArch64.

Previously, in #2128, we factored out a common "vanilla 64-bit ABI"
implementation from the AArch64 ABI code, with the idea that this should
be largely compatible with x64. This PR alters the new x64 backend to
make use of the shared infrastructure, removing the duplication that
existed previously. The generated code is nearly (not exactly) the same;
the only difference relates to how the clobber-save region is padded in
the prologue.

This also changes some register allocations in the aarch64 code because
call support in the shared ABI infra now passes a temp vreg in, rather
than requiring use of a fixed, non-allocable temp; tests have been
updated, and the runtime behavior is unchanged.

cranelift/filetests/filetests/vcode/aarch64/call.clif

@@ -11,8 +11,8 @@ block0(v0: i64):
 
 ; check:  stp fp, lr, [sp, #-16]!
 ; nextln:  mov fp, sp
-; nextln:  ldr x16, 8 ; b 12 ; data
-; nextln:  blr x16
+; nextln:  ldr x1, 8 ; b 12 ; data
+; nextln:  blr x1
 ; nextln:  mov sp, fp
 ; nextln:  ldp fp, lr, [sp], #16
 ; nextln:  ret
@@ -28,8 +28,8 @@ block0(v0: i32):
 ; check:  stp fp, lr, [sp, #-16]!
 ; nextln:  mov fp, sp
 ; nextln:  mov w0, w0
-; nextln:  ldr x16, 8 ; b 12 ; data
-; nextln:  blr x16
+; nextln:  ldr x1, 8 ; b 12 ; data
+; nextln:  blr x1
 ; nextln:  mov sp, fp
 ; nextln:  ldp fp, lr, [sp], #16
 ; nextln:  ret
@@ -57,8 +57,8 @@ block0(v0: i32):
 ; check:  stp fp, lr, [sp, #-16]!
 ; nextln:  mov fp, sp
 ; nextln:  sxtw x0, w0
-; nextln:  ldr x16, 8 ; b 12 ; data
-; nextln:  blr x16
+; nextln:  ldr x1, 8 ; b 12 ; data
+; nextln:  blr x1
 ; nextln:  mov sp, fp
 ; nextln:  ldp fp, lr, [sp], #16
 ; nextln:  ret
@@ -99,8 +99,8 @@ block0(v0: i8):
 ; nextln:  movz x7, #42
 ; nextln:  sxtb x8, w8
 ; nextln:  stur x8, [sp]
-; nextln:  ldr x16, 8 ; b 12 ; data
-; nextln:  blr x16
+; nextln:  ldr x8, 8 ; b 12 ; data
+; nextln:  blr x8
 ; nextln:  add sp, sp, #16
 ; nextln:  virtual_sp_offset_adjust -16
 ; nextln:  mov sp, fp

cranelift/filetests/filetests/vcode/aarch64/reftypes.clif

@@ -83,12 +83,12 @@ block3(v7: r64, v8: r64):
 ; nextln: mov x19, x0
 ; nextln: mov x20, x1
 ; nextln: mov x0, x19
-; nextln: ldr x16, 8 ; b 12 ; data
+; nextln: ldr x1, 8 ; b 12 ; data
 ; nextln: stur x0, [sp, #24]
 ; nextln: stur x19, [sp, #32]
 ; nextln: stur x20, [sp, #40]
 ; nextln: (safepoint: slots [S0, S1, S2]
-; nextln: blr x16
+; nextln: blr x1
 ; nextln: ldur x19, [sp, #32]
 ; nextln: ldur x20, [sp, #40]
 ; nextln: add x1, sp, #16

cranelift/filetests/filetests/vcode/aarch64/stack-limit.clif

@@ -44,8 +44,8 @@ block0(v0: i64):
 ; nextln:     mov fp, sp
 ; nextln:     subs xzr, sp, x0
 ; nextln:     b.hs 8 ; udf
-; nextln:     ldr x16
-; nextln:     blr x16
+; nextln:     ldr x0
+; nextln:     blr x0
 ; nextln:     mov sp, fp
 ; nextln:     ldp fp, lr, [sp], #16
 ; nextln:     ret
@@ -67,8 +67,8 @@ block0(v0: i64):
 ; nextln:     ldur x16, [x16, #4]
 ; nextln:     subs xzr, sp, x16
 ; nextln:     b.hs 8 ; udf
-; nextln:     ldr x16
-; nextln:     blr x16
+; nextln:     ldr x0
+; nextln:     blr x0
 ; nextln:     mov sp, fp
 ; nextln:     ldp fp, lr, [sp], #16
 ; nextln:     ret