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Add a FixedTied constraint kind for operand constraints.

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Fixes #175.

The Intel division instructions have fixed input operands that are
clobbered by fixed output operands, so the value passed as an input will
be clobbered just like a tied operand.

The FixedTied operand constraint is used to indicate a fixed input
operand that has a corresponding output operand with the same fixed
register.

Teach the spiller to teach a FixedTied operand the same as a Tied
operand constraint and make sure that the input value is killed by the
instruction.
This commit is contained in:
Jakob Stoklund Olesen
2017-10-25 11:14:11 -07:00
parent 2932a9314d
commit e8ecf1f809
7 changed files with 72 additions and 18 deletions
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10
lib/cretonne/src/isa/constraints.rs
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@@ -37,7 +37,8 @@ impl OperandConstraint {
false
}
}
ConstraintKind::FixedReg(reg) => {
ConstraintKind::FixedReg(reg) |
ConstraintKind::FixedTied(reg) => {
loc == ValueLoc::Reg(reg) && self.regclass.contains(reg)
}
ConstraintKind::Stack => {
@@ -73,6 +74,13 @@ pub enum ConstraintKind {
/// the out operand is `Tied(in)`.
Tied(u8),
/// This operand must be a fixed register, and it has a tied counterpart.
///
/// This works just like `FixedReg`, but additionally indicates that there are identical
/// input/output operands for this fixed register. For an input operand, this means that the
/// value will be clobbered by the instruction
FixedTied(RegUnit),
/// This operand must be a value in a stack slot.
///
/// The constraint's `regclass` field is the register class that would normally be used to load