Add a FixedTied constraint kind for operand constraints.

Fixes #175.

The Intel division instructions have fixed input operands that are
clobbered by fixed output operands, so the value passed as an input will
be clobbered just like a tied operand.

The FixedTied operand constraint is used to indicate a fixed input
operand that has a corresponding output operand with the same fixed
register.

Teach the spiller to teach a FixedTied operand the same as a Tied
operand constraint and make sure that the input value is killed by the
instruction.

lib/cretonne/meta/cdsl/isa.py

@@ -394,6 +394,16 @@ class EncRecipe(object):
                 o2i[o] = i
         return (i2o, o2i)
 
+    def fixed_ops(self):
+        # type: () -> Tuple[Set[Register], Set[Register]]
+        """
+        Return two sets of registers representing the fixed input and output
+        operands.
+        """
+        i = set(r for r in self.ins if isinstance(r, Register))
+        o = set(r for r in self.outs if isinstance(r, Register))
+        return (i, o)
+
     def recipe_pred(self):
         # type: () -> RecipePred
         """

lib/cretonne/meta/cdsl/registers.py

@@ -286,7 +286,10 @@ class RegClass(object):
 
         For example: `GPR.r5`.
         """
-        return Register(self, self.bank.unit_by_name(attr))
+        reg = Register(self, self.bank.unit_by_name(attr))
+        # Save this register so we won't have to create it again.
+        setattr(self, attr, reg)
+        return reg
 
     def mask(self):
         # type: () -> List[int]