From e898cb750a6307b9491fdb1f06acbdf3ee5e7c94 Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Tue, 17 May 2022 17:43:43 -0700
Subject: [PATCH] x64: remove TODO for i128 load (#4159)

This work has already been finished in a previous PR.
---
 cranelift/codegen/src/isa/x64/lower.isle | 2 --
 1 file changed, 2 deletions(-)

diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle
index ea7b1fa6a4..af12600da8 100644
--- a/cranelift/codegen/src/isa/x64/lower.isle
+++ b/cranelift/codegen/src/isa/x64/lower.isle
@@ -2578,8 +2578,6 @@
 (rule (lower (has_type $I64X2 (uload32x2 flags address offset)))
       (x64_pmovzxdq (to_amode flags address offset)))
 
-;; TODO: Multi-register loads (I128)
-
 ;; Rules for `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; 8-, 16-, 32- and 64-bit GPR stores.