Add trap codes to the Cretonne IL.

The trap and trapz/trapnz instructions now take a trap code immediate
operand which indicates the reason for trapping.

lib/cretonne/meta/isa/intel/encodings.py

@@ -287,8 +287,8 @@ I64.enc(base.brnz.b1, *r.t8jccb_abcd(0x75))
 #
 # Trap as ud2
 #
-I32.enc(base.trap, *r.noop(0x0f, 0x0b))
-I64.enc(base.trap, *r.noop(0x0f, 0x0b))
+I32.enc(base.trap, *r.trap(0x0f, 0x0b))
+I64.enc(base.trap, *r.trap(0x0f, 0x0b))
 
 #
 # Comparisons

lib/cretonne/meta/isa/intel/recipes.py

@@ -5,7 +5,7 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
-from base.formats import Nullary, Call, IndirectCall, Store, Load
+from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare
 from base.formats import RegMove, Ternary, Jump, Branch, FuncAddr
 from .registers import GPR, ABCD, FPR
@@ -195,8 +195,8 @@ class TailRecipe:
 null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
 
 # XX opcode, no ModR/M.
-noop = TailRecipe(
-        'noop', Nullary, size=0, ins=(), outs=(),
+trap = TailRecipe(
+        'trap', Trap, size=0, ins=(), outs=(),
         emit='PUT_OP(bits, BASE_REX, sink);')
 
 # XX /r