aarch64: Implement missing atomic rmw ops
This commit is contained in:
Afonso Bordado
@@ -1273,6 +1273,8 @@ impl MachInstEmit for Inst {
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mov x28, x26
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so that we simply write in the destination, the "2nd arg for op".
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*/
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// TODO: We should not hardcode registers here, a better idea would be to
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// pass some scratch registers in the AtomicRMW pseudo-instruction, and use those
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let xzr = zero_reg();
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let x24 = xreg(24);
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let x25 = xreg(25);
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@@ -1294,25 +1296,90 @@ impl MachInstEmit for Inst {
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}
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sink.put4(enc_ldxr(ty, x27wr, x25)); // ldxr x27, [x25]
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if op == inst_common::AtomicRmwOp::Xchg {
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// mov x28, x26
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sink.put4(enc_arith_rrr(0b101_01010_00_0, 0b000000, x28wr, xzr, x26))
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} else {
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// add/sub/and/orr/eor x28, x27, x26
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let bits_31_21 = match op {
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inst_common::AtomicRmwOp::Add => 0b100_01011_00_0,
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inst_common::AtomicRmwOp::Sub => 0b110_01011_00_0,
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inst_common::AtomicRmwOp::And => 0b100_01010_00_0,
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inst_common::AtomicRmwOp::Or => 0b101_01010_00_0,
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inst_common::AtomicRmwOp::Xor => 0b110_01010_00_0,
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inst_common::AtomicRmwOp::Nand
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| inst_common::AtomicRmwOp::Umin
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| inst_common::AtomicRmwOp::Umax
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| inst_common::AtomicRmwOp::Smin
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| inst_common::AtomicRmwOp::Smax => todo!("{:?}", op),
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inst_common::AtomicRmwOp::Xchg => unreachable!(),
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};
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sink.put4(enc_arith_rrr(bits_31_21, 0b000000, x28wr, x27, x26));
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match op {
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AtomicRmwOp::Xchg => {
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// mov x28, x26
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Inst::Mov64 { rd: x28wr, rm: x26 }.emit(sink, emit_info, state);
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}
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AtomicRmwOp::Nand => {
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// and x28, x27, x26
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// mvn x28, x28
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Inst::AluRRR {
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alu_op: ALUOp::And64,
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rd: x28wr,
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rn: x27,
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rm: x26,
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}
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.emit(sink, emit_info, state);
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Inst::AluRRR {
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alu_op: ALUOp::OrrNot64,
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rd: x28wr,
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rn: xzr,
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rm: x28,
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}
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.emit(sink, emit_info, state);
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}
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AtomicRmwOp::Umin
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| AtomicRmwOp::Umax
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| AtomicRmwOp::Smin
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| AtomicRmwOp::Smax => {
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// cmp x27, x26
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// csel.op x28, x27, x26
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let cond = match op {
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AtomicRmwOp::Umin => Cond::Lo,
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AtomicRmwOp::Umax => Cond::Hi,
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AtomicRmwOp::Smin => Cond::Lt,
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AtomicRmwOp::Smax => Cond::Gt,
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_ => unreachable!(),
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};
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Inst::AluRRR {
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alu_op: if ty == I64 {
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ALUOp::SubS64
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} else {
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ALUOp::SubS32
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},
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rd: writable_zero_reg(),
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rn: x27,
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rm: x26,
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}
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.emit(sink, emit_info, state);
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Inst::CSel {
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cond,
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rd: x28wr,
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rn: x27,
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rm: x26,
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}
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.emit(sink, emit_info, state);
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}
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_ => {
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// add/sub/and/orr/eor x28, x27, x26
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let alu_op = match op {
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AtomicRmwOp::Add => ALUOp::Add64,
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AtomicRmwOp::Sub => ALUOp::Sub64,
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AtomicRmwOp::And => ALUOp::And64,
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AtomicRmwOp::Or => ALUOp::Orr64,
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AtomicRmwOp::Xor => ALUOp::Eor64,
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AtomicRmwOp::Nand
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| AtomicRmwOp::Umin
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| AtomicRmwOp::Umax
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| AtomicRmwOp::Smin
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| AtomicRmwOp::Smax
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| AtomicRmwOp::Xchg => unreachable!(),
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};
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Inst::AluRRR {
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alu_op,
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rd: x28wr,
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rn: x27,
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rm: x26,
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}
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.emit(sink, emit_info, state);
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}
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}
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let srcloc = state.cur_srcloc();
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237
cranelift/filetests/filetests/runtests/atomic-rmw-2.clif
Normal file
237
cranelift/filetests/filetests/runtests/atomic-rmw-2.clif
Normal file
@@ -0,0 +1,237 @@
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test run
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target aarch64
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target x86_64 machinst
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; TODO: Merge this with atomic-rmw.clif when s390x supports it
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function %atomic_rmw_nand_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 nand v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_nand_i64(0, 0) == -1
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; run: %atomic_rmw_nand_i64(1, 0) == -1
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; run: %atomic_rmw_nand_i64(0, 1) == -1
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; run: %atomic_rmw_nand_i64(1, 1) == -2
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; run: %atomic_rmw_nand_i64(0xC0FFEEEE_DECAFFFF, 0x7DCB5691_7DCB5691) == 0xBF34B97F_A335A96E
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function %atomic_rmw_nand_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 nand v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_nand_i32(0, 0) == -1
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; run: %atomic_rmw_nand_i32(1, 0) == -1
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; run: %atomic_rmw_nand_i32(0, 1) == -1
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; run: %atomic_rmw_nand_i32(1, 1) == -2
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; run: %atomic_rmw_nand_i32(0xC0FFEEEE, 0x7DCB5691) == 0xBF34B97F
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function %atomic_rmw_umin_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 umin v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_umin_i64(0, 0) == 0
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; run: %atomic_rmw_umin_i64(1, 0) == 0
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; run: %atomic_rmw_umin_i64(0, 1) == 0
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; run: %atomic_rmw_umin_i64(1, 1) == 1
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; run: %atomic_rmw_umin_i64(-1, 1) == 1
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; run: %atomic_rmw_umin_i64(-1, -3) == -3
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function %atomic_rmw_umin_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 umin v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_umin_i32(0, 0) == 0
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; run: %atomic_rmw_umin_i32(1, 0) == 0
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; run: %atomic_rmw_umin_i32(0, 1) == 0
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; run: %atomic_rmw_umin_i32(1, 1) == 1
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; run: %atomic_rmw_umin_i32(-1, 1) == 1
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; run: %atomic_rmw_umin_i32(-1, -3) == -3
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function %atomic_rmw_umax_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 umax v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_umax_i64(0, 0) == 0
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; run: %atomic_rmw_umax_i64(1, 0) == 1
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; run: %atomic_rmw_umax_i64(0, 1) == 1
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; run: %atomic_rmw_umax_i64(1, 1) == 1
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; run: %atomic_rmw_umax_i64(-1, 1) == -1
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; run: %atomic_rmw_umax_i64(-1, -3) == -1
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function %atomic_rmw_umax_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 umax v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_umax_i32(0, 0) == 0
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; run: %atomic_rmw_umax_i32(1, 0) == 1
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; run: %atomic_rmw_umax_i32(0, 1) == 1
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; run: %atomic_rmw_umax_i32(1, 1) == 1
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; run: %atomic_rmw_umax_i32(-1, 1) == -1
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; run: %atomic_rmw_umax_i32(-1, -3) == -1
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function %atomic_rmw_smin_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 smin v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_smin_i64(0, 0) == 0
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; run: %atomic_rmw_smin_i64(1, 0) == 0
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; run: %atomic_rmw_smin_i64(0, 1) == 0
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; run: %atomic_rmw_smin_i64(1, 1) == 1
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; run: %atomic_rmw_smin_i64(-1, 1) == -1
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; run: %atomic_rmw_smin_i64(-1, -3) == -3
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function %atomic_rmw_smin_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 smin v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_smin_i32(0, 0) == 0
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; run: %atomic_rmw_smin_i32(1, 0) == 0
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; run: %atomic_rmw_smin_i32(0, 1) == 0
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; run: %atomic_rmw_smin_i32(1, 1) == 1
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; run: %atomic_rmw_smin_i32(-1, -1) == -1
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; run: %atomic_rmw_smin_i32(-1, -3) == -3
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function %atomic_rmw_smax_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 smax v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_smax_i64(0, 0) == 0
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; run: %atomic_rmw_smax_i64(1, 0) == 1
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; run: %atomic_rmw_smax_i64(0, 1) == 1
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; run: %atomic_rmw_smax_i64(1, 1) == 1
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; run: %atomic_rmw_smax_i64(-1, 1) == 1
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; run: %atomic_rmw_smax_i64(-1, -3) == -1
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function %atomic_rmw_smax_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 smax v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_smax_i32(0, 0) == 0
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; run: %atomic_rmw_smax_i32(1, 0) == 1
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; run: %atomic_rmw_smax_i32(0, 1) == 1
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; run: %atomic_rmw_smax_i32(1, 1) == 1
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; run: %atomic_rmw_smax_i32(-1, 1) == 1
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; run: %atomic_rmw_smax_i32(-1, -3) == -1
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function %atomic_rmw_xchg_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 xchg v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_xchg_i64(0, 0) == 0
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; run: %atomic_rmw_xchg_i64(1, 0) == 0
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; run: %atomic_rmw_xchg_i64(0, 1) == 1
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; run: %atomic_rmw_xchg_i64(0, 0xC0FFEEEE_DECAFFFF) == 0xC0FFEEEE_DECAFFFF
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function %atomic_rmw_xchg_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 xchg v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_xchg_i32(0, 0) == 0
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; run: %atomic_rmw_xchg_i32(1, 0) == 0
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; run: %atomic_rmw_xchg_i32(0, 1) == 1
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; run: %atomic_rmw_xchg_i32(0, 0xC0FFEEEE) == 0xC0FFEEEE
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197
cranelift/filetests/filetests/runtests/atomic-rmw.clif
Normal file
197
cranelift/filetests/filetests/runtests/atomic-rmw.clif
Normal file
@@ -0,0 +1,197 @@
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test run
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target aarch64
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target x86_64 machinst
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target s390x
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; We can't test that these instructions are right regarding atomicity, but we can
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; test if they perform their operation correctly
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function %atomic_rmw_add_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 add v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_add_i64(0, 0) == 0
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; run: %atomic_rmw_add_i64(1, 0) == 1
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; run: %atomic_rmw_add_i64(0, 1) == 1
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; run: %atomic_rmw_add_i64(1, 1) == 2
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; run: %atomic_rmw_add_i64(0xC0FFEEEE_C0FFEEEE, 0x1DCB1111_1DCB1111) == 0xDECAFFFF_DECAFFFF
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function %atomic_rmw_add_i32(i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32):
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stack_store.i32 v0, ss0
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v2 = stack_addr.i32 ss0
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v3 = atomic_rmw.i32 add v2, v1
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v4 = stack_load.i32 ss0
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return v4
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}
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; run: %atomic_rmw_add_i32(0, 0) == 0
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; run: %atomic_rmw_add_i32(1, 0) == 1
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; run: %atomic_rmw_add_i32(0, 1) == 1
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; run: %atomic_rmw_add_i32(1, 1) == 2
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; run: %atomic_rmw_add_i32(0xC0FFEEEE, 0x1DCB1111) == 0xDECAFFFF
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function %atomic_rmw_sub_i64(i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64):
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stack_store.i64 v0, ss0
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v2 = stack_addr.i64 ss0
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v3 = atomic_rmw.i64 sub v2, v1
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v4 = stack_load.i64 ss0
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return v4
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}
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; run: %atomic_rmw_sub_i64(0, 0) == 0
|
||||
; run: %atomic_rmw_sub_i64(1, 0) == 1
|
||||
; run: %atomic_rmw_sub_i64(0, 1) == -1
|
||||
; run: %atomic_rmw_sub_i64(1, 1) == 0
|
||||
; run: %atomic_rmw_sub_i64(0xDECAFFFF_DECAFFFF, 0x1DCB1111_1DCB1111) == 0xC0FFEEEE_C0FFEEEE
|
||||
|
||||
function %atomic_rmw_sub_i32(i32, i32) -> i32 {
|
||||
ss0 = explicit_slot 4
|
||||
|
||||
block0(v0: i32, v1: i32):
|
||||
stack_store.i32 v0, ss0
|
||||
|
||||
v2 = stack_addr.i32 ss0
|
||||
v3 = atomic_rmw.i32 sub v2, v1
|
||||
|
||||
v4 = stack_load.i32 ss0
|
||||
return v4
|
||||
}
|
||||
; run: %atomic_rmw_sub_i32(0, 0) == 0
|
||||
; run: %atomic_rmw_sub_i32(1, 0) == 1
|
||||
; run: %atomic_rmw_sub_i32(0, 1) == -1
|
||||
; run: %atomic_rmw_sub_i32(1, 1) == 0
|
||||
; run: %atomic_rmw_sub_i32(0xDECAFFFF, 0x1DCB1111) == 0xC0FFEEEE
|
||||
|
||||
|
||||
|
||||
function %atomic_rmw_and_i64(i64, i64) -> i64 {
|
||||
ss0 = explicit_slot 8
|
||||
|
||||
block0(v0: i64, v1: i64):
|
||||
stack_store.i64 v0, ss0
|
||||
|
||||
v2 = stack_addr.i64 ss0
|
||||
v3 = atomic_rmw.i64 and v2, v1
|
||||
|
||||
v4 = stack_load.i64 ss0
|
||||
return v4
|
||||
}
|
||||
; run: %atomic_rmw_and_i64(0, 0) == 0
|
||||
; run: %atomic_rmw_and_i64(1, 0) == 0
|
||||
; run: %atomic_rmw_and_i64(0, 1) == 0
|
||||
; run: %atomic_rmw_and_i64(1, 1) == 1
|
||||
; run: %atomic_rmw_and_i64(0xF1FFFEFE_FEEEFFFF, 0xCEFFEFEF_DFDBFFFF) == 0xC0FFEEEE_DECAFFFF
|
||||
|
||||
function %atomic_rmw_and_i32(i32, i32) -> i32 {
|
||||
ss0 = explicit_slot 4
|
||||
|
||||
block0(v0: i32, v1: i32):
|
||||
stack_store.i32 v0, ss0
|
||||
|
||||
v2 = stack_addr.i32 ss0
|
||||
v3 = atomic_rmw.i32 and v2, v1
|
||||
|
||||
v4 = stack_load.i32 ss0
|
||||
return v4
|
||||
}
|
||||
|
||||
; run: %atomic_rmw_and_i64(0, 0) == 0
|
||||
; run: %atomic_rmw_and_i64(1, 0) == 0
|
||||
; run: %atomic_rmw_and_i64(0, 1) == 0
|
||||
; run: %atomic_rmw_and_i64(1, 1) == 1
|
||||
; run: %atomic_rmw_and_i64(0xF1FFFEFE, 0xCEFFEFEF) == 0xC0FFEEEE
|
||||
|
||||
|
||||
|
||||
function %atomic_rmw_or_i64(i64, i64) -> i64 {
|
||||
ss0 = explicit_slot 8
|
||||
|
||||
block0(v0: i64, v1: i64):
|
||||
stack_store.i64 v0, ss0
|
||||
|
||||
v2 = stack_addr.i64 ss0
|
||||
v3 = atomic_rmw.i64 or v2, v1
|
||||
|
||||
v4 = stack_load.i64 ss0
|
||||
return v4
|
||||
}
|
||||
; run: %atomic_rmw_or_i64(0, 0) == 0
|
||||
; run: %atomic_rmw_or_i64(1, 0) == 1
|
||||
; run: %atomic_rmw_or_i64(0, 1) == 1
|
||||
; run: %atomic_rmw_or_i64(1, 1) == 1
|
||||
; run: %atomic_rmw_or_i64(0x80AAAAAA_8A8AAAAA, 0x40554444_54405555) == 0xC0FFEEEE_DECAFFFF
|
||||
|
||||
function %atomic_rmw_or_i32(i32, i32) -> i32 {
|
||||
ss0 = explicit_slot 4
|
||||
|
||||
block0(v0: i32, v1: i32):
|
||||
stack_store.i32 v0, ss0
|
||||
|
||||
v2 = stack_addr.i32 ss0
|
||||
v3 = atomic_rmw.i32 or v2, v1
|
||||
|
||||
v4 = stack_load.i32 ss0
|
||||
return v4
|
||||
}
|
||||
|
||||
; run: %atomic_rmw_or_i32(0, 0) == 0
|
||||
; run: %atomic_rmw_or_i32(1, 0) == 1
|
||||
; run: %atomic_rmw_or_i32(0, 1) == 1
|
||||
; run: %atomic_rmw_or_i32(1, 1) == 1
|
||||
; run: %atomic_rmw_or_i32(0x80AAAAAA, 0x40554444) == 0xC0FFEEEE
|
||||
|
||||
|
||||
|
||||
function %atomic_rmw_xor_i64(i64, i64) -> i64 {
|
||||
ss0 = explicit_slot 8
|
||||
|
||||
block0(v0: i64, v1: i64):
|
||||
stack_store.i64 v0, ss0
|
||||
|
||||
v2 = stack_addr.i64 ss0
|
||||
v3 = atomic_rmw.i64 xor v2, v1
|
||||
|
||||
v4 = stack_load.i64 ss0
|
||||
return v4
|
||||
}
|
||||
; run: %atomic_rmw_xor_i64(0, 0) == 0
|
||||
; run: %atomic_rmw_xor_i64(1, 0) == 1
|
||||
; run: %atomic_rmw_xor_i64(0, 1) == 1
|
||||
; run: %atomic_rmw_xor_i64(1, 1) == 0
|
||||
; run: %atomic_rmw_xor_i64(0x8FA50A64_9440A07D, 0x4F5AE48A_4A8A5F82) == 0xC0FFEEEE_DECAFFFF
|
||||
|
||||
function %atomic_rmw_xor_i32(i32, i32) -> i32 {
|
||||
ss0 = explicit_slot 4
|
||||
|
||||
block0(v0: i32, v1: i32):
|
||||
stack_store.i32 v0, ss0
|
||||
|
||||
v2 = stack_addr.i32 ss0
|
||||
v3 = atomic_rmw.i32 xor v2, v1
|
||||
|
||||
v4 = stack_load.i32 ss0
|
||||
return v4
|
||||
}
|
||||
; run: %atomic_rmw_xor_i32(0, 0) == 0
|
||||
; run: %atomic_rmw_xor_i32(1, 0) == 1
|
||||
; run: %atomic_rmw_xor_i32(0, 1) == 1
|
||||
; run: %atomic_rmw_xor_i32(1, 1) == 0
|
||||
; run: %atomic_rmw_xor_i32(0x8FA50A64, 0x4F5AE48A) == 0xC0FFEEEE
|
||||
Reference in New Issue
Block a user