Documentation fixes (#103)

* Clarify that extended basic blocks are abbreviated as EBB.

* Fix typo.

* Fix a typo.

* Fix typos.

* Use the same phrase to indicate scalar-only as other places in the doc.

* Mention that `band_imm` and friends are scalar-only.

And mention that they're equivalent to their respective
non-immediate-form counterparts.

docs/compare-llvm.rst

@@ -152,7 +152,7 @@ can hold.
   address type too.
 - SIMD vector types are limited to a power-of-two number of vector lanes up to
   256. LLVM allows an arbitrary number of SIMD lanes.
-- Cretonne has no aggregrate types. LLVM has named and anonymous struct types as
+- Cretonne has no aggregate types. LLVM has named and anonymous struct types as
   well as array types.
 
 Cretonne has multiple boolean types, whereas LLVM simply uses `i1`. The sized
@@ -160,7 +160,7 @@ Cretonne boolean types are used to represent SIMD vector masks like ``b32x4``
 where each lane is either all 0 or all 1 bits.
 
 Cretonne instructions and function calls can return multiple result values. LLVM
-instead models this by returning a single value of an aggregrate type.
+instead models this by returning a single value of an aggregate type.
 
 Instruction set
 ---------------

docs/langref.rst

@@ -40,9 +40,9 @@ that can be referenced inside the function. In the example above, the preamble
 declares a single local variable, ``ss1``.
 
 After the preamble follows the :term:`function body` which consists of
-:term:`extended basic block`\s, the first of which is the :term:`entry block`.
-Every EBB ends with a :term:`terminator instruction`, so execution can never
-fall through to the next EBB without an explicit branch.
+:term:`extended basic block`\s (EBBs), the first of which is the
+:term:`entry block`. Every EBB ends with a :term:`terminator instruction`, so
+execution can never fall through to the next EBB without an explicit branch.
 
 A ``.cton`` file consists of a sequence of independent function definitions:
 
@@ -253,7 +253,7 @@ indicate the different kinds of immediate operands on an instruction.
     A signed 32-bit immediate address offset.
 
     In the textual format, :type:`offset32` immediates always have an explicit
-    sign, and a 0 offset may beomitted.
+    sign, and a 0 offset may be omitted.
 
 .. type:: ieee32
 

docs/regalloc.rst

@@ -55,12 +55,12 @@ EBB argument fixup
 
 The contract between the spilling and coloring phases is that the number of
 values in registers never exceeds the number of available registers. This
-sounds simple enough in theory, but in pratice there are some complications.
+sounds simple enough in theory, but in practice there are some complications.
 
 Real-world complications to SSA coloring
 ----------------------------------------
 
-In practice, instruction set architectures don't have "K interchangable
+In practice, instruction set architectures don't have "K interchangeable
 registers", and register pressure can't be measured with a single number. There
 are complications:
 

docs/testing.rst

@@ -100,7 +100,7 @@ of input functions in the :doc:`Cretonne textual intermediate language
 
 The available test commands are described below.
 
-Many test comands only make sense in the context of a target instruction set
+Many test commands only make sense in the context of a target instruction set
 architecture. These tests require one or more ISA specifications in the test
 header: