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[AArch64] Merge 32- and 64-bit ALUOps (#3802)

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Combine the two opcodes into one and pass and add an OperandSize
field to these instructions, as well as an ISLE helper to perform
the conversion from Type.

This saves us from having having to write ISLE helpers to select the
correct opcode, based on type, and reduces the amount of code needed
for emission.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-02-17 18:03:54 +00:00
committed by GitHub
parent b62fe21914
commit e572198f85
10 changed files with 1786 additions and 1987 deletions
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284
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -32,7 +32,8 @@ fn test_aarch64_binemit() {
insns.push((Inst::Nop4, "1F2003D5", "nop"));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Add32,
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -42,7 +43,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Add64,
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -52,7 +54,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Adc32,
alu_op: ALUOp::Adc,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -62,7 +65,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Adc64,
alu_op: ALUOp::Adc,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -72,7 +76,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS32,
alu_op: ALUOp::AdcS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -82,7 +87,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS64,
alu_op: ALUOp::AdcS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -92,7 +98,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -102,7 +109,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -112,7 +120,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sbc32,
alu_op: ALUOp::Sbc,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -122,7 +131,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sbc64,
alu_op: ALUOp::Sbc,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -132,7 +142,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS32,
alu_op: ALUOp::SbcS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -142,7 +153,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS64,
alu_op: ALUOp::SbcS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -153,7 +165,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Orr32,
alu_op: ALUOp::Orr,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -163,7 +176,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Orr64,
alu_op: ALUOp::Orr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -173,7 +187,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::And32,
alu_op: ALUOp::And,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -183,7 +198,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::And64,
alu_op: ALUOp::And,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -193,7 +209,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS32,
alu_op: ALUOp::AndS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -203,7 +220,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS64,
alu_op: ALUOp::AndS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -213,7 +231,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS32,
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_zero_reg(),
rn: xreg(2),
rm: xreg(3),
@@ -224,7 +243,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS32,
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -234,7 +254,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS64,
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -244,7 +265,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddS32,
alu_op: ALUOp::AddS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -254,7 +276,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddS64,
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -264,7 +287,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::AddS64,
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_zero_reg(),
rn: xreg(5),
imm12: Imm12::maybe_from_u64(1).unwrap(),
@@ -275,7 +299,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SDiv64,
alu_op: ALUOp::SDiv,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -285,7 +310,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::UDiv64,
alu_op: ALUOp::UDiv,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -296,7 +322,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Eor32,
alu_op: ALUOp::Eor,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -306,7 +333,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Eor64,
alu_op: ALUOp::Eor,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -316,7 +344,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndNot32,
alu_op: ALUOp::AndNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -326,7 +355,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndNot64,
alu_op: ALUOp::AndNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -336,7 +366,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::OrrNot32,
alu_op: ALUOp::OrrNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -346,7 +377,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::OrrNot64,
alu_op: ALUOp::OrrNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -356,7 +388,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::EorNot32,
alu_op: ALUOp::EorNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -366,7 +399,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::EorNot64,
alu_op: ALUOp::EorNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -377,7 +411,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRR {
alu_op: ALUOp::RotR32,
alu_op: ALUOp::RotR,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -387,7 +422,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::RotR64,
alu_op: ALUOp::RotR,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -397,7 +433,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsr32,
alu_op: ALUOp::Lsr,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -407,7 +444,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsr64,
alu_op: ALUOp::Lsr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -417,7 +455,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Asr32,
alu_op: ALUOp::Asr,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -427,7 +466,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Asr64,
alu_op: ALUOp::Asr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -437,7 +477,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsl32,
alu_op: ALUOp::Lsl,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -447,7 +488,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsl64,
alu_op: ALUOp::Lsl,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
@@ -458,7 +500,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add32,
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -471,7 +514,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add32,
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -484,7 +528,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add64,
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -497,7 +542,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -510,7 +556,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -523,7 +570,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::SubS32,
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -536,7 +584,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::SubS64,
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
@@ -550,7 +599,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Add32,
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
rm: xreg(9),
@@ -562,7 +612,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Add64,
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(15),
rn: xreg(16),
rm: xreg(17),
@@ -574,7 +625,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -586,7 +638,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(20),
rn: xreg(21),
rm: xreg(22),
@@ -598,7 +651,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Add32,
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -612,7 +666,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Add64,
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -626,7 +681,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -640,7 +696,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -654,7 +711,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Orr32,
alu_op: ALUOp::Orr,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -668,7 +726,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Orr64,
alu_op: ALUOp::Orr,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -682,7 +741,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::And32,
alu_op: ALUOp::And,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -696,7 +756,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::And64,
alu_op: ALUOp::And,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -710,7 +771,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS32,
alu_op: ALUOp::AndS,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -724,7 +786,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS64,
alu_op: ALUOp::AndS,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -738,7 +801,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Eor32,
alu_op: ALUOp::Eor,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -752,7 +816,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Eor64,
alu_op: ALUOp::Eor,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -766,7 +831,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::OrrNot32,
alu_op: ALUOp::OrrNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -780,7 +846,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::OrrNot64,
alu_op: ALUOp::OrrNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -794,7 +861,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndNot32,
alu_op: ALUOp::AndNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -808,7 +876,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndNot64,
alu_op: ALUOp::AndNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -822,7 +891,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::EorNot32,
alu_op: ALUOp::EorNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -836,7 +906,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::EorNot64,
alu_op: ALUOp::EorNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -850,7 +921,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AddS32,
alu_op: ALUOp::AddS,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -864,7 +936,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AddS64,
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -878,7 +951,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::SubS32,
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -892,7 +966,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::SubS64,
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
@@ -907,7 +982,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::SubS64,
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_zero_reg(),
rn: stack_reg(),
rm: xreg(12),
@@ -964,6 +1040,7 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SMulH,
size: OperandSize::Size64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -974,6 +1051,7 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRR {
alu_op: ALUOp::UMulH,
size: OperandSize::Size64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -984,7 +1062,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::RotR32,
alu_op: ALUOp::RotR,
size: OperandSize::Size32,
rd: writable_xreg(20),
rn: xreg(21),
immshift: ImmShift::maybe_from_u64(19).unwrap(),
@@ -994,7 +1073,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::RotR64,
alu_op: ALUOp::RotR,
size: OperandSize::Size64,
rd: writable_xreg(20),
rn: xreg(21),
immshift: ImmShift::maybe_from_u64(42).unwrap(),
@@ -1004,7 +1084,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsr32,
alu_op: ALUOp::Lsr,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
immshift: ImmShift::maybe_from_u64(13).unwrap(),
@@ -1014,7 +1095,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsr64,
alu_op: ALUOp::Lsr,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
immshift: ImmShift::maybe_from_u64(57).unwrap(),
@@ -1024,7 +1106,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Asr32,
alu_op: ALUOp::Asr,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
immshift: ImmShift::maybe_from_u64(7).unwrap(),
@@ -1034,7 +1117,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Asr64,
alu_op: ALUOp::Asr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
immshift: ImmShift::maybe_from_u64(35).unwrap(),
@@ -1044,7 +1128,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsl32,
alu_op: ALUOp::Lsl,
size: OperandSize::Size32,
rd: writable_xreg(8),
rn: xreg(9),
immshift: ImmShift::maybe_from_u64(24).unwrap(),
@@ -1054,7 +1139,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsl64,
alu_op: ALUOp::Lsl,
size: OperandSize::Size64,
rd: writable_xreg(8),
rn: xreg(9),
immshift: ImmShift::maybe_from_u64(63).unwrap(),
@@ -1064,7 +1150,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsl32,
alu_op: ALUOp::Lsl,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
immshift: ImmShift::maybe_from_u64(0).unwrap(),
@@ -1074,7 +1161,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmShift {
alu_op: ALUOp::Lsl64,
alu_op: ALUOp::Lsl,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
immshift: ImmShift::maybe_from_u64(0).unwrap(),
@@ -1085,7 +1173,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::And32,
alu_op: ALUOp::And,
size: OperandSize::Size32,
rd: writable_xreg(21),
rn: xreg(27),
imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
@@ -1095,7 +1184,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::And64,
alu_op: ALUOp::And,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(6),
imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
@@ -1105,7 +1195,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::AndS32,
alu_op: ALUOp::AndS,
size: OperandSize::Size32,
rd: writable_xreg(21),
rn: xreg(27),
imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
@@ -1115,7 +1206,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::AndS64,
alu_op: ALUOp::AndS,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(6),
imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
@@ -1125,7 +1217,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::Orr32,
alu_op: ALUOp::Orr,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(5),
imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
@@ -1135,7 +1228,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::Orr64,
alu_op: ALUOp::Orr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
@@ -1145,7 +1239,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::Eor32,
alu_op: ALUOp::Eor,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(5),
imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
@@ -1155,7 +1250,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::Eor64,
alu_op: ALUOp::Eor,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(8),
imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),