[AArch64] Merge 32- and 64-bit ALUOps (#3802)
Combine the two opcodes into one and pass and add an OperandSize field to these instructions, as well as an ISLE helper to perform the conversion from Type. This saves us from having having to write ISLE helpers to select the correct opcode, based on type, and reduces the amount of code needed for emission. Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
@@ -67,7 +67,8 @@ pub fn mem_finalize(
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// is a valid base (for SPOffset) which we must handle here.
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// Also, SP needs to be the first arg, not second.
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let add_inst = Inst::AluRRRExtend {
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alu_op: ALUOp::Add64,
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alu_op: ALUOp::Add,
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size: OperandSize::Size64,
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rd: tmp,
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rn: basereg,
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rm: tmp.to_reg(),
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@@ -682,52 +683,48 @@ impl MachInstEmit for Inst {
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let mut start_off = sink.cur_offset();
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match self {
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&Inst::AluRRR { alu_op, rd, rn, rm } => {
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&Inst::AluRRR {
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alu_op,
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size,
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rd,
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rn,
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rm,
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} => {
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debug_assert!(match alu_op {
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ALUOp::SDiv | ALUOp::UDiv | ALUOp::SMulH | ALUOp::UMulH =>
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size == OperandSize::Size64,
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_ => true,
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});
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let top11 = match alu_op {
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ALUOp::Add32 => 0b00001011_000,
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ALUOp::Add64 => 0b10001011_000,
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ALUOp::Adc32 => 0b00011010_000,
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ALUOp::Adc64 => 0b10011010_000,
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ALUOp::AdcS32 => 0b00111010_000,
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ALUOp::AdcS64 => 0b10111010_000,
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ALUOp::Sub32 => 0b01001011_000,
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ALUOp::Sub64 => 0b11001011_000,
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ALUOp::Sbc32 => 0b01011010_000,
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ALUOp::Sbc64 => 0b11011010_000,
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ALUOp::SbcS32 => 0b01111010_000,
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ALUOp::SbcS64 => 0b11111010_000,
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ALUOp::Orr32 => 0b00101010_000,
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ALUOp::Orr64 => 0b10101010_000,
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ALUOp::And32 => 0b00001010_000,
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ALUOp::And64 => 0b10001010_000,
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ALUOp::AndS32 => 0b01101010_000,
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ALUOp::AndS64 => 0b11101010_000,
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ALUOp::Eor32 => 0b01001010_000,
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ALUOp::Eor64 => 0b11001010_000,
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ALUOp::OrrNot32 => 0b00101010_001,
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ALUOp::OrrNot64 => 0b10101010_001,
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ALUOp::AndNot32 => 0b00001010_001,
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ALUOp::AndNot64 => 0b10001010_001,
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ALUOp::EorNot32 => 0b01001010_001,
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ALUOp::EorNot64 => 0b11001010_001,
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ALUOp::AddS32 => 0b00101011_000,
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ALUOp::AddS64 => 0b10101011_000,
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ALUOp::SubS32 => 0b01101011_000,
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ALUOp::SubS64 => 0b11101011_000,
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ALUOp::SDiv64 => 0b10011010_110,
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ALUOp::UDiv64 => 0b10011010_110,
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ALUOp::RotR32 | ALUOp::Lsr32 | ALUOp::Asr32 | ALUOp::Lsl32 => 0b00011010_110,
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ALUOp::RotR64 | ALUOp::Lsr64 | ALUOp::Asr64 | ALUOp::Lsl64 => 0b10011010_110,
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ALUOp::Add => 0b00001011_000,
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ALUOp::Adc => 0b00011010_000,
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ALUOp::AdcS => 0b00111010_000,
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ALUOp::Sub => 0b01001011_000,
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ALUOp::Sbc => 0b01011010_000,
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ALUOp::SbcS => 0b01111010_000,
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ALUOp::Orr => 0b00101010_000,
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ALUOp::And => 0b00001010_000,
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ALUOp::AndS => 0b01101010_000,
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ALUOp::Eor => 0b01001010_000,
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ALUOp::OrrNot => 0b00101010_001,
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ALUOp::AndNot => 0b00001010_001,
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ALUOp::EorNot => 0b01001010_001,
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ALUOp::AddS => 0b00101011_000,
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ALUOp::SubS => 0b01101011_000,
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ALUOp::SDiv => 0b10011010_110,
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ALUOp::UDiv => 0b10011010_110,
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ALUOp::RotR | ALUOp::Lsr | ALUOp::Asr | ALUOp::Lsl => 0b00011010_110,
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ALUOp::SMulH => 0b10011011_010,
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ALUOp::UMulH => 0b10011011_110,
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};
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let top11 = top11 | size.sf_bit() << 10;
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let bit15_10 = match alu_op {
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ALUOp::SDiv64 => 0b000011,
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ALUOp::UDiv64 => 0b000010,
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ALUOp::RotR32 | ALUOp::RotR64 => 0b001011,
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ALUOp::Lsr32 | ALUOp::Lsr64 => 0b001001,
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ALUOp::Asr32 | ALUOp::Asr64 => 0b001010,
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ALUOp::Lsl32 | ALUOp::Lsl64 => 0b001000,
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ALUOp::SDiv => 0b000011,
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ALUOp::UDiv => 0b000010,
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ALUOp::RotR => 0b001011,
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ALUOp::Lsr => 0b001001,
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ALUOp::Asr => 0b001010,
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ALUOp::Lsl => 0b001000,
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ALUOp::SMulH | ALUOp::UMulH => 0b011111,
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_ => 0b000000,
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};
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@@ -755,21 +752,19 @@ impl MachInstEmit for Inst {
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}
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&Inst::AluRRImm12 {
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alu_op,
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size,
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rd,
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rn,
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ref imm12,
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} => {
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let top8 = match alu_op {
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ALUOp::Add32 => 0b000_10001,
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ALUOp::Add64 => 0b100_10001,
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ALUOp::Sub32 => 0b010_10001,
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ALUOp::Sub64 => 0b110_10001,
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ALUOp::AddS32 => 0b001_10001,
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ALUOp::AddS64 => 0b101_10001,
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ALUOp::SubS32 => 0b011_10001,
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ALUOp::SubS64 => 0b111_10001,
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ALUOp::Add => 0b000_10001,
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ALUOp::Sub => 0b010_10001,
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ALUOp::AddS => 0b001_10001,
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ALUOp::SubS => 0b011_10001,
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_ => unimplemented!("{:?}", alu_op),
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};
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let top8 = top8 | size.sf_bit() << 7;
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sink.put4(enc_arith_rr_imm12(
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top8,
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imm12.shift_bits(),
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@@ -780,57 +775,53 @@ impl MachInstEmit for Inst {
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}
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&Inst::AluRRImmLogic {
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alu_op,
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size,
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rd,
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rn,
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ref imml,
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} => {
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let (top9, inv) = match alu_op {
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ALUOp::Orr32 => (0b001_100100, false),
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ALUOp::Orr64 => (0b101_100100, false),
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ALUOp::And32 => (0b000_100100, false),
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ALUOp::And64 => (0b100_100100, false),
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ALUOp::AndS32 => (0b011_100100, false),
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ALUOp::AndS64 => (0b111_100100, false),
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ALUOp::Eor32 => (0b010_100100, false),
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ALUOp::Eor64 => (0b110_100100, false),
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ALUOp::OrrNot32 => (0b001_100100, true),
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ALUOp::OrrNot64 => (0b101_100100, true),
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ALUOp::AndNot32 => (0b000_100100, true),
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ALUOp::AndNot64 => (0b100_100100, true),
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ALUOp::EorNot32 => (0b010_100100, true),
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ALUOp::EorNot64 => (0b110_100100, true),
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ALUOp::Orr => (0b001_100100, false),
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ALUOp::And => (0b000_100100, false),
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ALUOp::AndS => (0b011_100100, false),
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ALUOp::Eor => (0b010_100100, false),
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ALUOp::OrrNot => (0b001_100100, true),
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ALUOp::AndNot => (0b000_100100, true),
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ALUOp::EorNot => (0b010_100100, true),
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_ => unimplemented!("{:?}", alu_op),
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};
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let top9 = top9 | size.sf_bit() << 8;
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let imml = if inv { imml.invert() } else { imml.clone() };
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sink.put4(enc_arith_rr_imml(top9, imml.enc_bits(), rn, rd));
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}
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&Inst::AluRRImmShift {
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alu_op,
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size,
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rd,
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rn,
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ref immshift,
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} => {
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let amt = immshift.value();
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let (top10, immr, imms) = match alu_op {
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ALUOp::RotR32 => (0b0001001110, machreg_to_gpr(rn), u32::from(amt)),
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ALUOp::RotR64 => (0b1001001111, machreg_to_gpr(rn), u32::from(amt)),
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ALUOp::Lsr32 => (0b0101001100, u32::from(amt), 0b011111),
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ALUOp::Lsr64 => (0b1101001101, u32::from(amt), 0b111111),
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ALUOp::Asr32 => (0b0001001100, u32::from(amt), 0b011111),
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ALUOp::Asr64 => (0b1001001101, u32::from(amt), 0b111111),
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ALUOp::Lsl32 => (
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0b0101001100,
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u32::from((32 - amt) % 32),
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u32::from(31 - amt),
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),
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ALUOp::Lsl64 => (
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0b1101001101,
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u32::from((64 - amt) % 64),
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u32::from(63 - amt),
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),
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ALUOp::RotR => (0b0001001110, machreg_to_gpr(rn), u32::from(amt)),
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ALUOp::Lsr => (0b0101001100, u32::from(amt), 0b011111),
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ALUOp::Asr => (0b0001001100, u32::from(amt), 0b011111),
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ALUOp::Lsl => {
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let bits = if size.is64() { 64 } else { 32 };
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(
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0b0101001100,
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u32::from((bits - amt) % bits),
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u32::from(bits - 1 - amt),
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)
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}
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_ => unimplemented!("{:?}", alu_op),
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};
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let top10 = top10 | size.sf_bit() << 9 | size.sf_bit();
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let imms = match alu_op {
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ALUOp::Lsr | ALUOp::Asr => imms | size.sf_bit() << 5,
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_ => imms,
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};
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sink.put4(
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(top10 << 22)
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| (immr << 16)
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@@ -842,36 +833,27 @@ impl MachInstEmit for Inst {
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&Inst::AluRRRShift {
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alu_op,
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size,
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rd,
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rn,
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rm,
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ref shiftop,
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} => {
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let top11: u32 = match alu_op {
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ALUOp::Add32 => 0b000_01011000,
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ALUOp::Add64 => 0b100_01011000,
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ALUOp::AddS32 => 0b001_01011000,
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ALUOp::AddS64 => 0b101_01011000,
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ALUOp::Sub32 => 0b010_01011000,
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ALUOp::Sub64 => 0b110_01011000,
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ALUOp::SubS32 => 0b011_01011000,
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ALUOp::SubS64 => 0b111_01011000,
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ALUOp::Orr32 => 0b001_01010000,
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ALUOp::Orr64 => 0b101_01010000,
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ALUOp::And32 => 0b000_01010000,
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ALUOp::And64 => 0b100_01010000,
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ALUOp::AndS32 => 0b011_01010000,
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ALUOp::AndS64 => 0b111_01010000,
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ALUOp::Eor32 => 0b010_01010000,
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ALUOp::Eor64 => 0b110_01010000,
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ALUOp::OrrNot32 => 0b001_01010001,
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ALUOp::OrrNot64 => 0b101_01010001,
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ALUOp::EorNot32 => 0b010_01010001,
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ALUOp::EorNot64 => 0b110_01010001,
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ALUOp::AndNot32 => 0b000_01010001,
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ALUOp::AndNot64 => 0b100_01010001,
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ALUOp::Add => 0b000_01011000,
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ALUOp::AddS => 0b001_01011000,
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ALUOp::Sub => 0b010_01011000,
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ALUOp::SubS => 0b011_01011000,
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ALUOp::Orr => 0b001_01010000,
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ALUOp::And => 0b000_01010000,
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ALUOp::AndS => 0b011_01010000,
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ALUOp::Eor => 0b010_01010000,
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ALUOp::OrrNot => 0b001_01010001,
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ALUOp::EorNot => 0b010_01010001,
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ALUOp::AndNot => 0b000_01010001,
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_ => unimplemented!("{:?}", alu_op),
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};
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let top11 = top11 | size.sf_bit() << 10;
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let top11 = top11 | (u32::from(shiftop.op().bits()) << 1);
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let bits_15_10 = u32::from(shiftop.amt().value());
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sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
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@@ -879,22 +861,20 @@ impl MachInstEmit for Inst {
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&Inst::AluRRRExtend {
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alu_op,
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size,
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rd,
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rn,
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rm,
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extendop,
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} => {
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let top11: u32 = match alu_op {
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ALUOp::Add32 => 0b00001011001,
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ALUOp::Add64 => 0b10001011001,
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ALUOp::Sub32 => 0b01001011001,
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ALUOp::Sub64 => 0b11001011001,
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ALUOp::AddS32 => 0b00101011001,
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ALUOp::AddS64 => 0b10101011001,
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ALUOp::SubS32 => 0b01101011001,
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ALUOp::SubS64 => 0b11101011001,
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ALUOp::Add => 0b00001011001,
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ALUOp::Sub => 0b01001011001,
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ALUOp::AddS => 0b00101011001,
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ALUOp::SubS => 0b01101011001,
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_ => unimplemented!("{:?}", alu_op),
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};
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let top11 = top11 | size.sf_bit() << 10;
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let bits_15_10 = u32::from(extendop.bits()) << 3;
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sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
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}
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@@ -1394,7 +1374,8 @@ impl MachInstEmit for Inst {
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// mvn x28, x28
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Inst::AluRRR {
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alu_op: ALUOp::And64,
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alu_op: ALUOp::And,
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size: OperandSize::Size64,
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rd: x28wr,
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rn: x27,
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rm: x26,
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@@ -1402,7 +1383,8 @@ impl MachInstEmit for Inst {
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.emit(sink, emit_info, state);
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Inst::AluRRR {
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alu_op: ALUOp::OrrNot64,
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alu_op: ALUOp::OrrNot,
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size: OperandSize::Size64,
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rd: x28wr,
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rn: xzr,
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rm: x28,
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@@ -1425,11 +1407,8 @@ impl MachInstEmit for Inst {
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};
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Inst::AluRRR {
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alu_op: if ty == I64 {
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ALUOp::SubS64
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} else {
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ALUOp::SubS32
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},
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alu_op: ALUOp::SubS,
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size: OperandSize::from_ty(ty),
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rd: writable_zero_reg(),
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rn: x27,
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rm: x26,
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@@ -1447,11 +1426,11 @@ impl MachInstEmit for Inst {
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_ => {
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// add/sub/and/orr/eor x28, x27, x26
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let alu_op = match op {
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AtomicRmwOp::Add => ALUOp::Add64,
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AtomicRmwOp::Sub => ALUOp::Sub64,
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AtomicRmwOp::And => ALUOp::And64,
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AtomicRmwOp::Or => ALUOp::Orr64,
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AtomicRmwOp::Xor => ALUOp::Eor64,
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AtomicRmwOp::Add => ALUOp::Add,
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AtomicRmwOp::Sub => ALUOp::Sub,
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AtomicRmwOp::And => ALUOp::And,
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AtomicRmwOp::Or => ALUOp::Orr,
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AtomicRmwOp::Xor => ALUOp::Eor,
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AtomicRmwOp::Nand
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| AtomicRmwOp::Umin
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| AtomicRmwOp::Umax
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@@ -1462,6 +1441,7 @@ impl MachInstEmit for Inst {
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Inst::AluRRR {
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alu_op,
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size: OperandSize::Size64,
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rd: x28wr,
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rn: x27,
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rm: x26,
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@@ -2478,7 +2458,8 @@ impl MachInstEmit for Inst {
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// than AND on smaller cores.
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let imml = ImmLogic::maybe_from_u64(1, I32).unwrap();
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Inst::AluRRImmLogic {
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alu_op: ALUOp::And32,
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alu_op: ALUOp::And,
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size: OperandSize::Size32,
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rd,
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rn,
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imml,
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@@ -2655,7 +2636,8 @@ impl MachInstEmit for Inst {
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inst.emit(sink, emit_info, state);
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// Add base of jump table to jump-table-sourced block offset
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let inst = Inst::AluRRR {
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alu_op: ALUOp::Add64,
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alu_op: ALUOp::Add,
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size: OperandSize::Size64,
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rd: rtmp1,
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rn: rtmp1.to_reg(),
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rm: rtmp2.to_reg(),
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@@ -2731,15 +2713,12 @@ impl MachInstEmit for Inst {
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} else {
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offset as u64
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};
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let alu_op = if offset < 0 {
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ALUOp::Sub64
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} else {
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ALUOp::Add64
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};
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let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
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if let Some((idx, extendop)) = index_reg {
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let add = Inst::AluRRRExtend {
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alu_op: ALUOp::Add64,
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alu_op: ALUOp::Add,
|
||||
size: OperandSize::Size64,
|
||||
rd,
|
||||
rn: reg,
|
||||
rm: idx,
|
||||
@@ -2756,6 +2735,7 @@ impl MachInstEmit for Inst {
|
||||
} else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
|
||||
let add = Inst::AluRRImm12 {
|
||||
alu_op,
|
||||
size: OperandSize::Size64,
|
||||
rd,
|
||||
rn: reg,
|
||||
imm12,
|
||||
@@ -2775,6 +2755,7 @@ impl MachInstEmit for Inst {
|
||||
}
|
||||
let add = Inst::AluRRR {
|
||||
alu_op,
|
||||
size: OperandSize::Size64,
|
||||
rd,
|
||||
rn: reg,
|
||||
rm: tmp.to_reg(),
|
||||
|
||||
Reference in New Issue
Block a user