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[AArch64] Cleanup dynamic lowering (#4432)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-07-18 19:13:16 +01:00
committed by GitHub
parent d792646677
commit e5678e8f8d
2 changed files with 3 additions and 12 deletions
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9
cranelift/codegen/src/isa/aarch64/lower.isle
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@@ -81,9 +81,6 @@
(rule (lower (has_type ty @ (multi_lane _ _) (iadd x y))) (rule (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
(add_vec x y (vector_size ty))) (add_vec x y (vector_size ty)))
(rule (lower (has_type ty @ (dynamic_lane _ _) (iadd x y)))
(value_reg (vec_rrr (VecALUOp.Add) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;; `i128` ;; `i128`
(rule (lower (has_type $I128 (iadd x y))) (rule (lower (has_type $I128 (iadd x y)))
(let (let
@@ -199,8 +196,6 @@
;; vectors ;; vectors
(rule (lower (has_type ty @ (multi_lane _ _) (isub x y))) (rule (lower (has_type ty @ (multi_lane _ _) (isub x y)))
(sub_vec x y (vector_size ty))) (sub_vec x y (vector_size ty)))
(rule (lower (has_type ty @ (dynamic_lane _ _) (isub x y)))
(value_reg (sub_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
;; `i128` ;; `i128`
(rule (lower (has_type $I128 (isub x y))) (rule (lower (has_type $I128 (isub x y)))
@@ -288,10 +283,6 @@
(rule (lower (has_type (ty_vec128 ty @ (not_i64x2)) (imul x y))) (rule (lower (has_type (ty_vec128 ty @ (not_i64x2)) (imul x y)))
(mul x y (vector_size ty))) (mul x y (vector_size ty)))
;; Case for 'dynamic' i8x16, i16x8, and i32x4.
(rule (lower (has_type ty @ (dynamic_lane _ _) (imul x y)))
(value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;; Special lowering for i64x2. ;; Special lowering for i64x2.
;; ;;
;; This I64X2 multiplication is performed with several 32-bit ;; This I64X2 multiplication is performed with several 32-bit

6
cranelift/codegen/src/isa/aarch64/lower_dynamic_neon.isle
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@@ -1,17 +1,17 @@
;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (iadd x y))) (rule (lower (has_type ty @ (dynamic_lane _ _) (iadd x y)))
(value_reg (vec_rrr (VecALUOp.Add) (put_in_reg x) (put_in_reg y) (vector_size ty)))) (value_reg (add_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (isub x y))) (rule (lower (has_type ty @ (dynamic_lane _ _) (isub x y)))
(value_reg (vec_rrr (VecALUOp.Sub) (put_in_reg x) (put_in_reg y) (vector_size ty)))) (value_reg (sub_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (lane_fits_in_32 ty @ (dynamic_lane _ _)) (imul x y))) (rule (lower (has_type (lane_fits_in_32 ty @ (dynamic_lane _ _)) (imul x y)))
(value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty)))) (value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fadd x y))) (rule (lower (has_type ty @ (dynamic_lane _ _) (fadd x y)))
(value_reg (vec_rrr (VecALUOp.Fadd) (put_in_reg x) (put_in_reg y) (vector_size ty)))) (value_reg (vec_rrr (VecALUOp.Fadd) (put_in_reg x) (put_in_reg y) (vector_size ty))))