Add some signed int to float conversions.

These map to single Intel instructions.

The i64 to float conversions are not tested yet. The encoding tables
can't yet differentiate instructions on a secondary type variable alone.

cranelift/filetests/isa/intel/binary32-float.cton

@@ -0,0 +1,34 @@
+; Binary emission of 32-bit floating point code.
+test binemit
+isa intel has_sse2
+
+; The binary encodings can be verified with the command:
+;
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32-float.cton | llvm-mc -show-encoding -triple=i386
+;
+
+function %F32() {
+ebb0:
+    [-,%rcx]            v0 = iconst.i32 1
+    [-,%rsi]            v1 = iconst.i32 2
+
+    ; asm: cvtsi2ss %ecx, %xmm5
+    [-,%xmm5]           v10 = fcvt_from_sint.f32 v0             ; bin: f3 0f 2a e9
+    ; asm: cvtsi2ss %esi, %xmm2
+    [-,%xmm2]           v11 = fcvt_from_sint.f32 v1             ; bin: f3 0f 2a d6
+
+    return
+}
+
+function %F64() {
+ebb0:
+    [-,%rcx]            v0 = iconst.i32 1
+    [-,%rsi]            v1 = iconst.i32 2
+
+    ; asm: cvtsi2sd %ecx, %xmm5
+    [-,%xmm5]           v10 = fcvt_from_sint.f64 v0             ; bin: f2 0f 2a e9
+    ; asm: cvtsi2sd %esi, %xmm2
+    [-,%xmm2]           v11 = fcvt_from_sint.f64 v1             ; bin: f2 0f 2a d6
+
+    return
+}

cranelift/filetests/isa/intel/binary64-float.cton

@@ -0,0 +1,49 @@
+; Binary emission of 64-bit floating point code.
+test binemit
+set is_64bit
+isa intel has_sse2
+
+; The binary encodings can be verified with the command:
+;
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
+;
+
+function %F32() {
+ebb0:
+    [-,%r11]            v0 = iconst.i32 1
+    [-,%rsi]            v1 = iconst.i32 2
+    [-,%rax]            v2 = iconst.i64 11
+    [-,%r14]            v3 = iconst.i64 12
+
+    ; asm: cvtsi2ssl %r11d, %xmm5
+    [-,%xmm5]           v10 = fcvt_from_sint.f32 v0             ; bin: f3 41 0f 2a eb
+    ; asm: cvtsi2ssl %esi, %xmm10
+    [-,%xmm10]          v11 = fcvt_from_sint.f32 v1             ; bin: f3 44 0f 2a d6
+
+    ; asm: cvtsi2ssq %rax, %xmm5
+    [-,%xmm5]           v12 = fcvt_from_sint.f32 v2             ; TODO: f3 48 0f 2a e8
+    ; asm: cvtsi2ssq %r14, %xmm10
+    [-,%xmm10]          v13 = fcvt_from_sint.f32 v3             ; TODO: f3 4d 0f 2a d6
+
+    return
+}
+
+function %F64() {
+ebb0:
+    [-,%r11]            v0 = iconst.i32 1
+    [-,%rsi]            v1 = iconst.i32 2
+    [-,%rax]            v2 = iconst.i64 11
+    [-,%r14]            v3 = iconst.i64 12
+
+    ; asm: cvtsi2sdl %r11d, %xmm5
+    [-,%xmm5]           v10 = fcvt_from_sint.f64 v0             ; bin: f2 41 0f 2a eb
+    ; asm: cvtsi2sdl %esi, %xmm10
+    [-,%xmm10]          v11 = fcvt_from_sint.f64 v1             ; bin: f2 44 0f 2a d6
+
+    ; asm: cvtsi2sdq %rax, %xmm5
+    [-,%xmm5]           v12 = fcvt_from_sint.f64 v2             ; TODO: f2 48 0f 2a e8
+    ; asm: cvtsi2sdq %r14, %xmm10
+    [-,%xmm10]          v13 = fcvt_from_sint.f64 v3             ; TODO: f2 4d 0f 2a d6
+
+    return
+}

cranelift/filetests/wasm/conversions.cton

@@ -21,3 +21,29 @@ ebb0(v0: i32):
     v1 = uextend.i64 v0
     return v1
 }
+
+function %f32_convert_s_i32(i32) -> f32 {
+ebb0(v0: i32):
+    v1 = fcvt_from_sint.f32 v0
+    return v1
+}
+
+function %f64_convert_s_i32(i32) -> f64 {
+ebb0(v0: i32):
+    v1 = fcvt_from_sint.f64 v0
+    return v1
+}
+
+function %f32_convert_s_i64(i64) -> f32 {
+ebb0(v0: i64):
+    v1 = fcvt_from_sint.f32 v0
+    return v1
+}
+
+function %f64_convert_s_i64(i64) -> f64 {
+ebb0(v0: i64):
+    v1 = fcvt_from_sint.f64 v0
+    return v1
+}
+
+; TODO: f*_convert_u_i* (Don't exist on Intel).