Add extend-add-pairwise instructions x64
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@@ -2868,7 +2868,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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| Opcode::WideningPairwiseDotProductS
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| Opcode::SqmulRoundSat
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| Opcode::FvpromoteLow
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| Opcode::Fvdemote => {
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| Opcode::Fvdemote
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| Opcode::ExtendedPairwiseAddSigned
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| Opcode::ExtendedPairwiseAddUnsigned => {
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// TODO
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unimplemented!("Vector ops not implemented.");
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}
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