Add primitive bvult, bvzeroext; Add semantics for bextend, icmp (partial - only for <) iadd_cout
This commit is contained in:
committed by
Jakob Stoklund Olesen
parent
3fd43fd006
commit
e346bd50c8
@@ -1,7 +1,8 @@
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from __future__ import absolute_import
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from __future__ import absolute_import
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from semantics.primitives import prim_to_bv, prim_from_bv, bvsplit, bvconcat,\
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from semantics.primitives import prim_to_bv, prim_from_bv, bvsplit, bvconcat,\
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bvadd
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bvadd, bvult, bvzeroext
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from .instructions import vsplit, vconcat, iadd
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from .instructions import vsplit, vconcat, iadd, iadd_cout, icmp, bextend
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from .immediates import intcc
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from cdsl.xform import Rtl
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from cdsl.xform import Rtl
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from cdsl.ast import Var
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from cdsl.ast import Var
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from cdsl.typevar import TypeSet
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from cdsl.typevar import TypeSet
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@@ -10,6 +11,9 @@ from cdsl.ti import InTypeset
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x = Var('x')
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x = Var('x')
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y = Var('y')
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y = Var('y')
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a = Var('a')
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a = Var('a')
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b = Var('b')
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c_out = Var('c_out')
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bvc_out = Var('bvc_out')
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xhi = Var('xhi')
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xhi = Var('xhi')
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yhi = Var('yhi')
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yhi = Var('yhi')
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ahi = Var('ahi')
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ahi = Var('ahi')
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@@ -21,6 +25,7 @@ hi = Var('hi')
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bvx = Var('bvx')
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bvx = Var('bvx')
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bvy = Var('bvy')
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bvy = Var('bvy')
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bva = Var('bva')
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bva = Var('bva')
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bva_wide = Var('bva_wide')
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bvlo = Var('bvlo')
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bvlo = Var('bvlo')
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bvhi = Var('bvhi')
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bvhi = Var('bvhi')
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@@ -56,3 +61,42 @@ iadd.set_semantics(
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alo << iadd(xlo, ylo),
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alo << iadd(xlo, ylo),
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ahi << iadd(xhi, yhi),
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ahi << iadd(xhi, yhi),
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a << vconcat(alo, ahi)))
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a << vconcat(alo, ahi)))
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iadd_cout.set_semantics(
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(a, c_out) << iadd_cout(x, y),
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Rtl(
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bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bva << bvadd(bvx, bvy),
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bvc_out << bvult(bva, bvx),
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a << prim_from_bv(bva),
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c_out << prim_from_bv(bvc_out)
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))
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bextend.set_semantics(
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a << bextend(x),
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(Rtl(
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bvx << prim_to_bv(x),
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bvy << bvzeroext(bvx),
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a << prim_from_bv(bvy)
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl((xlo, xhi) << vsplit(x),
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alo << bextend(xlo),
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ahi << bextend(xhi),
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a << vconcat(alo, ahi)))
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icmp.set_semantics(
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a << icmp(intcc.ult, x, y),
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(Rtl(
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bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bva << bvult(bvx, bvy),
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bva_wide << bvzeroext(bva),
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a << prim_from_bv(bva_wide),
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl((xlo, xhi) << vsplit(x),
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(ylo, yhi) << vsplit(y),
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alo << icmp(intcc.ult, xlo, ylo),
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ahi << icmp(intcc.ult, xhi, yhi),
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b << vconcat(alo, ahi),
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a << bextend(b)))
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@@ -9,11 +9,13 @@ from __future__ import absolute_import
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from cdsl.operands import Operand
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from cdsl.operands import Operand
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from cdsl.typevar import TypeVar
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from cdsl.typevar import TypeVar
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from cdsl.instructions import Instruction, InstructionGroup
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from cdsl.instructions import Instruction, InstructionGroup
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from cdsl.ti import WiderOrEq
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import base.formats # noqa
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import base.formats # noqa
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GROUP = InstructionGroup("primitive", "Primitive instruction set")
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GROUP = InstructionGroup("primitive", "Primitive instruction set")
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BV = TypeVar('BV', 'A bitvector type.', bitvecs=True)
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BV = TypeVar('BV', 'A bitvector type.', bitvecs=True)
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BV1 = TypeVar('BV1', 'A single bit bitvector.', bitvecs=(1, 1))
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Real = TypeVar('Real', 'Any real type.', ints=True, floats=True,
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Real = TypeVar('Real', 'Any real type.', ints=True, floats=True,
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bools=True, simd=True)
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bools=True, simd=True)
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@@ -66,4 +68,18 @@ bvadd = Instruction(
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""",
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""",
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ins=(x, y), outs=a)
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ins=(x, y), outs=a)
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# Bitvector comparisons
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cmp_res = Operand('cmp_res', BV1, doc="Single bit boolean")
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bvult = Instruction(
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'bvult', r"""Unsigned bitvector comparison""",
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ins=(x, y), outs=cmp_res)
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# Extensions
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ToBV = TypeVar('ToBV', 'A bitvector type.', bitvecs=True)
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x1 = Operand('x1', ToBV, doc="")
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bvzeroext = Instruction(
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'bvzeroext', r"""Unsigned bitvector extension""",
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ins=x, outs=x1, constraints=WiderOrEq(ToBV, BV))
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GROUP.close()
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GROUP.close()
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