From e2b2b520ebabeccc1485a9e4c5d6f6697f55a578 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 30 Aug 2019 19:07:39 +0200 Subject: [PATCH] Fix compilation --- cranelift/codegen/meta/src/isa/x86/encodings.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs index 1739ed3ab7..253491f01c 100644 --- a/cranelift/codegen/meta/src/isa/x86/encodings.rs +++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs @@ -1776,7 +1776,7 @@ pub(crate) fn define( insertlane_mapping.insert(32, (vec![0x66, 0x0f, 0x3a, 0x22], Some(use_sse41_simd))); // PINSRD insertlane_mapping.insert(64, (vec![0x66, 0x0f, 0x3a, 0x22], Some(use_sse41_simd))); // PINSRQ, only x86_64 - for ty in ValueType::all_lane_types() { + for ty in ValueType::all_lane_types().filter(allowed_simd_type) { if let Some((opcode, isap)) = insertlane_mapping.get(&ty.lane_bits()) { let instruction = insertlane.bind_vector_from_lane(ty, sse_vector_size); let template = rec_r_ib_unsigned_r.opcodes(opcode.clone()); @@ -1797,7 +1797,7 @@ pub(crate) fn define( extractlane_mapping.insert(32, (vec![0x66, 0x0f, 0x3a, 0x16], Some(use_sse41_simd))); // PEXTRD extractlane_mapping.insert(64, (vec![0x66, 0x0f, 0x3a, 0x16], Some(use_sse41_simd))); // PEXTRQ, only x86_64 - for ty in ValueType::all_lane_types() { + for ty in ValueType::all_lane_types().filter(allowed_simd_type) { if let Some((opcode, isap)) = extractlane_mapping.get(&ty.lane_bits()) { let instruction = extractlane.bind_vector_from_lane(ty, sse_vector_size); let template = rec_r_ib_unsigned_gpr.opcodes(opcode.clone());