Define register banks.

Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.

lib/cretonne/meta/isa/riscv/registers.py

@@ -0,0 +1,18 @@
+"""
+RISC-V register banks.
+"""
+from __future__ import absolute_import
+from cdsl.registers import RegBank
+from .defs import ISA
+
+
+# We include `x0`, a.k.a `zero` in the register bank. It will be reserved.
+IntRegs = RegBank(
+        'IntRegs', ISA,
+        'General purpose registers',
+        units=32, prefix='x')
+
+FloatRegs = RegBank(
+        'FloatRegs', ISA,
+        'Floating point registers',
+        units=32, prefix='f')