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[AArch64] Refactor ALUOp3 (#3950)

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As well as adding generic pattern for msub along with runtests
for madd and msub.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-04-14 20:16:56 +01:00
committed by GitHub
parent 51d82aebfd
commit e142f587a7
9 changed files with 699 additions and 487 deletions
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12
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -995,7 +995,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::AluRRRR {
alu_op: ALUOp3::MAdd32,
alu_op: ALUOp3::MAdd,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -1006,7 +1007,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp3::MAdd64,
alu_op: ALUOp3::MAdd,
size: OperandSize::Size64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -1017,7 +1019,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp3::MSub32,
alu_op: ALUOp3::MSub,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
@@ -1028,7 +1031,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::AluRRRR {
alu_op: ALUOp3::MSub64,
alu_op: ALUOp3::MSub,
size: OperandSize::Size64,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),