T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[AArch64] Refactor ALUOp3 (#3950)

Browse Source 
As well as adding generic pattern for msub along with runtests
for madd and msub.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-04-14 20:16:56 +01:00
committed by GitHub
parent 51d82aebfd
commit e142f587a7
9 changed files with 699 additions and 487 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -758,6 +758,7 @@ impl MachInstEmit for Inst {
}
&Inst::AluRRRR {
alu_op,
size,
rd,
rm,
rn,
@@ -769,11 +770,10 @@ impl MachInstEmit for Inst {
let ra = allocs.next(ra);
let (top11, bit15) = match alu_op {
ALUOp3::MAdd32 => (0b0_00_11011_000, 0),
ALUOp3::MSub32 => (0b0_00_11011_000, 1),
ALUOp3::MAdd64 => (0b1_00_11011_000, 0),
ALUOp3::MSub64 => (0b1_00_11011_000, 1),
ALUOp3::MAdd => (0b0_00_11011_000, 0),
ALUOp3::MSub => (0b0_00_11011_000, 1),
};
let top11 = top11 | size.sf_bit() << 10;
sink.put4(enc_arith_rrrr(top11, rm, bit15, ra, rn, rd));
}
&Inst::AluRRImm12 {