Fix the order of the rex2 registers for r_ib_unsigned_gpr (#1424)

Fixes #1423

cranelift/codegen/meta/src/isa/x86/recipes.rs

@@ -1008,7 +1008,7 @@ pub(crate) fn define<'shared>(
                 ))
                 .emit(
                     r#"
-                    {{PUT_OP}}(bits, rex2(in_reg0, out_reg0), sink);
+                    {{PUT_OP}}(bits, rex2(out_reg0, in_reg0), sink);
                     modrm_rr(out_reg0, in_reg0, sink); // note the flipped register in the ModR/M byte
                     let imm:i64 = lane.into();
                     sink.put1(imm as u8);

cranelift/filetests/filetests/isa/x86/simd-pextr-binemit.clif

@@ -0,0 +1,22 @@
+test binemit
+set enable_simd
+target x86_64 haswell
+
+function u0:0(i64 fp [%rbp]) -> i32 [%rax], i64 fp [%rbp] system_v {
+    ss0 = explicit_slot 32, offset -48
+    ss1 = spill_slot 16, offset -64
+    ss2 = incoming_arg 16, offset -16
+    sig0 = () system_v
+    fn0 = colocated u0:2 sig0
+
+block0(v5: i64 [%rbp]):
+[-]        x86_push v5
+[-]        copy_special %rsp -> %rbp
+[-]        adjust_sp_down_imm 48
+[-,%rax]   v0 = stack_addr.i64 ss0
+[-,%xmm15] v4 = load.i32x4 v0
+[-,%rax]   v2 = x86_pextr v4, 1 ; bin: 66 44 0f 3a 16 f8 01
+[-]        adjust_sp_up_imm 48
+[-]        v6 = x86_pop.i64
+[-]        return v2, v6
+}