Fix the order of the rex2 registers for r_ib_unsigned_gpr (#1424)

Fixes #1423
2020-03-27 22:29:32 +01:00
parent 9d40e1072a
commit dfe22836e8
2 changed files with 23 additions and 1 deletions
--- a/cranelift/codegen/meta/src/isa/x86/recipes.rs
+++ b/cranelift/codegen/meta/src/isa/x86/recipes.rs
@@ -1008,7 +1008,7 @@ pub(crate) fn define<'shared>(
                ))
                .emit(
                    r#"
-                    {{PUT_OP}}(bits, rex2(in_reg0, out_reg0), sink);
+                    {{PUT_OP}}(bits, rex2(out_reg0, in_reg0), sink);
                    modrm_rr(out_reg0, in_reg0, sink); // note the flipped register in the ModR/M byte
                    let imm:i64 = lane.into();
                    sink.put1(imm as u8);