Remove MachInst::gen_constant (#5427)

* aarch64: constant generation cleanup

Add support for MOVZ and MOVN generation via ISLE.
Handle f32const, f64const, and nop instructions via ISLE.
No longer call Inst::gen_constant from lower.rs.

* riscv64: constant generation cleanup

Handle f32const, f64const, and nop instructions via ISLE.

* s390x: constant generation cleanup

Fix rule priorities for "imm" term.
Only handle 32-bit stack offsets; no longer use load_constant64.

* x64: constant generation cleanup

No longer call Inst::gen_constant from lower.rs or abi.rs.

* Refactor LowerBackend::lower to return InstOutput

No longer write to the per-insn output registers; instead, return
an InstOutput vector of temp registers holding the outputs.

This will allow calling LowerBackend::lower multiple times for
the same instruction, e.g. to rematerialize constants.

When emitting the primary copy of the instruction during lowering,
writing to the per-insn registers is now done in lower_clif_block.

As a result, the ISLE lower_common routine is no longer needed.
In addition, the InsnOutput type and all code related to it
can be removed as well.

* Refactor IsleContext to hold a LowerBackend reference

Remove the "triple", "flags", and "isa_flags" fields that are
copied from LowerBackend to each IsleContext, and instead just
hold a reference to LowerBackend in IsleContext.

This will allow calling LowerBackend::lower from within callbacks
in src/machinst/isle.rs, e.g. to rematerialize constants.

To avoid having to pass LowerBackend references through multiple
functions, eliminate the lower_insn_to_regs subroutines in those
targets that still have them, and just inline into the main
lower routine.  This also eliminates lower_inst.rs on aarch64
and riscv64.

Replace all accesses to the removed IsleContext fields by going
through the LowerBackend reference.

* Remove MachInst::gen_constant

This addresses the problem described in issue
https://github.com/bytecodealliance/wasmtime/issues/4426
that targets currently have to duplicate code to emit
constants between the ISLE logic and the gen_constant
callback.

After the various cleanups in earlier patches in this series,
the only remaining user of get_constant is put_value_in_regs
in Lower.  This can now be removed, and instead constant
rematerialization can be performed in the put_in_regs ISLE
callback by simply directly calling LowerBackend::lower
on the instruction defining the constant (using a different
output register).

Since the check for egraph mode is now no longer performed in
put_value_in_regs, the Lower::flags member becomes obsolete.

Care needs to be taken that other calls directly to the
Lower::put_value_in_regs routine now handle the fact that
no more rematerialization is performed.  All such calls in
target code already historically handle constants themselves.
The remaining call site in the ISLE gen_call_common helper
can be redirected to the ISLE put_in_regs callback.

The existing target implementations of gen_constant are then
unused and can be removed.  (In some target there may still
be further opportunities to remove duplication between ISLE
and some local Rust code - this can be left to future patches.)

cranelift/filetests/filetests/isa/aarch64/arithmetic.clif

@@ -97,7 +97,7 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x2, xzr, #2
+;   movz x2, #2
 ;   udiv x0, x0, x2
 ;   ret
 
@@ -176,7 +176,7 @@ block0(v0: i32):
 
 ; block0:
 ;   mov w2, w0
-;   orr w4, wzr, #2
+;   movz w4, #2
 ;   udiv x0, x2, x4
 ;   ret
 
@@ -474,7 +474,7 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x2, xzr, #2
+;   movz x2, #2
 ;   udiv x4, x0, x2
 ;   msub x0, x4, x2, x0
 ;   ret

cranelift/filetests/filetests/isa/aarch64/bitops.clif

@@ -111,7 +111,7 @@ block0(v0: i128):
 ;   clz x5, x0
 ;   lsr x7, x3, #6
 ;   madd x0, x5, x7, x3
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %c(i8) -> i8 {
@@ -173,7 +173,7 @@ block0(v0: i128):
 ;   subs xzr, x5, #63
 ;   csel x14, x11, xzr, eq
 ;   add x0, x14, x5
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %d(i8) -> i8 {
@@ -235,7 +235,7 @@ block0(v0: i128):
 ;   clz x9, x5
 ;   lsr x11, x7, #6
 ;   madd x0, x9, x11, x7
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %d(i128) -> i128 {
@@ -250,7 +250,7 @@ block0(v0: i128):
 ;   cnt v7.16b, v4.16b
 ;   addv b17, v7.16b
 ;   umov w0, v17.b[0]
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %d(i64) -> i64 {
@@ -312,7 +312,7 @@ block0:
 }
 
 ; block0:
-;   movn x0, #0
+;   movz w0, #255
 ;   sxtb w0, w0
 ;   ret
 
@@ -324,7 +324,7 @@ block0:
 }
 
 ; block0:
-;   movn x0, #0
+;   movz w0, #255
 ;   sxtb w0, w0
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/bti.clif

@@ -35,25 +35,25 @@ block5(v5: i32):
 ;   subs wzr, w0, #3
 ;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
-;   movz x5, #4
+;   movz w5, #4
 ;   b label2
 ; block2:
 ;   b label9
 ; block3:
 ;   bti j
-;   movz x5, #1
+;   movz w5, #1
 ;   b label4
 ; block4:
 ;   b label9
 ; block5:
 ;   bti j
-;   movz x5, #2
+;   movz w5, #2
 ;   b label6
 ; block6:
 ;   b label9
 ; block7:
 ;   bti j
-;   movz x5, #3
+;   movz w5, #3
 ;   b label8
 ; block8:
 ;   b label9

cranelift/filetests/filetests/isa/aarch64/call.clif

@@ -82,14 +82,14 @@ block0(v0: i8):
 ;   mov x8, x0
 ;   sub sp, sp, #16
 ;   virtual_sp_offset_adjust 16
-;   movz x0, #42
-;   movz x1, #42
-;   movz x2, #42
-;   movz x3, #42
-;   movz x4, #42
-;   movz x5, #42
-;   movz x6, #42
-;   movz x7, #42
+;   movz w0, #42
+;   movz w1, #42
+;   movz w2, #42
+;   movz w3, #42
+;   movz w4, #42
+;   movz w5, #42
+;   movz w6, #42
+;   movz w7, #42
 ;   strb w8, [sp]
 ;   ldr x8, 8 ; b 12 ; data TestCase(%g) + 0
 ;   blr x8
@@ -107,14 +107,14 @@ block0(v0: i8):
 ; block0:
 ;   mov x9, x0
 ;   mov x8, x1
-;   movz x0, #42
-;   movz x1, #42
-;   movz x2, #42
-;   movz x3, #42
-;   movz x4, #42
-;   movz x5, #42
-;   movz x6, #42
-;   movz x7, #42
+;   movz w0, #42
+;   movz w1, #42
+;   movz w2, #42
+;   movz w3, #42
+;   movz w4, #42
+;   movz w5, #42
+;   movz w6, #42
+;   movz w7, #42
 ;   strb w9, [x8]
 ;   ret
 
@@ -442,8 +442,8 @@ block0:
 
 ; block0:
 ;   mov x6, x0
-;   movz x0, #0
-;   movz x4, #1
+;   movz w0, #0
+;   movz w4, #1
 ;   str w4, [x6]
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/condbr.clif

@@ -370,7 +370,7 @@ block1:
 ;   subs xzr, x1, x3
 ;   cset x9, ls
 ;   csel x11, x6, x9, eq
-;   orr x13, xzr, #1
+;   movz x13, #1
 ;   subs xzr, x13, x11
 ;   b.ls label1 ; b label2
 ; block1:
@@ -472,7 +472,7 @@ block1:
 ;   subs xzr, x1, x3
 ;   cset x9, hs
 ;   csel x11, x6, x9, eq
-;   orr x13, xzr, #1
+;   movz x13, #1
 ;   subs xzr, x11, x13
 ;   b.hs label1 ; b label2
 ; block1:

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -287,7 +287,7 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -304,7 +304,7 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -321,7 +321,7 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -338,7 +338,7 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -355,7 +355,7 @@ block0(v0: i128, v1: i128, v2: i128):
 
 ; block0:
 ;   movz x9, #42
-;   movz w11, #0
+;   movz x11, #0
 ;   subs xzr, x0, x9
 ;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
@@ -667,7 +667,7 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -685,7 +685,7 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -703,7 +703,7 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -721,7 +721,7 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; block0:
 ;   movz x6, #42
-;   movz w8, #0
+;   movz x8, #0
 ;   subs xzr, x0, x6
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
@@ -739,7 +739,7 @@ block0(v0: i128, v1: i128, v2: i128):
 
 ; block0:
 ;   movz x9, #42
-;   movz w11, #0
+;   movz x11, #0
 ;   subs xzr, x0, x9
 ;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq

cranelift/filetests/filetests/isa/aarch64/constants.clif

@@ -9,7 +9,7 @@ block0:
 }
 
 ; block0:
-;   movn x0, #0
+;   movz w0, #255
 ;   ret
 
 function %f() -> i16 {
@@ -19,7 +19,7 @@ block0:
 }
 
 ; block0:
-;   movz x0, #0
+;   movz w0, #0
 ;   ret
 
 function %f() -> i64 {
@@ -164,7 +164,7 @@ block0:
 }
 
 ; block0:
-;   movn x0, #0
+;   movn w0, #0
 ;   ret
 
 function %f() -> i32 {

cranelift/filetests/filetests/isa/aarch64/extend-op.clif

@@ -33,7 +33,7 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i128_sextend_i64(i64) -> i128 {
@@ -54,7 +54,7 @@ block0(v0: i32):
 
 ; block0:
 ;   mov w0, w0
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i128_sextend_i32(i32) -> i128 {
@@ -76,7 +76,7 @@ block0(v0: i16):
 
 ; block0:
 ;   uxth w0, w0
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i128_sextend_i16(i16) -> i128 {
@@ -98,7 +98,7 @@ block0(v0: i8):
 
 ; block0:
 ;   uxtb w0, w0
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i128_sextend_i8(i8) -> i128 {
@@ -154,7 +154,7 @@ block0(v0: i8x16):
 
 ; block0:
 ;   umov w0, v0.b[1]
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i8x16_sextend_i16(i8x16) -> i16 {
@@ -233,7 +233,7 @@ block0(v0: i16x8):
 
 ; block0:
 ;   umov w0, v0.h[1]
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i16x8_sextend_i32(i16x8) -> i32 {
@@ -290,7 +290,7 @@ block0(v0: i32x4):
 
 ; block0:
 ;   mov w0, v0.s[1]
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i32x4_sextend_i64(i32x4) -> i64 {
@@ -325,7 +325,7 @@ block0(v0: i64x2):
 
 ; block0:
 ;   mov x0, v0.d[1]
-;   movz w1, #0
+;   movz x1, #0
 ;   ret
 
 function %i64x2_sextend_i128(i64x2) -> i128 {

cranelift/filetests/filetests/isa/aarch64/heap_addr.clif

@@ -79,7 +79,7 @@ block0(v0: i64, v1: i32):
 ;   mov w8, w1
 ;   add x9, x0, x1, UXTW
 ;   add x9, x9, #16
-;   movz w6, #65512
+;   movz x6, #65512
 ;   movz x10, #0
 ;   subs xzr, x8, x6
 ;   csel x0, x10, x9, hi

cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif

@@ -14,9 +14,9 @@ block0:
 }
 
 ; block0:
-;   movz x0, #56780
+;   movz w0, #56780
 ;   uxth w2, w0
-;   movz x4, #56780
+;   movz w4, #56780
 ;   subs wzr, w2, w4, UXTH
 ;   cset x0, ne
 ;   ret

cranelift/filetests/filetests/isa/aarch64/jumptable.clif

@@ -34,22 +34,22 @@ block5(v5: i32):
 ;   subs wzr, w0, #3
 ;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
-;   movz x5, #4
+;   movz w5, #4
 ;   b label2
 ; block2:
 ;   b label9
 ; block3:
-;   movz x5, #1
+;   movz w5, #1
 ;   b label4
 ; block4:
 ;   b label9
 ; block5:
-;   movz x5, #2
+;   movz w5, #2
 ;   b label6
 ; block6:
 ;   b label9
 ; block7:
-;   movz x5, #3
+;   movz w5, #3
 ;   b label8
 ; block8:
 ;   b label9

cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif

@@ -13,7 +13,7 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x5, xzr, #128
+;   movz x5, #128
 ;   sub x7, x5, x2
 ;   lsr x9, x0, x2
 ;   lsr x11, x1, x2
@@ -96,7 +96,7 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x5, xzr, #128
+;   movz x5, #128
 ;   sub x7, x5, x2
 ;   lsl x9, x0, x2
 ;   lsl x11, x1, x2

cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif

@@ -162,7 +162,7 @@ block0:
 
 ; block0:
 ;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   movz x1, #1
+;   movz w1, #1
 ;   and w3, w1, #7
 ;   sub x5, xzr, x3
 ;   dup v7.16b, w5
@@ -191,7 +191,7 @@ block0(v0: i8x16, v1: i32):
 }
 
 ; block0:
-;   movz x3, #3
+;   movz w3, #3
 ;   and w5, w3, #7
 ;   sub x7, xzr, x5
 ;   dup v17.16b, w7

cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif

@@ -10,9 +10,9 @@ block0:
 }
 
 ; block0:
-;   movz x0, #1
-;   movk x0, x0, #1, LSL #48
-;   fmov d0, x0
+;   movz x1, #1
+;   movk x1, x1, #1, LSL #48
+;   fmov d0, x1
 ;   ret
 
 function %f2() -> i32x4 {
@@ -23,7 +23,7 @@ block0:
 }
 
 ; block0:
-;   movz x0, #42679
+;   movz w0, #42679
 ;   fmov s0, w0
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif

@@ -9,7 +9,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x2, #127
+;   movz w2, #127
 ;   adds w0, w0, w2
 ;   b.lo 8 ; udf
 ;   ret
@@ -22,7 +22,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x2, #127
+;   movz w2, #127
 ;   adds w0, w2, w0
 ;   b.lo 8 ; udf
 ;   ret

cranelift/filetests/filetests/isa/x64/branches.clif

@@ -307,17 +307,17 @@ block202:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movl    $1112539136, %r8d
-;   movd    %r8d, %xmm5
-;   ucomiss %xmm5, %xmm0
+;   movl    $1112539136, %edx
+;   movd    %edx, %xmm6
+;   ucomiss %xmm6, %xmm0
 ;   jp      label2
 ;   jnz     label2; j label1
 ; block1:
 ;   jmp     label5
 ; block2:
-;   movl    $1112539136, %esi
-;   movd    %esi, %xmm9
-;   ucomiss %xmm9, %xmm0
+;   movl    $1112539136, %r11d
+;   movd    %r11d, %xmm10
+;   ucomiss %xmm10, %xmm0
 ;   jnp     label3; j label4
 ; block3:
 ;   ud2 heap_oob