s390x: Add z14 support
* Add support for processor features (including auto-detection). * Move base architecture set requirement back to z14. * Add z15 feature sets and re-enable z15-specific code generation when required features are available.
This commit is contained in:
Ulrich Weigand
@@ -34,6 +34,18 @@ mod emit_tests;
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//=============================================================================
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// Instructions (top level): definition
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/// Supported instruction sets
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#[allow(non_camel_case_types)]
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#[derive(Debug)]
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pub(crate) enum InstructionSet {
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/// Baseline ISA for cranelift is z14.
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Base,
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/// Miscellaneous-Instruction-Extensions Facility 2 (z15)
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MIE2,
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/// Vector-Enhancements Facility 2 (z15)
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VXRS_EXT2,
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}
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/// An ALU operation. This can be paired with several instruction formats
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/// below (see `Inst`) in any combination.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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@@ -70,6 +82,17 @@ pub enum ALUOp {
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XorNot64,
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}
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impl ALUOp {
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pub(crate) fn available_from(&self) -> InstructionSet {
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match self {
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ALUOp::AndNot32 | ALUOp::AndNot64 => InstructionSet::MIE2,
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ALUOp::OrrNot32 | ALUOp::OrrNot64 => InstructionSet::MIE2,
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ALUOp::XorNot32 | ALUOp::XorNot64 => InstructionSet::MIE2,
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_ => InstructionSet::Base,
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}
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}
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum UnaryOp {
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Abs32,
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@@ -82,6 +105,15 @@ pub enum UnaryOp {
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PopcntReg,
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}
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impl UnaryOp {
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pub(crate) fn available_from(&self) -> InstructionSet {
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match self {
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UnaryOp::PopcntReg => InstructionSet::MIE2,
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_ => InstructionSet::Base,
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}
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}
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum ShiftOp {
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RotL32,
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@@ -941,18 +973,6 @@ pub enum Inst {
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},
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}
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fn count_zero_half_words(mut value: u64) -> usize {
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let mut count = 0;
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for _ in 0..4 {
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if value & 0xffff == 0 {
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count += 1;
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}
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value >>= 16;
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}
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count
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}
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#[test]
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fn inst_size_test() {
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// This test will help with unintentionally growing the size
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@@ -961,6 +981,135 @@ fn inst_size_test() {
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}
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impl Inst {
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/// Retrieve the ISA feature set in which the instruction is available.
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fn available_in_isa(&self) -> InstructionSet {
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match self {
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// These instructions are part of the baseline ISA for cranelift (z14)
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Inst::Nop0
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| Inst::Nop2
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| Inst::AluRRSImm16 { .. }
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| Inst::AluRR { .. }
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| Inst::AluRX { .. }
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| Inst::AluRSImm16 { .. }
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| Inst::AluRSImm32 { .. }
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| Inst::AluRUImm32 { .. }
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| Inst::AluRUImm16Shifted { .. }
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| Inst::AluRUImm32Shifted { .. }
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| Inst::ShiftRR { .. }
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| Inst::SMulWide { .. }
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| Inst::UMulWide { .. }
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| Inst::SDivMod32 { .. }
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| Inst::SDivMod64 { .. }
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| Inst::UDivMod32 { .. }
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| Inst::UDivMod64 { .. }
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| Inst::Flogr { .. }
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| Inst::CmpRR { .. }
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| Inst::CmpRX { .. }
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| Inst::CmpRSImm16 { .. }
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| Inst::CmpRSImm32 { .. }
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| Inst::CmpRUImm32 { .. }
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| Inst::CmpTrapRR { .. }
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| Inst::CmpTrapRSImm16 { .. }
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| Inst::CmpTrapRUImm16 { .. }
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| Inst::AtomicRmw { .. }
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| Inst::AtomicCas32 { .. }
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| Inst::AtomicCas64 { .. }
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| Inst::Fence
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| Inst::Load32 { .. }
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| Inst::Load32ZExt8 { .. }
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| Inst::Load32SExt8 { .. }
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| Inst::Load32ZExt16 { .. }
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| Inst::Load32SExt16 { .. }
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| Inst::Load64 { .. }
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| Inst::Load64ZExt8 { .. }
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| Inst::Load64SExt8 { .. }
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| Inst::Load64ZExt16 { .. }
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| Inst::Load64SExt16 { .. }
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| Inst::Load64ZExt32 { .. }
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| Inst::Load64SExt32 { .. }
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| Inst::LoadRev16 { .. }
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| Inst::LoadRev32 { .. }
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| Inst::LoadRev64 { .. }
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| Inst::Store8 { .. }
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| Inst::Store16 { .. }
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| Inst::Store32 { .. }
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| Inst::Store64 { .. }
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| Inst::StoreImm8 { .. }
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| Inst::StoreImm16 { .. }
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| Inst::StoreImm32SExt16 { .. }
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| Inst::StoreImm64SExt16 { .. }
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| Inst::StoreRev16 { .. }
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| Inst::StoreRev32 { .. }
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| Inst::StoreRev64 { .. }
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| Inst::LoadMultiple64 { .. }
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| Inst::StoreMultiple64 { .. }
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| Inst::Mov32 { .. }
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| Inst::Mov64 { .. }
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| Inst::Mov32Imm { .. }
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| Inst::Mov32SImm16 { .. }
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| Inst::Mov64SImm16 { .. }
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| Inst::Mov64SImm32 { .. }
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| Inst::Mov64UImm16Shifted { .. }
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| Inst::Mov64UImm32Shifted { .. }
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| Inst::Insert64UImm16Shifted { .. }
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| Inst::Insert64UImm32Shifted { .. }
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| Inst::Extend { .. }
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| Inst::CMov32 { .. }
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| Inst::CMov64 { .. }
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| Inst::CMov32SImm16 { .. }
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| Inst::CMov64SImm16 { .. }
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| Inst::FpuMove32 { .. }
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| Inst::FpuMove64 { .. }
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| Inst::FpuCMov32 { .. }
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| Inst::FpuCMov64 { .. }
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| Inst::MovToFpr { .. }
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| Inst::MovFromFpr { .. }
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| Inst::FpuRR { .. }
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| Inst::FpuRRR { .. }
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| Inst::FpuRRRR { .. }
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| Inst::FpuCopysign { .. }
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| Inst::FpuCmp32 { .. }
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| Inst::FpuCmp64 { .. }
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| Inst::FpuLoad32 { .. }
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| Inst::FpuStore32 { .. }
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| Inst::FpuLoad64 { .. }
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| Inst::FpuStore64 { .. }
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| Inst::LoadFpuConst32 { .. }
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| Inst::LoadFpuConst64 { .. }
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| Inst::FpuToInt { .. }
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| Inst::IntToFpu { .. }
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| Inst::FpuRound { .. }
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| Inst::FpuVecRRR { .. }
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| Inst::Call { .. }
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| Inst::CallInd { .. }
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| Inst::Ret { .. }
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| Inst::EpiloguePlaceholder
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| Inst::Jump { .. }
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| Inst::CondBr { .. }
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| Inst::TrapIf { .. }
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| Inst::OneWayCondBr { .. }
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| Inst::IndirectBr { .. }
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| Inst::Debugtrap
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| Inst::Trap { .. }
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| Inst::JTSequence { .. }
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| Inst::LoadExtNameFar { .. }
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| Inst::LoadAddr { .. }
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| Inst::VirtualSPOffsetAdj { .. }
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| Inst::ValueLabelMarker { .. }
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| Inst::Unwind { .. } => InstructionSet::Base,
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// These depend on the opcode
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Inst::AluRRR { alu_op, .. } => alu_op.available_from(),
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Inst::UnaryRR { op, .. } => op.available_from(),
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// These are all part of VXRS_EXT2
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Inst::FpuLoadRev32 { .. }
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| Inst::FpuStoreRev32 { .. }
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| Inst::FpuLoadRev64 { .. }
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| Inst::FpuStoreRev64 { .. } => InstructionSet::VXRS_EXT2,
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}
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}
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/// Create a 64-bit move instruction.
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pub fn mov64(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
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assert!(to_reg.to_reg().get_class() == from_reg.get_class());
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