Merge pull request #2985 from afonso360/aarch64-i128-load-store
aarch64: Implement I128 Loads and Stores
This commit is contained in:
Chris Fallin
@@ -692,6 +692,63 @@ fn collect_address_addends<C: LowerCtx<I = Inst>>(
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(result64, result32, offset)
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}
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/// Lower the address of a pair load or store.
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pub(crate) fn lower_pair_address<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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roots: &[InsnInput],
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offset: i32,
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) -> PairAMode {
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// Collect addends through an arbitrary tree of 32-to-64-bit sign/zero
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// extends and addition ops. We update these as we consume address
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// components, so they represent the remaining addends not yet handled.
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let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
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let offset = args_offset + (offset as i64);
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trace!(
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"lower_pair_address: addends64 {:?}, addends32 {:?}, offset {}",
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addends64,
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addends32,
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offset
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);
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// Pairs basically only have reg + imm formats so we only have to worry about those
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let base_reg = if let Some(reg64) = addends64.pop() {
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reg64
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} else if let Some((reg32, extendop)) = addends32.pop() {
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let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
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let signed = match extendop {
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ExtendOp::SXTW => true,
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ExtendOp::UXTW => false,
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_ => unreachable!(),
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};
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ctx.emit(Inst::Extend {
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rd: tmp,
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rn: reg32,
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signed,
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from_bits: 32,
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to_bits: 64,
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});
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tmp.to_reg()
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} else {
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zero_reg()
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};
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let addr = ctx.alloc_tmp(I64).only_reg().unwrap();
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ctx.emit(Inst::gen_move(addr, base_reg, I64));
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// We have the base register, if we have any others, we need to add them
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lower_add_addends(ctx, addr, addends64, addends32);
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// Figure out what offset we should emit
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let imm7 = SImm7Scaled::maybe_from_i64(offset, I64).unwrap_or_else(|| {
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lower_add_immediate(ctx, addr, addr.to_reg(), offset);
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SImm7Scaled::maybe_from_i64(0, I64).unwrap()
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});
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PairAMode::SignedOffset(addr.to_reg(), imm7)
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}
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/// Lower the address of a load or store.
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pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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@@ -792,36 +849,23 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
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// If there is any offset, load that first into `addr`, and add the `reg`
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// that we kicked out of the `AMode`; otherwise, start with that reg.
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if offset != 0 {
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// If we can fit offset or -offset in an imm12, use an add-imm
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// to combine the reg and offset. Otherwise, load value first then add.
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if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
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ctx.emit(Inst::AluRRImm12 {
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alu_op: ALUOp::Add64,
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rd: addr,
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rn: reg,
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imm12,
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});
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} else if let Some(imm12) = Imm12::maybe_from_u64(offset.wrapping_neg() as u64) {
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ctx.emit(Inst::AluRRImm12 {
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alu_op: ALUOp::Sub64,
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rd: addr,
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rn: reg,
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imm12,
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});
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} else {
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lower_constant_u64(ctx, addr, offset as u64);
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Add64,
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rd: addr,
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rn: addr.to_reg(),
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rm: reg,
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});
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}
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lower_add_immediate(ctx, addr, reg, offset)
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} else {
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ctx.emit(Inst::gen_move(addr, reg, I64));
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}
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// Now handle reg64 and reg32-extended components.
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lower_add_addends(ctx, addr, addends64, addends32);
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memarg
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}
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fn lower_add_addends<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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rd: Writable<Reg>,
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addends64: AddressAddend64List,
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addends32: AddressAddend32List,
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) {
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for reg in addends64 {
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// If the register is the stack reg, we must move it to another reg
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// before adding it.
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@@ -834,8 +878,8 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
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};
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Add64,
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rd: addr,
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rn: addr.to_reg(),
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rd,
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rn: rd.to_reg(),
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rm: reg,
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});
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}
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@@ -843,14 +887,42 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
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assert!(reg != stack_reg());
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ctx.emit(Inst::AluRRRExtend {
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alu_op: ALUOp::Add64,
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rd: addr,
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rn: addr.to_reg(),
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rd,
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rn: rd.to_reg(),
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rm: reg,
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extendop,
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});
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}
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}
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memarg
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/// Adds into `rd` a signed imm pattern matching the best instruction for it.
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// TODO: This function is duplicated in ctx.gen_add_imm
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fn lower_add_immediate<C: LowerCtx<I = Inst>>(ctx: &mut C, dst: Writable<Reg>, src: Reg, imm: i64) {
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// If we can fit offset or -offset in an imm12, use an add-imm
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// Otherwise, lower the constant first then add.
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if let Some(imm12) = Imm12::maybe_from_u64(imm as u64) {
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ctx.emit(Inst::AluRRImm12 {
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alu_op: ALUOp::Add64,
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rd: dst,
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rn: src,
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imm12,
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});
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} else if let Some(imm12) = Imm12::maybe_from_u64(imm.wrapping_neg() as u64) {
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ctx.emit(Inst::AluRRImm12 {
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alu_op: ALUOp::Sub64,
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rd: dst,
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rn: src,
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imm12,
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});
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} else {
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lower_constant_u64(ctx, dst, imm as u64);
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Add64,
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rd: dst,
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rn: dst.to_reg(),
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rm: src,
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});
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}
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}
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pub(crate) fn lower_constant_u64<C: LowerCtx<I = Inst>>(
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@@ -1248,7 +1320,10 @@ fn load_op_to_ty(op: Opcode) -> Option<Type> {
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/// Helper to lower a load instruction; this is used in several places, because
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/// a load can sometimes be merged into another operation.
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pub(crate) fn lower_load<C: LowerCtx<I = Inst>, F: FnMut(&mut C, Writable<Reg>, Type, AMode)>(
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pub(crate) fn lower_load<
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C: LowerCtx<I = Inst>,
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F: FnMut(&mut C, ValueRegs<Writable<Reg>>, Type, AMode),
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>(
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ctx: &mut C,
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ir_inst: IRInst,
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inputs: &[InsnInput],
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@@ -1261,7 +1336,7 @@ pub(crate) fn lower_load<C: LowerCtx<I = Inst>, F: FnMut(&mut C, Writable<Reg>,
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let off = ctx.data(ir_inst).load_store_offset().unwrap();
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let mem = lower_address(ctx, elem_ty, &inputs[..], off);
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let rd = get_output_reg(ctx, output).only_reg().unwrap();
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let rd = get_output_reg(ctx, output);
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f(ctx, rd, elem_ty, mem);
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}
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@@ -1303,56 +1303,71 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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.memflags(insn)
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.expect("Load instruction should have memflags");
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lower_load(
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ctx,
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insn,
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&inputs[..],
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outputs[0],
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|ctx, rd, elem_ty, mem| {
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let is_float = ty_has_float_or_vec_representation(elem_ty);
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ctx.emit(match (ty_bits(elem_ty), sign_extend, is_float) {
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(1, _, _) => Inst::ULoad8 { rd, mem, flags },
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(8, false, _) => Inst::ULoad8 { rd, mem, flags },
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(8, true, _) => Inst::SLoad8 { rd, mem, flags },
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(16, false, _) => Inst::ULoad16 { rd, mem, flags },
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(16, true, _) => Inst::SLoad16 { rd, mem, flags },
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(32, false, false) => Inst::ULoad32 { rd, mem, flags },
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(32, true, false) => Inst::SLoad32 { rd, mem, flags },
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(32, _, true) => Inst::FpuLoad32 { rd, mem, flags },
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(64, _, false) => Inst::ULoad64 { rd, mem, flags },
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// Note that we treat some of the vector loads as scalar floating-point loads,
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// which is correct in a little endian environment.
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(64, _, true) => Inst::FpuLoad64 { rd, mem, flags },
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(128, _, _) => Inst::FpuLoad128 { rd, mem, flags },
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_ => panic!("Unsupported size in load"),
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});
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let vec_extend = match op {
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Opcode::Sload8x8 => Some(VecExtendOp::Sxtl8),
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Opcode::Sload8x8Complex => Some(VecExtendOp::Sxtl8),
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Opcode::Uload8x8 => Some(VecExtendOp::Uxtl8),
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Opcode::Uload8x8Complex => Some(VecExtendOp::Uxtl8),
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Opcode::Sload16x4 => Some(VecExtendOp::Sxtl16),
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Opcode::Sload16x4Complex => Some(VecExtendOp::Sxtl16),
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Opcode::Uload16x4 => Some(VecExtendOp::Uxtl16),
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Opcode::Uload16x4Complex => Some(VecExtendOp::Uxtl16),
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Opcode::Sload32x2 => Some(VecExtendOp::Sxtl32),
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Opcode::Sload32x2Complex => Some(VecExtendOp::Sxtl32),
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Opcode::Uload32x2 => Some(VecExtendOp::Uxtl32),
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Opcode::Uload32x2Complex => Some(VecExtendOp::Uxtl32),
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_ => None,
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};
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if let Some(t) = vec_extend {
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ctx.emit(Inst::VecExtend {
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t,
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rd,
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rn: rd.to_reg(),
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high_half: false,
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let out_ty = ctx.output_ty(insn, 0);
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if out_ty == I128 {
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let off = ctx.data(insn).load_store_offset().unwrap();
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let mem = lower_pair_address(ctx, &inputs[..], off);
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let dst = get_output_reg(ctx, outputs[0]);
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ctx.emit(Inst::LoadP64 {
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rt: dst.regs()[0],
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rt2: dst.regs()[1],
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mem,
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flags,
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});
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} else {
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lower_load(
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ctx,
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insn,
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&inputs[..],
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outputs[0],
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|ctx, dst, elem_ty, mem| {
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let rd = dst.only_reg().unwrap();
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let is_float = ty_has_float_or_vec_representation(elem_ty);
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ctx.emit(match (ty_bits(elem_ty), sign_extend, is_float) {
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(1, _, _) => Inst::ULoad8 { rd, mem, flags },
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(8, false, _) => Inst::ULoad8 { rd, mem, flags },
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(8, true, _) => Inst::SLoad8 { rd, mem, flags },
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(16, false, _) => Inst::ULoad16 { rd, mem, flags },
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(16, true, _) => Inst::SLoad16 { rd, mem, flags },
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(32, false, false) => Inst::ULoad32 { rd, mem, flags },
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(32, true, false) => Inst::SLoad32 { rd, mem, flags },
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(32, _, true) => Inst::FpuLoad32 { rd, mem, flags },
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(64, _, false) => Inst::ULoad64 { rd, mem, flags },
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// Note that we treat some of the vector loads as scalar floating-point loads,
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// which is correct in a little endian environment.
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(64, _, true) => Inst::FpuLoad64 { rd, mem, flags },
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(128, _, true) => Inst::FpuLoad128 { rd, mem, flags },
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_ => panic!("Unsupported size in load"),
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});
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}
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},
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);
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let vec_extend = match op {
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Opcode::Sload8x8 => Some(VecExtendOp::Sxtl8),
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Opcode::Sload8x8Complex => Some(VecExtendOp::Sxtl8),
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Opcode::Uload8x8 => Some(VecExtendOp::Uxtl8),
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Opcode::Uload8x8Complex => Some(VecExtendOp::Uxtl8),
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Opcode::Sload16x4 => Some(VecExtendOp::Sxtl16),
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Opcode::Sload16x4Complex => Some(VecExtendOp::Sxtl16),
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Opcode::Uload16x4 => Some(VecExtendOp::Uxtl16),
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Opcode::Uload16x4Complex => Some(VecExtendOp::Uxtl16),
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Opcode::Sload32x2 => Some(VecExtendOp::Sxtl32),
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Opcode::Sload32x2Complex => Some(VecExtendOp::Sxtl32),
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Opcode::Uload32x2 => Some(VecExtendOp::Uxtl32),
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Opcode::Uload32x2Complex => Some(VecExtendOp::Uxtl32),
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_ => None,
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};
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if let Some(t) = vec_extend {
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let rd = dst.only_reg().unwrap();
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ctx.emit(Inst::VecExtend {
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t,
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rd,
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rn: rd.to_reg(),
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high_half: false,
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});
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}
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},
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);
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}
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}
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Opcode::Store
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@@ -1376,19 +1391,30 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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.memflags(insn)
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.expect("Store instruction should have memflags");
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let mem = lower_address(ctx, elem_ty, &inputs[1..], off);
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let rd = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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let dst = put_input_in_regs(ctx, inputs[0]);
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ctx.emit(match (ty_bits(elem_ty), is_float) {
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(1, _) | (8, _) => Inst::Store8 { rd, mem, flags },
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(16, _) => Inst::Store16 { rd, mem, flags },
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(32, false) => Inst::Store32 { rd, mem, flags },
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(32, true) => Inst::FpuStore32 { rd, mem, flags },
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(64, false) => Inst::Store64 { rd, mem, flags },
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(64, true) => Inst::FpuStore64 { rd, mem, flags },
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(128, _) => Inst::FpuStore128 { rd, mem, flags },
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_ => panic!("Unsupported size in store"),
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});
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if elem_ty == I128 {
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let mem = lower_pair_address(ctx, &inputs[1..], off);
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ctx.emit(Inst::StoreP64 {
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rt: dst.regs()[0],
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rt2: dst.regs()[1],
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mem,
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flags,
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});
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} else {
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let rd = dst.only_reg().unwrap();
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let mem = lower_address(ctx, elem_ty, &inputs[1..], off);
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ctx.emit(match (ty_bits(elem_ty), is_float) {
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(1, _) | (8, _) => Inst::Store8 { rd, mem, flags },
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(16, _) => Inst::Store16 { rd, mem, flags },
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(32, false) => Inst::Store32 { rd, mem, flags },
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(32, true) => Inst::FpuStore32 { rd, mem, flags },
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(64, false) => Inst::Store64 { rd, mem, flags },
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(64, true) => Inst::FpuStore64 { rd, mem, flags },
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(128, _) => Inst::FpuStore128 { rd, mem, flags },
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_ => panic!("Unsupported size in store"),
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});
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}
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}
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Opcode::StackAddr => {
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@@ -386,3 +386,130 @@ block0(v0: i64, v1: i64, v2: i64):
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; nextln: ldrsh x0, [x0]
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %i128(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0
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store.i128 v1, v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: ldp x2, x1, [x1]
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; nextln: stp x2, x1, [x0]
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; nextln: mov x0, x2
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %i128_imm_offset(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0+16
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store.i128 v1, v0+16
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: ldp x2, x1, [x1, #16]
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; nextln: stp x2, x1, [x0, #16]
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; nextln: mov x0, x2
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %i128_imm_offset_large(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0+504
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store.i128 v1, v0+504
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: ldp x2, x1, [x1, #504]
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; nextln: stp x2, x1, [x0, #504]
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; nextln: mov x0, x2
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %i128_imm_offset_negative_large(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0-512
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store.i128 v1, v0-512
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return v1
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}
|
||||
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: mov x1, x0
|
||||
; nextln: ldp x2, x1, [x1, #-512]
|
||||
; nextln: stp x2, x1, [x0, #-512]
|
||||
; nextln: mov x0, x2
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
function %i128_add_offset(i64) -> i128 {
|
||||
block0(v0: i64):
|
||||
v1 = iadd_imm v0, 32
|
||||
v2 = load.i128 v1
|
||||
store.i128 v2, v1
|
||||
return v2
|
||||
}
|
||||
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: mov x1, x0
|
||||
; nextln: ldp x2, x1, [x1, #32]
|
||||
; nextln: stp x2, x1, [x0, #32]
|
||||
; nextln: mov x0, x2
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
function %i128_32bit_sextend_simple(i32) -> i128 {
|
||||
block0(v0: i32):
|
||||
v1 = sextend.i64 v0
|
||||
v2 = load.i128 v1
|
||||
store.i128 v2, v1
|
||||
return v2
|
||||
}
|
||||
|
||||
; TODO: We should be able to deduplicate the sxtw instruction
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sxtw x1, w0
|
||||
; nextln: ldp x2, x1, [x1]
|
||||
; nextln: sxtw x0, w0
|
||||
; nextln: stp x2, x1, [x0]
|
||||
; nextln: mov x0, x2
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
function %i128_32bit_sextend(i64, i32) -> i128 {
|
||||
block0(v0: i64, v1: i32):
|
||||
v2 = sextend.i64 v1
|
||||
v3 = iadd.i64 v0, v2
|
||||
v4 = iadd_imm.i64 v3, 24
|
||||
v5 = load.i128 v4
|
||||
store.i128 v5, v4
|
||||
return v5
|
||||
}
|
||||
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: mov x2, x0
|
||||
; nextln: add x2, x2, x1, SXTW
|
||||
; nextln: ldp x3, x2, [x2, #24]
|
||||
; nextln: add x0, x0, x1, SXTW
|
||||
; nextln: stp x3, x2, [x0, #24]
|
||||
; nextln: mov x0, x3
|
||||
; nextln: mov x1, x2
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
@@ -276,3 +276,167 @@ block0(v0: b1):
|
||||
|
||||
return v0, v137
|
||||
}
|
||||
|
||||
|
||||
|
||||
function %i128_stack_store(i128) {
|
||||
ss0 = explicit_slot 16
|
||||
|
||||
block0(v0: i128):
|
||||
stack_store.i128 v0, ss0
|
||||
return
|
||||
}
|
||||
; TODO: Codegen improvement opportunities: This should be just a stp x0, x1, [sp, #-16]
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #16
|
||||
; nextln: mov x2, sp
|
||||
; nextln: stp x0, x1, [x2]
|
||||
; nextln: add sp, sp, #16
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
|
||||
|
||||
function %i128_stack_store_slot_offset(i128) {
|
||||
ss0 = explicit_slot 16, offset 16
|
||||
|
||||
block0(v0: i128):
|
||||
stack_store.i128 v0, ss0
|
||||
return
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #16
|
||||
; nextln: mov x2, sp
|
||||
; nextln: stp x0, x1, [x2]
|
||||
; nextln: add sp, sp, #16
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
|
||||
|
||||
function %i128_stack_store_inst_offset(i128) {
|
||||
ss0 = explicit_slot 16
|
||||
ss1 = explicit_slot 16
|
||||
|
||||
block0(v0: i128):
|
||||
stack_store.i128 v0, ss1+16
|
||||
return
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #32
|
||||
; nextln: add x2, sp, #32
|
||||
; nextln: stp x0, x1, [x2]
|
||||
; nextln: add sp, sp, #32
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
function %i128_stack_store_big(i128) {
|
||||
ss0 = explicit_slot 100000
|
||||
ss1 = explicit_slot 8
|
||||
|
||||
block0(v0: i128):
|
||||
stack_store.i128 v0, ss0
|
||||
return
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: movz w16, #34480
|
||||
; nextln: movk w16, #1, LSL #16
|
||||
; nextln: sub sp, sp, x16, UXTX
|
||||
; nextln: mov x2, sp
|
||||
; nextln: stp x0, x1, [x2]
|
||||
; nextln: movz w16, #34480
|
||||
; nextln: movk w16, #1, LSL #16
|
||||
; nextln: add sp, sp, x16, UXTX
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
|
||||
function %i128_stack_load() -> i128 {
|
||||
ss0 = explicit_slot 16
|
||||
|
||||
block0:
|
||||
v0 = stack_load.i128 ss0
|
||||
return v0
|
||||
}
|
||||
; TODO: Codegen improvement opportunities: This should be just a ldp x0, x1, [sp, #-16]
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #16
|
||||
; nextln: mov x0, sp
|
||||
; nextln: ldp x1, x0, [x0]
|
||||
; nextln: mov x2, x0
|
||||
; nextln: mov x0, x1
|
||||
; nextln: mov x1, x2
|
||||
; nextln: add sp, sp, #16
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
function %i128_stack_load_slot_offset() -> i128 {
|
||||
ss0 = explicit_slot 16, offset 16
|
||||
|
||||
block0:
|
||||
v0 = stack_load.i128 ss0
|
||||
return v0
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #16
|
||||
; nextln: mov x0, sp
|
||||
; nextln: ldp x1, x0, [x0]
|
||||
; nextln: mov x2, x0
|
||||
; nextln: mov x0, x1
|
||||
; nextln: mov x1, x2
|
||||
; nextln: add sp, sp, #16
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
|
||||
function %i128_stack_load_inst_offset() -> i128 {
|
||||
ss0 = explicit_slot 16
|
||||
ss1 = explicit_slot 16
|
||||
|
||||
block0:
|
||||
v0 = stack_load.i128 ss1+16
|
||||
return v0
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: sub sp, sp, #32
|
||||
; nextln: add x0, sp, #32
|
||||
; nextln: ldp x1, x0, [x0]
|
||||
; nextln: mov x2, x0
|
||||
; nextln: mov x0, x1
|
||||
; nextln: mov x1, x2
|
||||
; nextln: add sp, sp, #32
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
|
||||
|
||||
function %i128_stack_load_big() -> i128 {
|
||||
ss0 = explicit_slot 100000
|
||||
ss1 = explicit_slot 8
|
||||
|
||||
block0:
|
||||
v0 = stack_load.i128 ss0
|
||||
return v0
|
||||
}
|
||||
; check: stp fp, lr, [sp, #-16]!
|
||||
; nextln: mov fp, sp
|
||||
; nextln: movz w16, #34480
|
||||
; nextln: movk w16, #1, LSL #16
|
||||
; nextln: sub sp, sp, x16, UXTX
|
||||
; nextln: mov x0, sp
|
||||
; nextln: ldp x1, x0, [x0]
|
||||
; nextln: mov x2, x0
|
||||
; nextln: mov x0, x1
|
||||
; nextln: mov x1, x2
|
||||
; nextln: movz w16, #34480
|
||||
; nextln: movk w16, #1, LSL #16
|
||||
; nextln: add sp, sp, x16, UXTX
|
||||
; nextln: ldp fp, lr, [sp], #16
|
||||
; nextln: ret
|
||||
|
||||
136
cranelift/filetests/filetests/runtests/i128-load-store.clif
Normal file
136
cranelift/filetests/filetests/runtests/i128-load-store.clif
Normal file
@@ -0,0 +1,136 @@
|
||||
test run
|
||||
target x86_64 machinst
|
||||
target aarch64
|
||||
|
||||
function %i128_stack_store_load(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 16
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
stack_store.i128 v2, ss0
|
||||
v3 = stack_load.i128 ss0
|
||||
|
||||
v4 = icmp.i128 eq v2, v3
|
||||
return v4
|
||||
}
|
||||
; run: %i128_stack_store_load(0, 0) == true
|
||||
; run: %i128_stack_store_load(-1, -1) == true
|
||||
; run: %i128_stack_store_load(-1, 0) == true
|
||||
; run: %i128_stack_store_load(0, -1) == true
|
||||
; run: %i128_stack_store_load(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_stack_store_load(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_stack_store_load(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
|
||||
|
||||
function %i128_stack_store_load_offset(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 16, offset 16
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
stack_store.i128 v2, ss0
|
||||
v3 = stack_load.i128 ss0
|
||||
|
||||
v4 = icmp.i128 eq v2, v3
|
||||
return v4
|
||||
}
|
||||
; run: %i128_stack_store_load_offset(0, 0) == true
|
||||
; run: %i128_stack_store_load_offset(-1, -1) == true
|
||||
; run: %i128_stack_store_load_offset(-1, 0) == true
|
||||
; run: %i128_stack_store_load_offset(0, -1) == true
|
||||
; run: %i128_stack_store_load_offset(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_stack_store_load_offset(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_stack_store_load_offset(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
|
||||
|
||||
function %i128_stack_store_load_inst_offset(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 16
|
||||
ss1 = explicit_slot 16
|
||||
ss2 = explicit_slot 16
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
stack_store.i128 v2, ss1+16
|
||||
v3 = stack_load.i128 ss1+16
|
||||
|
||||
v4 = icmp.i128 eq v2, v3
|
||||
return v4
|
||||
}
|
||||
; run: %i128_stack_store_load_inst_offset(0, 0) == true
|
||||
; run: %i128_stack_store_load_inst_offset(-1, -1) == true
|
||||
; run: %i128_stack_store_load_inst_offset(-1, 0) == true
|
||||
; run: %i128_stack_store_load_inst_offset(0, -1) == true
|
||||
; run: %i128_stack_store_load_inst_offset(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_stack_store_load_inst_offset(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_stack_store_load_inst_offset(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
|
||||
|
||||
; Some arches (aarch64) try to encode the offset into the load/store instructions
|
||||
; test that we spill if the offset is too large and doesn't fit in the instruction
|
||||
function %i128_stack_store_load_big_offset(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 100000
|
||||
ss1 = explicit_slot 8
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
stack_store.i128 v2, ss0
|
||||
v3 = stack_load.i128 ss0
|
||||
|
||||
v4 = icmp.i128 eq v2, v3
|
||||
return v4
|
||||
}
|
||||
; run: %i128_stack_store_load_big_offset(0, 0) == true
|
||||
; run: %i128_stack_store_load_big_offset(-1, -1) == true
|
||||
; run: %i128_stack_store_load_big_offset(-1, 0) == true
|
||||
; run: %i128_stack_store_load_big_offset(0, -1) == true
|
||||
; run: %i128_stack_store_load_big_offset(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_stack_store_load_big_offset(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_stack_store_load_big_offset(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
|
||||
|
||||
|
||||
function %i128_store_load(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 16
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
v3 = stack_addr.i64 ss0
|
||||
store.i128 v2, v3
|
||||
v4 = load.i128 v3
|
||||
|
||||
v5 = icmp.i128 eq v2, v4
|
||||
return v5
|
||||
}
|
||||
; run: %i128_store_load(0, 0) == true
|
||||
; run: %i128_store_load(-1, -1) == true
|
||||
; run: %i128_store_load(-1, 0) == true
|
||||
; run: %i128_store_load(0, -1) == true
|
||||
; run: %i128_store_load(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_store_load(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_store_load(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
|
||||
|
||||
function %i128_store_load_offset(i64, i64) -> b1 {
|
||||
ss0 = explicit_slot 32
|
||||
|
||||
block0(v0: i64,v1: i64):
|
||||
v2 = iconcat v0, v1
|
||||
|
||||
v3 = stack_addr.i64 ss0
|
||||
store.i128 v2, v3+16
|
||||
v4 = load.i128 v3+16
|
||||
|
||||
v5 = icmp.i128 eq v2, v4
|
||||
return v5
|
||||
}
|
||||
; run: %i128_store_load_offset(0, 0) == true
|
||||
; run: %i128_store_load_offset(-1, -1) == true
|
||||
; run: %i128_store_load_offset(-1, 0) == true
|
||||
; run: %i128_store_load_offset(0, -1) == true
|
||||
; run: %i128_store_load_offset(0x01234567_89ABCDEF, 0xFEDCBA98_76543210) == true
|
||||
; run: %i128_store_load_offset(0x06060606_06060606, 0xA00A00A0_0A00A00A) == true
|
||||
; run: %i128_store_load_offset(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == true
|
||||
Reference in New Issue
Block a user