Removed extraneous newlines

lib/cretonne/src/dominator_tree.rs

@@ -8,7 +8,6 @@ use packed_option::PackedOption;
 use std::cmp;
 use std::mem;
 use timing;
-
 use std::cmp::Ordering;
 use std::vec::Vec;
 

lib/cretonne/src/isa/arm32/mod.rs

@@ -14,7 +14,6 @@ use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
 use std::fmt;
-
 use std::boxed::Box;
 
 #[allow(dead_code)]

lib/cretonne/src/isa/arm64/mod.rs

@@ -14,7 +14,6 @@ use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
 use std::fmt;
-
 use std::boxed::Box;
 
 #[allow(dead_code)]

lib/cretonne/src/isa/intel/mod.rs

@@ -16,7 +16,6 @@ use regalloc;
 use result;
 use timing;
 use std::fmt;
-
 use std::boxed::Box;
 
 #[allow(dead_code)]

lib/cretonne/src/isa/mod.rs

@@ -54,7 +54,6 @@ use result;
 use timing;
 use isa::enc_tables::Encodings;
 use std::fmt;
-
 use std::boxed::Box;
 
 #[cfg(build_riscv)]

lib/cretonne/src/isa/riscv/mod.rs

@@ -14,7 +14,6 @@ use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
 use std::fmt;
-
 use std::boxed::Box;
 
 #[allow(dead_code)]

lib/cretonne/src/simple_gvn.rs

@@ -6,7 +6,6 @@ use dominator_tree::DominatorTree;
 use ir::{InstructionData, Function, Inst, Opcode, Type};
 use scoped_hash_map::ScopedHashMap;
 use timing;
-
 use std::vec::Vec;
 
 /// Test whether the given opcode is unsafe to even consider for GVN.

lib/cretonne/src/topo_order.rs

@@ -3,7 +3,6 @@
 use entity::SparseSet;
 use dominator_tree::DominatorTree;
 use ir::{Ebb, Layout};
-
 use std::vec::Vec;
 
 /// Present EBBs in a topological order such that all dominating EBBs are guaranteed to be visited