[AArch64] Merge 32- and 64-bit FPUOp1 (#4031)

2022-04-14 22:00:48 +01:00
parent 9a02320dd4
commit dd442a4d2f
7 changed files with 237 additions and 206 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst.isle
+++ b/cranelift/codegen/src/isa/aarch64/inst.isle
@@ -317,6 +317,7 @@
       ;; 1-op FPU instruction.
       (FpuRR
        (fpu_op FPUOp1)
+        (size ScalarSize)
        (rd WritableReg)
        (rn Reg))

@@ -940,12 +941,9 @@
 ;; A floating-point unit (FPU) operation with one arg.
 (type FPUOp1
  (enum
-    (Abs32)
-    (Abs64)
-    (Neg32)
-    (Neg64)
-    (Sqrt32)
-    (Sqrt64)
+    (Abs)
+    (Neg)
+    (Sqrt)
    (Cvt32To64)
    (Cvt64To32)
 ))